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The QDID PUF is an innovative hardware experience designed to generate a unique cryptographic identity through quantum tunneling current variations. Utilizing standard CMOS processes, it taps into randomness deriving from oxide thickness variations and defect distribution in gate oxide, creating a robust hardware root-of-trust. This enables the establishment of secure architectures by providing on-the-fly identity generation that does not rely on memory storage, making it resistant to side-channel and machine learning attacks. The QDID PUF is especially noteworthy for its high entropy seed generation, supporting customizable security strengths up to 256 bits, and is designed with built-in resistance against secret leakage through advanced countermeasures. The technology is thoroughly tested under diverse environmental conditions, consistently maintaining reliability and longevity, and has achieved extensive verification across major fabs including TSMC, GF, and UMC across various process nodes in Bulk CMOS, FDSOI, and FinFET technologies. It enables key generation and device authentication, serving as a cornerstone for secure provisioning and post-quantum cryptography, thus supporting various applications in device identification, supply chain security, and more. Successfully verified under NIST standards, QDID PUF ensures excellent performance across voltage, temperature, and ageing tests, offering a robust solution for future-proof IoT device integration.
Fault Injection Detection IP from Crypto Quantique provides a defense mechanism against physical attacks on silicon through hardware-level fault detection. By monitoring anomalies in clock, power, and thermal parameters, this IP enables secure embedded systems to proactively respond to potential glitches, enhancing overall security. Its modular design allows easy integration with existing crypto IPs and secure FSMs, providing additional layers of protection for sensitive embedded devices. Critical for automotive, medical, and industrial applications, the IP helps in meeting security standards like ISO/SAE 21434 and IEC 62443. This IP provides flexible configuration of sensitivity levels and pulse durations to tailor defenses to specific threat models, ensuring minimal impact on performance while maintaining a high level of security.
QRoot Lite is designed for resource-constrained MCUs and IoT devices, offering a lightweight, configurable root-of-trust. Built on TCG MARS specification, it simplifies integration and reduces cost, ensuring secure boot, attestation, and key protection. The IP minimizes silicon and power requirements, making it ideal for low-power device applications. Its flexible architecture allows seamless inclusion into SoC designs, offering not only secure boot and firmware validation but also tamper protection and unauthorized access prevention during device operation. QRoot Lite provides secure attestation using Trusted Computing Group standards, making it an excellent choice for meeting compliance and security standards in smart sensors, medical devices, and gateway products. It supports integration with standard industry interfaces and is optimized for low silicon footprint, reinforcing its versatility in diverse IoT environments.
Crypto Quantique's Cryptographic Cores are scalable cryptographic accelerators offering comprehensive algorithm coverage including AES, SHA, ECC, Ascon, and emerging post-quantum cryptography standards like Kyber and Dilithium. These cores are engineered for high-performance deployments in secure SoC designs, optimized for low-area and low-latency operation. Designed to resist side-channel and fault injection attacks, these cores provide a secure foundation for enforcement of secure boot, identity verification, and encryption protocols across various device implementations. This ensures reliable cryptographic operations in industry sectors like IoT, automotive, and medical devices. The cores offer configurable integration options, accommodating a variety of interface standards such as APB and AXI, which ease incorporation into existing development workflows. Focused on achieving compliance, these cores come with processes streamlined for regulatory certification, making them a pragmatic choice for forward-thinking system designs.
The Agile Secure Element is a configurable security enclave designed for integrating robust, flexible security features directly into SoC designs. It includes an embedded microprocessor and various cryptographic engines, supporting tasks like secure boot and trusted execution, making it an ideal tool for creating trusted zones in multi-core or subsystem-based SoC designs. With support for high-speed cryptographic operations and customizable architecture, the Agile Secure Element is prepared for regulatory compliance, ensuring capabilities align with standards like CRA and ISO. Its modular, certifiable design allows efficient security integration without the need for extensive modifications to existing systems. The IP features a rich set of cryptographic primitives and integration flexibility, accommodating standard interfaces like APB and AXI, which facilitates its adoption within various system architectures. The support for post-quantum cryptographic (PQC) implementations further enhances its readiness for future security requirements, ensuring next-generation SoC robustness, while maintaining efficient power and area ratios.
The True Random Number Generator (TRNG) IP is essential for generating high-quality entropy sources needed for secure cryptographic operations. NIST- and BSI-compliant, this product ensures secure key generation and other critical encryption operations, forming a foundational element for secure SoC and embedded systems. TRNG provides high throughput of up to 100 Mbit/s, supported by in-built health checks to maintain entropy quality over time and under various operating conditions. The TRNG offers digital and analog implementations, providing flexibility depending on performance requirements and integration specifics. Errored entropy output detection and conditioning ensure continuous operational integrity, making it ideal for secure boot and identity provision applications. With robust integration support, the TRNG IP fits seamlessly into diverse electronic environments, cementing its role in maintaining scalable and reliable cryptographic operations.
Digital PUF is a compact, logic-based Physical Unclonable Function tailored to provide trusted hardware identity for secure boot, key generation, and device authentication. Its small footprint is essential for embedding unclonable 128 or 256-bit identifiers into SoCs, ensuring minimal silicon overhead. Optimized for stability and reliability, Digital PUF features customizable security and reliability enhancements, including NIST-validated randomness tests, to comply with stringent security and audit requirements. Its design integrates seamlessly with SoC buses via standard interfaces, supporting easy integration into existing architectures. The IP leverages a logic-based entropy array to create a unique bitstring for each device, fortified by a built-in fuzzy extractor to facilitate error correction and secure communication, safeguarding systems from unauthorized access with high fidelity.
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