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The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
**Ceva-Waves Dragonfly platform** is a turnkey platform with optimized, low-power hardware IP and protocol software for implementing narrow-band IoT (NB-IoT) cellular modem SoCs. Extensions provide support for GNSS such as GPS and BeiDou and for sensor-fusion applications. The Ceva-Waves Dragonfly platform comprises hardware IP with an enhanced Ceva-BX1 processor, specific hardware accelerators, and SoC infrastructure IP. Software includes NB-IoT protocol stack for L1 through L3 functions including encryption and software PHY, a task-optimized RTOS, and optional GNSS receiver and control software, all executing on the Ceva-BX1. Pre-certified for 3GPP Release 15 CAT NB2, the solution is tuned for small footprint and extremely low power, yet has headroom for additional software-defined functions, such as sensor fusion. [**Learn more about Ceva-Waves Dragonfly>**](https://www.ceva-ip.com/product/ceva-waves-dragonfly/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_dragonfly_page)
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
**Ceva-Waves Wi-Fi platforms portfolio** provide a comprehensive selection of hardware IP and CPU-agnostic host software for energy-efficient SoC implementation of any of a wide range of Wi-Fi subsystems, from Wi-Fi 4 to Wi-Fi 7, for both client devices and access points. The portfolio includes a suite of pre-optimized solutions for various generations and configurations for specific Wi-Fi uses, power consumption levels, and price points, ranging from low-bandwidth IoT connectivity to high-bandwidth hubs. Embedded into one of the Ceva-Waves Links multi-protocol wireless platforms, the Ceva-Waves Wi-Fi IPs can efficiently co-exist with the Ceva-Waves Bluetooth IPs and/or Ceva-Waves UWB IP. The Ceva-Waves Wi-Fi platforms comprise hardware modem PHY IP that supports DSSS, CCK, OFDM and OFDMA modulations; optimized MAC IP that offloads MAC functions from the CPU; and a comprehensive selection of MAC protocol software stacks. The IP and software elements are further organized into three main solution profiles. * Wi-Fi IoT is for energy-efficient low-bandwidth connectivity for IoT devices, supporting 2.4GHz single band or dual/triple bands on 2.4/5/6 GHz for IEEE 802.11n, ax, or be (Wi-Fi 4, 6 or 7). * Wi-Fi High-Performance supports up to 160 MHz bands at 2.4, 5, or 6 GHz in either single-antenna or 2×2 MIMO mode for IEEE 802.11ax or be (Wi-Fi 6 or 7), and is intended for consumer media-streaming applications. * Wi-Fi Access Point supports 160 MHz bands and 2×2 MIMO for IEEE 802.11ax or be (Wi-Fi 6/6E/7), for applications such as media access points, gateways, and small-cell offload that must support up to hundreds of clients. The Ceva-Waves Wi-Fi platforms include a coexistence interface that permits highly efficient operation with the Ceva-Waves Bluetooth platforms. [**Learn more about Ceva-Waves Wi-Fi solution>**](https://www.ceva-ip.com/product/ceva-waves-wi-fi/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_wifi_page)
**Ceva-NeuPro-Nano** is a highly efficient and self-sufficient Edge NPU designed for Embedded ML applications. This Edge NPU, which is the smallest of **Ceva-NeuPro's NPU product family**, delivers the optimal balance of ultra-low power and high performance in a small area to efficiently execute Embedded ML workloads across AIoT product categories, including Hearables, Wearables, Home Audio, Smart Home, Smart Factory, and more. Ranging from 10 GOPS up to 200 GOPS per core, Ceva-NeuPro-Nano is designed to enable always-on audio, voice, vision, and sensing use cases in battery-operated devices across a wide array of end markets. Ceva-NeuPro-Nano makes the possibilities enabled by Embedded ML into realities for low cost, energy efficient AIoT devices. [**Learn more about Ceva-Neupro-Nano salution>**](https://www.ceva-ip.com/product/ceva-neupro-nano/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_neupro-nano_page)
**Ceva-BX2 baseband processor IP** handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming. It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size. Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators. The Ceva-BX2 combines the capabilities of signal processing and control-code execution into a single, compact DSP. Computational speed comes from quad-32×32/octal-16×16 MACs with added support for 16×8 and 8×8 MAC operations, organized into two parallel compute engines within an 11-stage pipeline. Each compute engine can add optional half- and single-precision IEEE floating-point units. These resources are directed by a five-way VLIW instruction set architecture with optimizations for single-instruction-multiple-data (SIMD) operation, including a hardware loop buffer for kernel execution. Efficient execution of control code is aided by dynamic branch prediction and a branch target cache. On signal-processing tasks the Ceva-BX2 can reach up to 16 GMACs per second, and on control workloads it can achieve up to 5.46 CoreMark/MHz. The hardware design is optimized for speed, achieving 2 GHz operation implemented in a TSMC 7nm process node with only common standard cells and memory compilers. [**Learn more about Ceva-BX2>**](https://www.ceva-ip.com/product/ceva-bx2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_bx2_page)
**Ceva-NeuPro-M** is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, with an exceptional power efficiency of up to 3500 Tokens-per-Second/Watt for a Llama 2 and 3.2 models The Ceva-NeuPro-M Neural Processing Unit (NPU) IP family delivers exceptional energy efficiency tailored for edge computing while offering scalable performance to handle AI models with over a billion parameters. Its innovative architecture, which has won multiple awards, introduces significant advancements in power efficiency and area optimization, enabling it to support massive machine-learning networks, advanced language and vision models, and multi-modal generative AI. With a processing range of 4 to 200 TOPs per core and leading area efficiency, the Ceva-NeuPro-M optimizes key AI models seamlessly. A robust tool suite complements the NPU by streamlining hardware implementation, model optimization, and runtime module composition. The Ceva-NeuPro-M NPU IP family is a highly scalable, complete hardware and software IP solution for embedding high performance AI processing in SoCs across a wide range of edge AI applications. The heart of the NeuPro-M NPU architecture is the computational unit. Scalable from 4 to 20 TOPs, a single computational unit comprises a multiple-MAC parallel neural computing engine, activation and sparsity control units, an independent programable vector-processing unit, plus local shared L1 memory and a local unit controller. A core may contain up to eight of these computational units, along with a shared Common Subsystem comprising functional-safety, data-compression, shared L2 memory, and system interfaces. These NPU cores may be grouped into multi-core clusters to reach performance levels in excess of 2000 TOPS. [**Learn more about Ceva's NeuPro-M solution>**](https://www.ceva-ip.com/product/ceva-neupro-m/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=neupro_m_page)
**Ceva-XC23** is the most powerful DSP core available today for communications applications. Ceva-XC23 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, more efficient wireless infrastructure Targeted for 5G and 5G-Advanced workloads, the Ceva-XC23 has two independent execution threads and a dynamic scheduled vector-processor, providing not only unprecedented processing power but unprecedented utilization on real-world 5G multitasking workloads. The Ceva-XC23, based on the advanced Ceva-XC20 architecture, features dual execution threads with independent memory subsystems and caches. It includes a shared Vector Computation Unit (VCU) with four engines, dynamically allocated to maximize utilization and reduce contention. The VCU consist of two arithmetic engines, with one non-linear engine and one move-and-scale engine that supports 128 16×16 MACs. The architecture ensures efficient data handling with wide memory connections and dedicated DMA engines [**Learn more about Ceva-XC23>**](https://www.ceva-ip.com/product/ceva-xc23/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc23_page)
**Ceva-PentaG RAN platform** is a modular, optimized hardware and software IP for implementing L1 PHY baseband processing in 5G base station and other cellular infrastructure SoCs. Employing Ceva’s highest-performance DSP cores and dedicated hardware accelerators teamed with optimized software, the Ceva-PentaG RAN platform is in use by 5G industry incumbents, and can substantially reduce development time and risk for new entrants. Highly scalable, it provides high-performance processing for all major signal and control chains for macro cell base stations, small cells, and remote radio units, supporting any Open-RAN high-PHY/low-PHY split. Special attention is given to massive MIMO, beamforming, and the specific needs of non-terrestrial network (NTN) gateways and satellites. The Ceva-PentaG RAN platform comprises both hardware IP – Ceva-XC22 vector DSP cores, optimized accelerators, and supporting software, all with proven interoperability. Blocks support processing for each signal and control chain in the user’s application. This approach yields unmatched power-performance-area figures of merit for completed designs. For base-station SoCs, all main signal and control chains are supported, including frequency-domain chains such as FFTs and equalization, symbol/bit-domain tasks including forward error correction, massive MIMO processing and beamforming, and Open-RAN fronthaul/backhaul processing. Modules can be assembled to create optimal hardware across a wide range of configurations from massive MIMO macro cell base stations to small cells. [**Learn more about Ceva-PentaG RAN>**](https://www.ceva-ip.com/product/ceva-pentag-ran/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag_ran_page)
**Ceva-BX1 audio digital signal controller IP** handles both modest signal-processing and control workloads with up to 8 GMACs per second performance and high-level-language programming. Yet it is power-efficient enough for always-on applications and use in wearables and TWS earbuds. The Ceva-BX1 supports a range of integer and floating-point data types for a wide range of applications, from audio signal processing to light AI workloads, with remarkably compact code size. Optimized high-speed interfaces expedite Ceva-BX1 connection to coprocessors or accelerators, and a rich software partners ecosystem provide ready-to-use application-level solutions The Ceva-BX1 combines the capabilities of signal processing and control-code execution into a single compact, low-power DSP core. Computational speed comes from dual-32×32 and quad-16×16 MACs with added support for 16×8 and 8×8 MAC operations, implemented in an 11-stage pipeline. A floating-point unit supporting half, single, and double-precision IEEE floating-point is optional. These resources are directed by a four-way VLIW instruction set architecture with optimizations for single-instruction-multiple-data (SIMD) operation. A hardware loop buffer speeds kernel code execution, while efficient execution of control code is aided by dynamic branch prediction and a branch target buffer. Trusted execution modes enable secure operation. On signal-processing tasks the Ceva-BX1 can reach up to 8 GMACs per second, and on control workloads it can achieve up to 4.41 CoreMark/MHz. The hardware design is optimized for speed, achieving 2 GHz operation when implemented in a TSMC 7nm process node using only common standard cells and memory compilers. [**Learn more about Ceva-BX1 solution>**](https://www.ceva-ip.com/product/ceva-bx1/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_bx1_page)
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