Our IP is hosted on Silicon Hub, letting you download trial versions instantly. Browse our IP below, or find out more.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
Certus Semiconductor's Analog I/O offerings bring ultra-low capacitance and robust ESD protection to the forefront. These solutions are crafted to handle extreme voltage conditions while securing signal integrity by minimizing impedance mismatches. Key features include integrated ESD and power clamps, support for broad RF frequencies, and the ability to handle signal swings below ground. Ideal for high-speed RF applications, these Analog I/Os provide superior protection and performance, aligning with the most demanding circuit requirements.
Specializing in ESD protections, Certus Semiconductor offers highly adaptive solutions that meet various operational demands. These circuits provide enduring defense against ESD threats, surpassing traditional HBM and CDM specifications. Capabilities include low capacitance solutions and customized protections tailored to endure voltages between -18V to +30V. These ESD circuits are integrated with specialized features like Rad-Hard technology, high-temperature resilience, and enhanced burst immunity, setting a standard for highly secure semiconductor solutions in harsh environments.
Certus Semiconductor's RF/Analog solutions encompass state-of-the-art ultra-low power wireless front-end technologies. These include silicon-proven RF IPs, full-chip RF products, and next-generation wireless IPs. The RF IPs are compatible with various process nodes, offering comprehensive transceiver solutions integrated with digital controls and modern power management strategies. Specialized for wireless applications, these products include transceivers for LTE, Wifi, GNSS, and Zigbee, each meticulously designed to enhance communication reliability and efficiency in any technology node, from 12nm to 65nm processes.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications. Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications. The I/O macro seamlessly integrates with the TSMC 1.0V I/O Library, sharing a compatible VDDA and VSSA bus structure for streamlined power management. Designed with a 14-bondpad ESD macro, including two differential pairs and dedicated power/ground cells, it provides a robust 0.8V VDDA power domain with a 0V ground reference. Engineered for reliability, the library avoids minimum-width metal traces and adheres to enhanced via/contact recommendations for long-term durability. With Cadence OA database compatibility, the library supports Spectre and auCdl views, enabling seamless simulation, LVS verification, and integration into standard design flows.
This library is a production-quality, silicon-proven custom Die-to-Die high speed interface available in TSMC’s 16nm process. The I/O cell is bidirectional, has two modes of operation: standard full rail to rail swing, or a custom low noise pseudo-differential interface. The RX cells have a weak pull-down feature.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology. The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter. The library also includes a 1.2V ODIO with two slew rate options as well as a 3.3V ODIO with a 5V tolerance. All I/Os have highly programmable POC options and active pull up/down. The library is compliant with ANSI/JEDEC/ESDA JS-001-2014 ESD standards.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor. Four selectable drive strengths are offered (25 235MHz @ 1.8V, 10pF) to optimize across SS) currents & power. The output driver exhibits 50 ((20%) termination across PVT to reduce reflections at higher operating frequencies. Supply cells for VDDIO, VREF, and core VDD include necessary built in ESD circuitry. A 5VI2C / SMBUS open drain (fail safe) cell, 5V OTP, programming gate cell and 1.8V & 3.3V analog cells with ESD protection are included. The library features protection break cells to allow for separate grounds while maintaining ESD robustness. ESD design targets 2kV HBM, & 50 0V CDM, yet this library has constantly demonstrated 4kV HBM. This library can also support 2kV IEC 6100-4-2 system ESD with appropriate integration.
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme. The functional cells in the library (GPIO & ODIO) feature an Output Enable pin which, when de-asserted, place the I/O in a HiZ state, and can control multiple modes of output operation with the Output Mode Control pins. The input RX path for this library all have selectable operations between a Schmitt trigger input with hysteresis, a standard buffer with no hysteresis, and a low input voltage mode that can receive a voltage level much lower than the I/O supply without causing metastability or large leakage current. The library has no poly orientation limitations and can be used in any orientation. The library cells are only built up to metal three, but include an metal 4 pad anchor that can be overlaid with either a wirebond or connected to a BUMP. ESD design level are 2kV HBM, 500V CDM and +/-125mA Latch-up.
This flip-chip compatible library in Dongbu HiTek 130nm features a fail-safe GPIO, two standard GPIOs, a 5V GPI, and 5V I2C-compliant ODIO. The GFGPIO is a highly configurable 5V tolerant, multi-voltage, multi=-protocol I/O. The standard GPIO, both regular and reduced footprint, in this library is a highly configurable 5V tolerant, multi-voltage, multi-protocol I/O. The library’s GPI is a highly configurable general-purpose input cell which features three selectable input modes, three selectable resistive termination options, and a wide supply range. The library’s ODIO is a 5V I2C-compliant ODIO which features standard mode, fast-mode, and fast-mode plus, as well as selectable input modes, drive strength control and robust 2kV HBM protection. The library also supports I3C, SPI and QSPI standards. The library includes all layout and support cells. ESD targets are 2kV HBM and 500V CDM.
This silicon-proven Wirebond compatible library in Dongbu HiTek 110nm features a multi-voltage, multi-standard General Purpose Input Output with an Open-Drain Input Output capability, that targets the I2C standard. The library is built as a Fail- Safe I/O design. There is no poly-orientation for this library. The library features an Analog Mux, which allows for core direct access to the bondpad, either to drive externally a signal or receive a signal from the PAD. The I/O Library is compliant with standards regarding all 1.2V, 1.8V, and 3.3V operation. The library can support various standards, including I3C, I2C, SPI and QSPI. ESD targets are 2kV HMB and 500V CDM.
This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity. The library includes 1.83.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD. Complemented by a full set of power, filler, corner, and transition cells, the VZ55 library enables reliable padring construction across mixed-signal designs. With wide voltage support, industrial temperature range (-40C to 125C), and cross-domain ESD protection, VZ55 provides a scalable, production-ready I/O platform for advanced SoC integration.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!