Is this your business? Claim it to manage your IP and profile
The Low Power ARM AV Player is built for versatility and low power usage, ideal for application in mobile consumer electronics and digital advertising environments. This solution integrates several features into a compact design, including an H.264 video decoder, AAC audio decoder, and a user-friendly GUI operating over Linux environments. Utilizing the Xilinx Zynq 7010 FPGA for core processing, it makes full use of ARM's processor capabilities. This ensures seamless interaction of AV components while allowing further customization through available FPGA logic resources.
This H.264 decoder core is tailored for low power and low latency applications across industrial, medical, and consumer electronics sectors. It facilitates high-efficiency decoding of AVC Baseline Profile videos up to 1080p30, perfect for devices that require minimal power consumption. With support for error resiliency features like Arbitrary Slice Ordering and Flexible Macroblock Ordering, it ensures robustness even over unreliable networks. Designed for easy integration with both FPGA and ASIC platforms, the core is fully compliant with H.264 standards, delivering high-quality video output sustainably and effectively.
The QDR IV XP PHY + Memory Controller leverages high-performance capabilities for advanced networking and communication systems. Designed to optimize data flow at high frequencies, this controller interfaces effectively with Stratix V FPGAs, achieving superior memory speeds. Its advanced calibration and de-skew features ensure precise interaction between user and memory interfaces, enhancing performance for high-speed applications such as network processing. Configured for two bidirectional ports and featuring on-die termination, this controller enables robust and reliable data transactions critical for maintaining system efficiency in demanding environments.
The H.264 Software Video Encoder is designed as a low power yet efficient software solution for video encoding on diverse devices, utilized in sectors like industrial monitoring and consumer electronics. Highly adaptable, it processes AVC Baseline Profile videos up to 1080p, supporting single-pass variable and constant bit rates. The encoder guarantees excellent video quality through optimized mode decisions and an in-loop deblocking filter, making it ideal for surveillance and portable video recording systems. Its architecture is compatible with a wide range of ARM processors, reinforcing its utility across various platforms.
The H.264 UHD Hi422 Intra Video Decoder is a cutting-edge hardware solution for decoding ultra-high-definition video with exceptional quality and speed. Targeting industries such as medical imaging, broadcast, and enterprise applications, this decoder excels in delivering low-latency and high-precision video output. It supports the H.264 Hi422 profile up to Level 5.1, capable of processing signals as large as 3840x2160p at 30 frames per second. The decoder's design ensures no compromise in video quality, particularly noted in its support for 10-bit color depth and YUV 4:2:2 chroma subsampling, which enhances image detail critical for applications like surgery videos.
The H.264 UHD Hi422 Intra Video Encoder offers robust encoding for high-definition video, perfecting the balance between quality and speed for critical industries such as broadcast and medical imaging. This encoder is designed to work in tandem with its counterpart decoder for seamless, low-latency video processing. Supporting 3840x2160p video at 30fps, the encoder maintains high video quality with precise color fidelity using 10-bit color and YUV 4:2:2 chroma formats. Implemented on the versatile Xilinx Zynq-7000 platform, it optimizes logic and RAM utilization, ensuring optimal performance while leaving room for additional system enhancements.
The MPEG-2 Software Video Encoder is a robust solution for encoding video in industrial and medical fields. Supporting MPEG-2 Main Profile IPB encoding, the encoder is well-suited for broadcast and video archiving tasks. It ensures high-quality video through rate distortion optimization, even at low bit rates, while efficiently managing power usage. This software-based encoder runs seamlessly on Linux and Windows environments and is compatible with various ARM processors, offering flexibility for a range of embedded systems and portable devices, such as recorders and PACS in healthcare.
The I2C Master/Slave Controller Core simplifies data transfer over two-wire serial buses, supporting both master and slave operational modes. Designed for simplicity and efficiency, this controller provides flexible system integration via various bus interfaces and ensures robust communication through features like multi-master arbitration and clock synchronization. With its compatibility with standard I2C specifications, it adapts to a wide range of embedded systems, supporting data transfer speeds from 100 Kbps up to 400 Kbps. This IP core is ideally suited for consumer electronics and industrial automation systems.
The PCIe Gen1/2 PHY from Atria Logic offers a complete suite of physical layer design services that extend across the PCI Express specifications, providing excellent solutions for high-speed data transfer applications. Compliant with PCI-SIG's PCI Express 2.0 standards, this IP features configurable PIPE interfaces to support a range of bit widths. A robust architecture ensures seamless data transmission and minimal latency, making it suitable for applications in networking and high-performance computing environments. Its compatibility with major FPGA platforms facilitates broad integration capabilities.
The H.264 Streaming Video Decoder Reference Design offers a comprehensive and compact solution for decoding streaming H.264 AVC videos, targeting uses from industrial monitoring to automotive infotainment. By integrating various Atria Logic IP blocks, this FPGA-based design facilitates efficient media processing, including a hardware-implemented AVC decoder, Ethernet MAC for data input, and an LCD display controller for video output. Built for flexibility, its low power footprint makes it ideal for cost-sensitive applications, and it can be adapted for use in more extensive SOC systems.
Atria Logic NVMe Validation Test Suite provides a robust environment for validating NVMe controllers, crucial for ensuring high performance and interoperability with industry standards for SSD communications. This test suite facilitates system-level validation using off-the-shelf hardware and is portable across platforms, including Linux and RTOS environments. With a focus on ease of integration and adaptability, it aids engineers in simulating complex system interactions and validating the efficiency of PCIe-connected NVMe storage setups, making it vital for high-speed data center operations.
This DDR memory controller core offers a high-performance solution for interfacing with various generations of DDR SDRAM, making it ideal for both FPGA and ASIC platforms. With comprehensive support for DDR-I, DDR-II, and DDR-III, it facilitates seamless integration into complex SoC designs. By providing programmable capabilities for CAS latencies, refresh intervals, and address mapping, this controller maximizes data throughput and minimizes latency. The design additionally supports power-saving features like self-refresh and power-down modes, aligning with JEDEC standards to ensure efficient and reliable memory management.
The USB 2.0 Controller IP Core offers a fully synthesized solution for high and full-speed USB device communication, compliant with industry standards. Designed for flexibility, the core supports multiple data transfer methods and integrates seamlessly with a system’s microprocessor. Enhanced with options for DMA support and power management, the design is made for ease of reuse in various embedded applications. By leveraging its programmable nature and comprehensive interface support, the USB 2.0 Controller Core is well-suited for consumer electronics and industrial devices.
The 10/100/1000 Mbps Ethernet MAC core ensures high-speed data transmission over Ethernet networks, fully compliant with IEEE 802.3 standards. Supporting half and full duplex modes and interfacing through industry-standard PHY devices, this core is adaptable across multiple FPGA platforms. The design entails mechanisms for efficient frame control, data integrity, and minimal latency, making it a versatile choice for varied applications from enterprise networking to sophisticated industrial communications. Customizable configuration ensures it meets specific user needs for data transfer efficiency.
Hybrid Memory Cube Verification IP provides a comprehensive validation solution for HMC-related SoC designs. Developed using SystemVerilog, this reusable component simplifies the verification process of HMC host controllers. It supports all major HMC version 1.0 transactions and ensures compliance through detailed analysis and error detection capabilities. The integrated Device Model and Analyzer components can function independently or together, facilitating robust testing environments for both IPs and full system designs, ensuring the reliability and performance of memory-intensive applications.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
