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TimeServoPTP extends the capabilities of the TimeServo core, providing a comprehensive IEEE 1588v2 PTP compliant ordinary clock slave implementation for FPGAs. This solution enables the achievement of high-level synchronization through both 1-Step and 2-Step processes with external network time grandmasters, addressing the needs for precise timing in distributed systems. By communicating with PTP masters via standard Ethernet L2 frames, TimeServoPTP ensures consistent time coherence across varied output domains, proving essential in applications where clock synchronization is critical. The single-component structure eases the implementation in complex FPGA systems, reducing dependency on external processors while maintaining a flexible architecture that supports multiple clock domains and user-defined outputs. Incorporating a digital phase locked loop, TimeServoPTP ensures accuracy and stability in timing to a microsecond level, making it ideal for synchronization tasks in telecom networks and data centers. The solution's compatibility with both Intel Agilex and Xilinx UltraScalePlus enhances its deployability across major FPGA platforms.
Designed as a highly accurate FPGA system timer, the TimeServo IP core delivers unparalleled resolution and timing precision. Its primary function focuses on providing a reliable timebase that meets the high demands of packet timestamping, necessary for line-rate independent applications. TimeServo employs a PI-DPLL to synchronize with an external Pulse-Per-Second (PPS) signal, thus ensuring precise timekeeping and syntonicity across various system components. TimeServo can be configured as TimeServoPTP, embodying an IEEE-1588v2/PTP compliant slave device that seamlessly operates without requiring host processor intervention. Featuring flexible and independent clock domains, TimeServo caters to various control-plane and reference clock needs, supporting up to 32 outputs for expansive use in complex timing requirements. The core of TimeServo integrates a 120-bit resolution phase accumulator, offering fractional control and synchronization, all observed and controlled via an AXI-compliant software interface. It also boasts minimal jitter for both simulation and real-world conditions, making it an exemplary fit for applications where precise synchronization is paramount, like telecommunications and advanced networking systems.
The UDP Offload Engine (UOE) from Atomic Rules provides a robust offload platform for UDP operations, enabling configurations from 10 GbE up to 400 GbE on popular FPGA devices. By implementing the UDP/IPv4 standards, the solution includes hardware offload for checksum, segmentation, and reassembly processes, supporting seamless integration with Ethernet MACs. With the ability to instantly deliver data across diverse Ethernet speeds, UOE facilitates improved data transfer rates while simplifying the overhead management of UDP operations. A pre-functionality for IGMPv2 multicast helps streamline traffic, preventing unwanted data from burdening the application layer. Suitable for both high-speed data transfer and resource-efficient deployment, it supports programmable frame sizes up to 16KBytes and allows datagram manipulation up to IPv4 limits, maximizing the operational efficiency of network-centric FPGA deployments. Through interoperability with widespread protocols and a low-area implementation, UOE enables advanced data processing solutions that promote system scalability and reliability.
ARDSoC introduces Data Plane Development Kit (DPDK) capabilities to the ARM-based System on Chip (SoC) domain, bypassing the traditional Linux network stack to save valuable ARM processor cycles. Designed specifically for embedded MPSoC environments, ARDSoC streamlines the transition of existing DPDK programs with minimal adjustments, bringing powerful data manipulation capabilities to devices with ARM architecture. This solution is particularly beneficial in reducing the power, latency, and total cost of ownership for applications transitioning from x86 frameworks to ARM structures. ARDSoC provides a zero-copy memory structure enhancing cache performance, along with an optimized Poll Mode Driver (PMD) that ensures minimal latency by maintaining data proximity to processing nodes. Notably, it harmonizes with a range of applications, from embedded protocol bridges to cloud-edge networks that demand robust packet processing. Among its many features, ARDSoC enables seamless packet vector and container-aware processing, supporting various platforms like VPP and Kubernetes. Compatible with Xilinx platforms, ARDSoC facilitates swift integration and testing, allowing developers to leverage the inherent flexibility and performance advantages in diverse networking and cloud computing scenarios.
The Arkville Data Mover serves as a high-throughput and low-latency communication bridge between FPGA logic and host memory, capable of transferring data up to 60 GBytes/s, or 480 Gbps, bidirectionally. By acting as a direct conduit for data, it eliminates the bottlenecks typically associated with traditional CPU core usage and memory copy processes, presenting hardware engineers with industry-standard RTL interfaces and offering software engineers seamless APIs for efficient data manipulation. Arkville supports concurrent, full-duplex data operations with both upstream and downstream movements, integrating AXI streaming interfaces to enhance packet handling. Designed to adhere to prevalent standards like DPDK and AXI, Arkville ensures compatibility with a wide array of packet processing systems and future-proofs applications through vendor-agnostic support for AMD/Xilinx and Intel FPGA devices. Its open-source driver integrated into DPDK further simplifies design workflows for developers. Packed with example designs, Arkville empowers engineers to accelerate their product development cycles significantly. The component incorporates burst traffic processing with AXI streams, maintaining up to 1 Tbps within two 128 byte wide streams operating at 500 MHz, and is particularly effective in applications necessitating high-volume data transfers, such as networking and storage solutions.
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