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CodaCache delivers high efficiency in SoC environments by serving as a highly configurable last-level cache. It addresses design challenges related to performance and power use by effectively managing data access and system scalability. Supporting flexible configurations, the IP adapts seamlessly into various SoC layouts, optimizing memory latency and power consumption. The strategic use of CodaCache in tandem with Arteris's NoC solutions enhances overall system performance, allowing for smoother data flow and faster processing speeds while mitigating bottlenecks.
Arteris's Ncore Cache Coherent Interconnect IP addresses the complex challenges of multi-core ASIC development, offering a scalable, highly configurable solution for coherent network-on-chip designs. This IP supports multiple protocols, including Arm and RISC-V, and is engineered to comply with ISO 26262 for safety-critical applications. Ncore enables seamless communication and cache coherence across varied processor cores, enhancing performance while meeting stringent functional safety standards. Its capability to automate Fault Modes Effects and Diagnostic Analysis (FMEDA) further simplifies safety compliance, proving its value in advanced SoCs where reliability and high throughput are critical.
Magillem Connectivity from Arteris simplifies SoC design by reducing integration complexity and shortening assembly times by a significant margin, sometimes up to 30%. Built on the IP-XACT standard, it automates processes, thereby enabling seamless system integration. Whether for large-scale designs or rapid iterations, Magillem caters to high productivity needs through continuous integration and connectivity verification features. Its automated approach enhances design precision, with robust error-checking mechanisms ensuring quality and adherence to constraints, making it indispensable for complex system deployments.
Designed for versatile applications in the IoT and microcontroller markets, the FlexWay Interconnect by Arteris is tailored to support cost-efficient yet high-performing devices. It features simple elements derived from intuitive algorithms, positioning it as ideal for small to medium scale SoC implementations. Despite its emphasis on power efficiency, FlexWay does not compromise on bandwidth or integration ability. It's engineered for dynamic environments, integrating multiple protocols and offering robust performance management capabilities, making it suitable for both constrained power designs and those requiring flexibility in topology.
The Magillem Register solution underpins efficient hardware/software integration by streamlining the register management process for SoCs. By developing a single-source-of-truth database for design teams, it allows the consistent and rapid generation of hardware/software interfaces. This product enhances collaboration across teams and significantly reduces time-to-market, all while maintaining high accuracy and functionality across diverse use cases.
CSRCompiler by Arteris is designed to streamline the creation of the hardware/software interface for system-on-chip designs. It offers a comprehensive approach to managing register designs, benefiting from tools like the CSRSpec language for synchronization across hardware, software, verification, and documentation aspects. This solution simplifies complex register operations and provides over 1,000 error checks, ensuring a high level of design integrity and efficiency. The CSRCompiler fosters quicker iteration cycles, supporting extensive multi-language inputs and outputs, thereby reducing development times significantly.
The FlexNoC Interconnect from Arteris stands as a pivotal component in semiconductor designs, serving as a physically aware network-on-chip (NoC) IP. It boasts flexibility in creating topologies, whether for small embedded systems or large, multi-billion transistor designs. FlexNoC's integrated physical awareness technology reduces the interconnection area and energy consumption, enabling designers to achieve up to five times faster time-to-market versus manual alternatives. Emphasizing scalability and performance optimization, this IP supports robust communication across SoC components, facilitating data flow both on-chip and off-chip.
The FlexGen Smart Network-on-Chip by Arteris revolutionizes semiconductor design with advanced AI-driven automation. Its heuristics enable industry-leading reductions in wire length and latency, delivering up to 30% wire length reductions and decreasing latency by up to 10%. This IP is designed to boost productivity tenfold by optimizing NoC topologies for complex systems, facilitating faster integration and enhancing SoC designs across various industries including automotive, data centers, and industrial electronics.
Discover how Arteris' expanded Ncore Cache Coherent Interconnect IP is transforming SoC design, enhancing scalability, efficiency & flexibility for cutting-edge technologies. Read more
Discover how Arteris joins the Intel Foundry Accelerator Ecosystem, enhancing scalable SoC design with advanced NoC and integration technology for future chip innovations. Read more
Arteris secures two Gold and one Silver Stevie Award in the 2025 American Business Awards, recognizing innovation in NoC IP and system-on-chip development. Read more
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