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CodaCache is the last-level cache solution from Arteris, designed to solve significant system-on-chip design challenges, including performance bottlenecks, data access latency, and power efficiency constraints. By leveraging high-performance caching techniques, CodaCache effectively optimizes data flow and power consumption across complex SoC architectures, ensuring accelerated memory access times and improved overall system efficiency. This cache solution is highly configurable, enabling developers to fine-tune features such as cache associativity and partitioning, which is critical for maximizing performance in specific application scenarios. Moreover, CodaCache benefits from seamless integration with the Arteris NoC environment, facilitating streamlined data traffic management across integrated systems. The product supports real-time processing needs by enabling a scalable cache that addresses challenges in timing closure and system integration. Performance monitoring and hardware-supported coherency management features empower engineers with tools for enhanced control and monitoring, ensuring the cache operates at peak efficiency. CodaCache’s functional safety and resilience options further its use in critical applications where high reliability is mandatory.
The Ncore Cache Coherent Interconnect by Arteris addresses the multifaceted challenges of multi-core ASIC design, offering a production-ready, highly configurable coherent NoC interconnect solution. Ncore is tailored for high-performance applications, supporting a variety of protocols compatible with Arm and RISC-V processors while enhancing inter-core communication and synchronization. Ncore is designed with functional safety in mind, making it suitable for ISO 26262 certification, a crucial factor for safety-critical applications such as automotive systems. It ensures credible operation in these environments with built-in safety and reliability features, including FMEDA data and ASIL certification. The IP supports multi-protocol coherency with CHI-B, CHI-E, and ACE alongside I/O coherent agent interfaces, providing versatility and backward compatibility for diverse SoC architectures. Enhanced with unique proxy caches, Ncore lowers power requirements while maintaining high performance, offering a scalable, power-efficient interconnect fabric suitable for a wide array of system scales, from small embedded solutions to extensive multi-billion transistor designs.
FlexWay Interconnect from Arteris provides a streamlined network-on-chip solution, ideally suited for low-power IoT edge devices and microcontrollers. This NoC IP is renowned for its efficiency and cost-effectiveness, making it an ideal candidate for embedded applications where power conservation is crucial. These interconnect mechanisms are constructed from rudimentary components, guided by robust algorithms and an intuitive graphical interface to facilitate the development of optimally configured topologies. FlexWay is adept at managing smaller scale systems, delivering smooth scalability from simple to medium complexity designs without unnecessary bloat. It maintains performance integrity across varied workloads, ensuring expedited on-chip data flow. Despite its power-efficient architecture, FlexWay handles bandwidth demands proficiently, supporting robust data transportation for embedded systems. Key capabilities include multi-clock, power, and voltage domain management, and comprehensive support for AMBA protocols to maintain a versatile environment, addressing diverse industrial standards. With SystemC simulation and UVM verification, FlexWay Interconnect ensures coherent design flows, reducing potential integration issues within the overall system architecture.
Magillem Connectivity by Arteris offers a comprehensive system-on-chip integration solution that simplifies the design of complex systems by streamlining connectivity processes. By automating the assembly of system components, it eliminates manual tasks and allows developers to concentrate on value-adding activities. Utilization of the IP-XACT standard ensures accuracy and consistency throughout the integration process. With embedded automation workflows, Magillem Connectivity greatly reduces the time required for system integration by up to 30%, maintaining a high quality of development and configurability. The tool enables seamless IP deployment and incorporates continuous integration practices to adapt swiftly to design changes, improving productivity and design predictability. Magillem Connectivity offers a robust set of features including project management, automatic IP instantiation, and comprehensive hierarchical design manipulation. This supports the efficient management of power and physical design constraints, while reducing integration time from several weeks to just a few days. Its capacity to manage thousands of instances in large-scale designs makes it invaluable for comprehensive projects, ensuring error-free design implementation with progress reporting tools that underscore portability and adaptability.
The Magillem 5 Registers from Arteris creates a synchronized hardware/software interface that dramatically decreases time-to-market by automating system memory map generation. Its single source of truth approach simplifies capturing register intents and ensures consistent execution throughout the life cycle of large-scale SoCs. Magillem 5 Registers enables automatic capture and verification of register data, expediting the generation of RTL, digital verification, firmware, and documentation. By maintaining a unified database of memory map information, it supports comprehensive error checks and syntax validations, thus enhancing the overall quality and reliability of the design. The interface supports diverse input formats such as SystemRDL and IP-XACT, and includes tools for managing complex designs with features like aliasing, virtual registers, and wide memory support. By fostering effective collaboration between hardware and software teams, Magillem 5 Registers improves debugging capabilities and minimizes iteration cycles, leading to more predictable design outcomes in shorter timelines.
Harmony Trace is a comprehensive Network on Chip IP by Arteris, designed to enable seamless integration with a wide range of existing systems while providing flexibility through scalable protocol support. It supports multiple foundries and process nodes, ensuring compatibility with various manufacturing technologies. The IP is characterized by minimal integration time and high scalability, making it suitable for a variety of applications.
The CSRCompiler from Arteris enhances the automation of hardware/software interface development for complex systems-on-chip (SoC). By orchestrating a streamlined creation of CSR functions, this system supports multiple specifications and input formats, paving the way for enhanced design integrity across hardware and software teams. The compiler's robust feature set includes strong error checking, enabling teams to manage register designs collaboratively from a singular source specification which is crucial for maintaining consistency and accuracy during the verification and documentation phases. It eliminates the challenges of CSR confusion through comprehensive syntactic and semantic checks and supports the production of high-quality RTL. CSRCompiler's efficiency is attested by its ability to process large volumes swiftly, generating thousands of registers in mere seconds. This significantly accelerates the development process, providing timely functional outputs that align with industry standards, ensuring that the verification teams have reliable models to base their operations on.
FlexGen Smart Network-on-Chip (NoC) by Arteris offers an innovative approach for crafting Network-on-Chip designs through AI and machine learning enhancements. This NoC IP allows design iterations to proceed up to ten times faster than traditional methodologies, primarily by automating the complex task of topology generation. By adopting FlexGen, developers can significantly reduce wire lengths and enhance power efficiency, thereby minimizing the typical manual effort involved in such processes. FlexGen caters to applications in sectors like automotive, data centers, and industrial electronics by streamlining design cycles for quicker launches and more exploratory design ventures. Optimizing productivity with a substantial tenfold increase in speed, FlexGen is specifically engineered to address intricate design needs, condensing SoC or chiplet iteration times from several weeks to a mere few days. It achieves expert-level results by reducing routing congestion and improving both silicon area and throughput during physical synthesis. This is complemented by its capability to optimize wirelength and overall performance using advanced machine learning algorithms. The core features of this IP include scripting-driven topology creation, incremental design capabilities, and automatic timing closure assistance. These tools equip engineers to manage intricate physical design challenges efficiently, allowing for substantial time savings and enhanced project outcomes. FlexGen’s design automation features enable developers to extract significant performance improvements while expediting the overall SoC design process.
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