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Spec-TRACER serves as a comprehensive requirements lifecycle management solution, ideal for FPGA and ASIC design projects. It supports functions ranging from requirements capture and management to detailed traceability and reporting, thus providing engineers with a structured framework to adhere to industry standards. This ease of integration and comprehensive feature set underpin its utility in complex design environments where compliance and traceability are paramount.
ALINT-PRO is a robust design verification tool focused on analyzing RTL code to prevent common pitfalls such as simulation mismatches and synthesis issues. It streams the design workflow by addressing both syntactical and logical errors early in the process, allowing for a more efficient transition into detailed design phases. By emphasizing best coding practices, ALINT-PRO supports designers in creating portable and reusable code, significantly enhancing design quality and maintainability.
TySOM Boards are designed as part of Aldec's embedded system prototyping ecosystem, providing a platform for developers to test and optimize applications across industries. At the core of each board is one of three types of FPGAs, facilitating compatibility with a wide range of daughter cards for extended functionality. These boards cater to a spectrum of sectors including automotive, AI, machine learning, and IoT, emphasizing rapid development cycles and integration capabilities in embedded environments.
HES-DVM represents a hybrid verification and validation environment specifically designed for SoC and ASIC designs. With capabilities for bit-level simulation acceleration, hardware prototyping, and transaction emulation, this solution stands out for its automated and scriptable workflow, suitable for designs scaling up to 633 million ASIC gates. The integration of virtual modeling with cutting-edge co-emulation strategies extends the potential for versatile and scalable design validation processes.
The HES Proto-AXI software package, when coupled with Aldec's HES prototyping boards, establishes a robust framework for swift design prototyping and algorithm accelerator development. With a focus on efficiency and robustness, this package ensures seamless integration with hardware, facilitating the rapid initialization and testing of designs and highlightings its value within diverse application settings.
Riviera-PRO is engineered to address the verification demands of engineers developing the next generation of FPGA and SoC devices. It enhances productivity by combining a high-performance simulation engine with advanced debugging capabilities, boosting testbench productivity and ensuring comprehensive verification coverage. Valuable for its automation features, Riviera-PRO fosters testbench reusability and efficiency across varied projects.
Active-HDL is a comprehensive Windows-based integrated design and simulation solution tailored for team environments. It offers a wide range of HDL and graphical design tools alongside a mixed-language simulator, enabling rapid deployment and efficient design processes. The integrated design environment ensures that engineers can efficiently transition from design to verification, minimizing errors and streamlining workflow.
The CCSDS 131.2 Wideband Demodulator performs critical modulation tasks necessary for high-performance communication. Adapted for use in space communications, it employs SCCC encoded frames, supporting comprehensive mapping, baseband interpolation, and output gain adjustments. Designed to interface seamlessly with RF systems and DACs, it fulfills demanding specifications of high-performance space communication systems requiring precise operational parameters.
The CCSDS 231.0 Encoder and Decoder IP cores support LDPC coding schemes specific to the CCSDS standards, optimized for telecommand applications. Incorporating error correction capabilities, these IP cores handle different coded block sizes and rates essential for high-performance forward error correction. Broadly applicable beyond telecommand uses, their versatility is augmented by options for both ASIC and FPGA implementations.
The 5G LDPC Decoder conforms to the 5th generation mobile broadband standards, employing a versatile structure for LDPC codes to meet various channel coding demands. Designed to handle high-throughput and low-latency requirements, the decoder is optimized for forward error correction in complex environments. It integrates seamlessly into designs demanding compliance with modern telecommunication standards, delivering reliability and efficiency.
The AWGN Channel generator from Creonic is a powerful tool for evaluating digital communication systems in the presence of noise. Capable of handling up to 512 symbols in parallel, this hardware-based solution reduces evaluation times significantly compared to software alternatives. By focusing on low bit-error-rates, it offers a reliable and precise noise generation capacity crucial for high-fidelity assessments.
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