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Akeana's 1000 Series processors are advanced 64-bit RISC-V cores designed for a spectrum of data computation needs. They are highly configurable, supporting high-performance applications such as Edge AI, industrial automation, and automotive sensing. Available in architectures supporting both in-order and out-of-order execution, these processors can handle substantial computational tasks efficiently. The 1000 Series processors feature a 9 to 12-stage pipeline and offer options for multi-threaded execution, allowing for single, dual, or quad-issue operation. These features make them particularly adept at managing high-throughput workloads requiring data precision and fast processing, such as those found in edge gateways and smart cameras. To accommodate such needs, these processors include options for comprehensive memory management, such as large TLBs and extensive instruction caches. This series is designed with flexibility in mind, offering modular add-ons like cryptographic and vector extensions, which are crucial for secure and efficient processing of complex data sets. The ability to scale with coherent many-core clusters enhances the processors' applicability to a broad range of sophisticated computational environments.
The Akeana 100 Series comprises 32-bit RISC-V processors designed for applications that demand small size and low power consumption. These processors are highly configurable and find their optimal use in deeply embedded systems like smart speakers, smart home appliances, drones, and wearable tech. Featuring an in-order, short pipeline length, the 100 Series offers low-latency, real-time processing capabilities. With a design catering to power and area-constrained environments, the Akeana 100 Series supports configurations with up to 64 KB L1 instruction cache and closely-coupled memory of up to 512 KB. The series includes options such as scalar cryptographic extensions, making it well-suited for IoT devices that require lightweight security. Its high configurability also includes custom instruction support, aligning with various application needs. Perfect for deeply embedded microcontrollers, this line offers various standard features, including Physical Memory Protection with multiple entries, and options to add custom instructions for specific use-cases. This flexibility extends its usability across different segments, ensuring optimal performance for a myriad of low power, real-time processing applications.
The Akeana 5000 Series represents the pinnacle of Akeana's processor IP offerings, delivering ultra-high performance for demanding computational tasks in data centers and cloud environments. These 64-bit RISC-V processors are optimized for extensive operations requiring high clock frequencies and rich operating systems like Android and Linux. Their design features a 12-stage out-of-order pipeline and supports multi-threaded execution with up to 10-wide instruction issue architecture. This makes the 5000 Series suitable for heavy-duty applications such as AI training, networking, and mobile computing. These processors are scalable, capable of forming fully coherent many-core clusters, allowing businesses to implement highly efficient processing units within expansive system architectures. Featuring advanced security and virtualization extensions, the 5000 Series ensures robust access control and efficient workload distribution across virtualized environments. Their configurability includes options for comprehensive L1 and L2 caching, enabling them to handle extensive data loads and reduce latency, which is critical in high-performance computing scenarios.
Akeana offers a suite of Processor System IPs to accelerate the creation of complete processor systems, meeting various performance and scalability requirements. These consist of essential components like the Compute Coherence Block (CCB), which supports coherent multi-core cluster configurations. This block is crucial for connecting up to eight cores with a shared cache via a directory-based protocol, enabling efficient data processing. Akeana's offerings include a versatile Input-Output Memory Management Unit (IOMMU) conforming to RISC-V standards, facilitating the translation between device and system physical addresses to optimize and secure SOC memory operations. By managing DMA access effectively, it enhances the system’s tolerance and reliability during high throughput operations. The system IP portfolio also features the AkeanaMesh, a CHI-compatible coherent interconnect fabric. This component is designed to support large compute configurations by coherently linking multiple CCBs, making it compatible with both AMBA AXI (non-coherent) and AMBA CHI (coherent) protocols. It provides an architecture capable of handling extensive data movement and ensures effective control over interrupt mechanisms.
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