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The embedded FPGA (eFPGA) from ADICSYS is a groundbreaking solution designed for seamless integration within ASICs and SOCs. This technologically independent FPGA is fully compatible with standard RTL design flows, making it a versatile choice for a wide variety of semiconductor applications. It allows for customizations in dimensions and architecture, including LUT count and routing density, tailored to meet specific area, performance, or power constraints. The eFPGA by ADICSYS promises high levels of flexibility and adaptability by incorporating a Verilog-based programmable IP featuring synthesizable RTL and constraint files. This is complemented by ADICSYS's proprietary compilation tool, Acompile, as well as a bitstream loader and built-in self-test (BIST) program. It even offers the option of delivering a hard block, such as GDSII, for specific design kits, ensuring bespoke integration suited to distinct customer requirements. Engineered to enhance system capability, ADICSYS's eFPGA significantly reduces time to market by simplifying design verification processes. It mitigates risks related to bugs and offers post-silicon flexibilities, ensuring that developments remain adaptable until tape-out. With support for extensive use of standard cells, it facilitates risk reduction by eliminating the need for unique silicon-proofing with each new instance, making recent technology nodes more accessible.
The Synthesizable Programmable Core (SPC) offered by ADICSYS is a sophisticated soft FPGA IP aimed at enhancing flexibility and extending the lifecycle of ASICs. This core diminishes the risk of errors, adapts rapidly to evolving specifications, and accelerates the time to market. It supports RTL-level decision-making, allowing modifications even in later development phases, thereby reducing delays and costs associated with design changes. SPC's advantage is underscored by its complete compatibility with standard ASIC CAD tools, providing a seamless integration into the existing ASIC workflow without constraints on the design process. Its reliance on standard cells for eFPGA construction also reduces the gap between standard and custom cell designs, making high-risk and high-cost full-custom designs a thing of the past. Built to support the challenges of modern technology nodes, SPC allows for enhanced backend access, simulation, synthesis, and testing. It offers immediate flexibility for late-stage semiconductor design decisions and can be tailored to fit varying scales and amounts of SPCs within a given project, thus promoting effective and efficient integration in a variety of silicon environments.
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