As the demand for high-performance computing (HPC) and artificial intelligence (AI) continues to surge, efficient power management has become a cornerstone of advanced semiconductor design. TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) platform, particularly its CoWoS-L variant with Local Silicon Interconnect (LSI), is leading this evolution by integrating Power Management Integrated Circuits (PMICs) and Deep Trench Capacitors (DTCs), branded as iCAPs, into large silicon interposers. Planned for full implementation by 2028, this approach is tailored to meet the power-intensive needs of hyperscale data centers and AI accelerators. This blog post explores the intricacies of TSMC’s CoWoS-L, detailing its technical specifications, advantages, challenges, and transformative impact on AI and HPC applications, supported by publicly available sources.

Understanding CoWoS and CoWoS-L

TSMC’s CoWoS platform is a 2.5D packaging technology that integrates multiple chiplets (e.g., System-on-Chips (SoCs), High Bandwidth Memory (HBM), and I/O dies) on a silicon interposer, connected via through-silicon vias (TSVs) and redistribution layers (RDL). The interposer acts as a high-density interconnect hub, enabling low-latency communication and robust power delivery. CoWoS-L, an advanced variant, combines silicon-based LSI with organic RDL for cost-effective scalability while maintaining high performance.

By 2028, TSMC plans to embed PMICs (fabricated on N16 FinFET with TSVs and on-wafer inductors) and DTCs (scaling from 340 nF/mm² in 2019 to 2,500 nF/mm²) within CoWoS-L interposers, which will expand to 7,885 mm² (9.5x reticle size). This supports massive chiplet assemblies, such as 12 HBM4 stacks and multiple SoCs, delivering over 1TB/s bandwidth and kilowatt-class power (>1,000A) for AI and HPC workloads.

Technical Details of CoWoS-L Power Management

Components Integrated

1. PMICs: Built on TSMC’s N16 FinFET process, these circuits regulate voltage and manage power distribution, delivering >1,000A to chiplets. TSVs and on-wafer inductors ensure low-resistance power paths.
2. DTCs (iCAPs): 3D deep trench capacitors provide high-density decoupling, with 340 nF/mm² currently and up to 2,500 nF/mm² (eDTCs) by 2028, yielding 68 µF per 1,700 mm² interposer for voltage stability.
3. On-Wafer Inductors and RDL: Submicron RDL (0.8 µm line width/spacing) and GSGSG shielding enhance signal and power integrity, reducing impedance by 0.05x compared to non-DTC designs.

Power Delivery Capacity

CoWoS-L supports >1,000A and >1KW, critical for AI accelerators like NVIDIA GPUs and AMD MI300, enabling robust power delivery for complex multi-chiplet systems.

Transient Response

With TSVs and RDL, CoWoS-L achieves a transient response of ~10–20 ns, faster than external voltage regulators (>100 ns) but slower than on-chip solutions, balancing latency and high-current delivery.

Package Size

CoWoS-L interposers scale from 2,900 mm² (3.5x reticle, 2024) to 7,885 mm² (2028), accommodating 12 HBM4 stacks and multiple SoCs, significantly larger than typical 2.5D/3D packages (100–1,000 mm²).

Thermal Management

TSMC employs high-thermal-conductivity thermal interface materials (TIMs), reducing thermal resistance by 85% (CoWoS-S5, 2024), and liquid cooling for AI/HPC systems. The 3Dblox standard optimizes thermal design, though PMIC heat in large interposers remains a challenge.

Yield

TSMC achieves >95% die-to-die (D2D) yield in CoWoS-S5 (2024) using TSV-first/TSV-last flows and automated alignment to mitigate warpage risks. Scaling to 7,885 mm² by 2028 introduces yield challenges, addressed through advanced process controls.

Sources: TSMC 2024 Technology Symposium, IEEE IEDM 2019 papers on iCAPs, TSMC corporate reports on fab capacity, and UCIe consortium specifications.

Advantages of CoWoS-L Integration

1. Unmatched Power Density: DTCs deliver 2,500 nF/mm², providing up to 68 µF per interposer, minimizing voltage droop (0.45x) and impedance (0.05x). This ensures stable power for kilowatt-class AI/HPC chips, critical for training large language models (LLMs) like GPT or inferencing for real-time AI applications.
2. Scalability for Hyperscale Systems: Large interposers (7,885 mm²) support complex chiplet assemblies, such as 12 HBM4 stacks with >1TB/s bandwidth, ideal for hyperscale data centers powering cloud services like AWS and Azure.
3. Modular and Interoperable Design: The 3Dblox standard and UCIe consortium (with TSMC, Intel, Samsung) streamline multi-die design, ensuring PMIC and DTC integration aligns with EDA tools from Synopsys and Cadence for customers like NVIDIA and AMD.
4. Superior Signal Integrity: Submicron RDL and GSGSG shielding reduce noise, enabling high-speed data transfer (e.g., 1,280 GB/s for HBM4), crucial for AI accelerators and networking ASICs.
5. High-Volume Production Readiness: TSMC’s mature CoWoS platform, with over 60 tape-outs by 2019 and a global capacity of ~13 million 300mm-equivalent wafers/year, ensures scalability. Arizona Fab 21 (N3/A16 by 2028) supports US demand.

Sources: TSMC 2024 Technology Symposium, Synopsys 3DIC Compiler documentation, UCIe 1.0 specification, TSMC 2019 corporate report.

Challenges of CoWoS-L Integration

1. Manufacturing Complexity and Cost: Integrating PMICs, DTCs, and TSVs in silicon interposers increases fabrication complexity and cost. Non-Taiwan fabs, such as Arizona Fab 21, are 50% costlier than Taiwan-based production due to higher operational expenses. TSMC mitigates this through high-volume production and hybrid silicon/organic RDL in CoWoS-L.
2. Thermal Management: PMIC heat in large interposers (7,885 mm²) complicates cooling in dense 3D stacks. TSMC counters this with advanced TIMs, liquid cooling, and 3Dblox thermal optimization, achieving reliability (1,300 cycles TCC, −65°C to 150°C).
3. Yield Risks: Warpage in large interposers risks yield loss during PMIC and TSV alignment. TSMC’s TSV-first/last flows and automated alignment maintain >95% D2D yield, but scaling to 7,885 mm² requires ongoing process refinement.
4. Latency Trade-Off: A transient response of ~10–20 ns is slower than some alternatives, though optimized by TSVs (5–20 µm) and submicron RDL.
5. Customer Design Dependency: As a foundry, TSMC relies on customers to optimize chiplet designs for CoWoS-L’s PMIC/DTC capabilities. UCIe and 3Dblox standards mitigate this by ensuring interoperability.

Sources: TSMC 2024 Technology Symposium, IEEE VLSI Symposium 2024 papers, Cadence 3D-IC design flow documentation.

Applications of CoWoS-L

CoWoS-L is designed for AI and HPC applications, powering:

1. AI Accelerators: NVIDIA GPUs (e.g., H100, Blackwell), AMD MI300, and Broadcom multi-die systems for training LLMs and inferencing (e.g., chatbots, recommendation systems).
2. Hyperscale Data Centers: Supports 12 HBM4 stacks with >1TB/s bandwidth for cloud computing, big data analytics, and enterprise AI (e.g., medical imaging, fraud detection).
3. Networking ASICs: Enables low-latency, high-throughput designs for 5G and data center interconnects.
4. Foundry Services: UCIe-compliant chiplets for custom designs, serving TSMC’s broad customer base.

Sources: TSMC 2024 Technology Symposium, NVIDIA H100 technical brief, AMD MI300 datasheet.

Timeline and Future Outlook

1. 2024: CoWoS-L achieves 3.5x reticle size (2,900 mm²) with DTCs (340 nF/mm²), supporting Broadcom’s 9-die, 6-HBM packages.
2. 2026: TSMC’s A16 process introduces Super Power Rail (SPR), a backside power delivery network, enhancing PMIC efficiency by 15–20% through reduced IR drop.
3. 2028: Full PMIC integration in 7,885 mm² interposers with eDTCs (2,500 nF/mm²), targeting kilowatt-class AI/HPC systems with 12 HBM4 stacks.

By 2030, CoWoS-L is expected to integrate next-generation HBM4 and potentially advanced ferroelectric capacitors, maintaining TSMC’s leadership in hyperscale computing.

Sources: TSMC 2024 Technology Symposium, IEEE IEDM 2024 roadmap, TSMC Arizona Fab 21 announcements.

Ecosystem Support

TSMC’s CoWoS-L leverages a robust ecosystem:

1. 3Dblox Standard: Simplifies 3D IC design for power, thermal, and signal integrity.
2. UCIe Consortium: Ensures chiplet interoperability with partners like Intel, Samsung, and AMD.
3. EDA Partnerships: Synopsys and Cadence provide tools for seamless PMIC/DTC integration.
4. Foundry Customers: NVIDIA, AMD, and Broadcom drive adoption, leveraging TSMC’s high-volume production and global fab network, including Arizona Fab 21.

Sources: UCIe Consortium 1.0 specification, Synopsys 2024 3DIC Compiler release notes, TSMC 2024 corporate overview.

Conclusion

TSMC’s CoWoS-L platform, with its planned integration of PMICs and DTCs by 2028, is a game-changer for power management in advanced semiconductor packaging. By embedding high-density components in large interposers (7,885 mm²), CoWoS-L delivers unparalleled power density (>1,000A), scalability, and signal integrity for AI and HPC applications. Despite challenges like manufacturing cost, thermal management, and yield risks, TSMC’s mature processes (>95% D2D yield), advanced cooling solutions, and ecosystem support (3Dblox, UCIe) position CoWoS-L as a leader in hyperscale computing. As AI and HPC demands grow, CoWoS-L’s innovations will power the next generation of trillion-transistor designs, driving advancements in LLMs, cloud infrastructure, and beyond. For further details, TSMC’s Technology Symposium, IEEE IEDM, and VLSI Symposium papers provide authoritative insights.