Chip Talk > Synopsys and Intel Foundry's Leap into Angstrom-Scale: A New Frontier in Semiconductor Innovation
In an exciting development for the semiconductor industry, Synopsys, Inc. has announced its collaboration with Intel Foundry to deliver cutting-edge angstrom-scale chip designs utilizing Intel's 18A and Intel 18A-P technologies. This partnership was announced at the recent Intel Foundry Direct Connect 2025 event and represents a significant advancement in electronic design automation (EDA) and integrated IP solutions. The initiative seeks to enhance the fabrication of AI and high-performance computing (HPC) chips, vital for the constantly evolving tech landscape.
At the heart of this collaboration is the introduction of Synopsys' AI-driven digital and analog design flows, which are certified for the Intel 18A process node and include production-ready EDA flows for Intel 18A-P. These advancements are particularly noteworthy as they integrate Intel’s RibbonFET Gate-all-around transistor architecture and PowerVia backside power delivery, representing the industry's first commercial foundry implementation of such technologies.
The Synopsys EDA flows are optimized for power and area on these cutting-edge process nodes, which enables the delivery of advanced-node System on Chips (SoCs) with superior quality-of-results. With this level of design technology co-optimization, engineers can leverage Synopsys' tools to address the growing demands of AI and HPC applications.
A major highlight of the collaboration is the support for multi-die design innovation through Intel’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging technology. Synopsys has developed an EDA reference flow, powered by its 3DIC Compiler, to enhance EMIB-T’s capabilities. This technology enables the combination of EMIB 2.5D and Foveros 3D packaging technologies, which facilitate high interconnect densities and efficient chip integration beyond traditional die size limitations.
The Synopsys 3DIC Compiler provides a unified platform for exploration to signoff, integrating features for early bump and Through Silicon Via (TSV) planning and optimization, as well as automated routing for UCIe and HBM, ensuring high-quality outcomes and swift 3D heterogeneous integration.
In tandem with these technological innovations, Synopsys is expanding its IP portfolio to align with the angstrom-scale processes essential for future AI and HPC chips. This includes IP for interfaces, embedded memories, and a variety of other essential components. The company’s efforts here aim to enhance the power distribution and performance of chips fabricated using Intel’s advanced process technologies.
With the introduction of Intel’s PowerVia backside power delivery network, Synopsys's offerings are designed to optimize power efficiency, delivering chip designs that are not only advanced but also differentiated in performance, power, and area optimization.
Beyond technological advancements, Synopsys is strengthening its collaboration with Intel Foundry through engagement in the Intel Foundry Accelerator Design Services Alliance and the Intel Foundry Accelerator Chiplet Alliance. This strategic membership underscores Synopsys's commitment to supporting Intel Foundry's ecosystem, offering design services that accelerate the adoption and innovation of advanced chip designs across the industry.
The collaboration between Synopsys and Intel Foundry redefines the technological landscape for semiconductor professionals by offering sophisticated tools and IP that cater to the rigorous demands of next-generation AI and HPC applications. This partnership not only highlights the power of cooperation between leading industry players but also sets new benchmarks for what’s possible in chip design and manufacturing.
For more details on this significant industry development, you can visit the original announcement here.
Published April 29, 2025
