BELGIUM – October 21, 2025 — Sofics BV, a global leader in on-chip protection and I/O interface technology, announced the successful tape-out of a new test chip on TSMC’s N4C (4 nm FinFET) process. The milestone, officially approved and supported by TSMC, demonstrates Sofics’ commitment to delivering high-performance, low-leakage, and area-efficient electrostatic-discharge (ESD) and input/output (GPIO) IP for cutting-edge SoCs.

Breaking New Ground on TSMC N4C

The Sofics engineering team spent the summer finalizing silicon design and validation for a comprehensive test vehicle on TSMC’s advanced 4 nm node. The test chip integrates multiple generations of ESD protection clamps, as well as 1.8 V and 3.3 V GPIO circuits optimized for:

1. 🔋 Ultra-low leakage and power consumption
2. ⚡ High transient robustness and repeatable ESD performance
3. 🧩 Compact area for high-density SoC integration

The new designs are tailored to meet the evolving needs of mobile, automotive, HPC, and AI applications—segments where balancing performance, reliability, and silicon area is increasingly critical.

Why It Matters

As semiconductor geometries continue to shrink, ESD protection and robust I/O design become key differentiators in both product reliability and overall PPA (Power-Performance-Area). Sofics’ IP portfolio directly addresses these challenges by providing:

1. Turnkey ESD solutions that minimize design iterations and silicon overhead
2. Process-qualified GPIO libraries across voltage domains (1.2 V – 3.3 V)
3. Proven scalability from legacy planar to FinFET and GAA nodes

By taping out on TSMC N4C, Sofics expands its presence within the foundry’s ecosystem, complementing previous design kits on N5, N6, and N7. The collaboration ensures customers can adopt Sofics’ protection IP seamlessly within TSMC’s advanced design flows.

Driving Innovation for AI, HPC, and Automotive

The integration of advanced ESD clamps and high-speed GPIOs has become a foundational requirement for:

1. AI accelerators and data-center chips where large die sizes and stacked power domains raise ESD complexity
2. Automotive ICs that demand AEC-Q100-grade reliability under harsh conditions
3. 5G and mobile devices needing low leakage to extend battery life without sacrificing IO robustness

Sofics’ latest test chip validates these technologies in real silicon, paving the way for qualified IP blocks ready for volume production enablement across multiple design partners in 2026.

Quote from Sofics Leadership

“We’re proud of our team’s achievement on TSMC N4C,” said Jan Mampaey, CEO of Sofics.

“Our goal is to empower SoC design teams with IP that not only meets their performance targets but also ensures intrinsic robustness from day one. This test chip marks another important step in strengthening our collaboration with TSMC and serving the next wave of AI, HPC, and automotive innovators.”

About Sofics

Sofics BV is a Belgium-based semiconductor IP company specializing in on-chip ESD protection, I/O libraries, and analog interface robustness. With over 100 customers worldwide and silicon-proven IP on more than 10 foundry platforms, Sofics continues to bridge the gap between design reliability and PPA optimization for the world’s leading chip makers.

For more information, read the full press release:

👉 Sofics Press Release – “Sofics Tapes Out Test Chip on TSMC 4 nm Process with Novel ESD IP and Low-Power GPIO Solutions”

Key Takeaway

Sofics’ new 4 nm test chip on TSMC N4C demonstrates how carefully engineered ESD and I/O IP can directly enhance silicon efficiency, reliability, and manufacturability for tomorrow’s AI and automotive SoCs—proving that robustness and performance can scale together.