In a significant leap for semiconductor innovation, Silicon Creations announced on April 24, 2025, the expansion of its industry-leading Clocking IP portfolio with a new Fractional-N Sub-Sampling Phase-Locked Loop (PLL) implemented in TSMC’s cutting-edge 3nm process (N3E and N3P nodes). This advancement, detailed in a recent Yahoo Finance article, underscores Silicon Creations’ pivotal role in enabling high-performance, power-efficient solutions for AI, data centers, automotive, and 5G applications. Let’s dive into the details of this breakthrough, its implications for the semiconductor industry, and why it matters for the future of technology.

What Is the Fractional-N Sub-Sampling PLL?

A Phase-Locked Loop (PLL) is a critical component in modern integrated circuits, acting as a clock generator to synchronize operations across a chip. The Fractional-N Sub-Sampling PLL is an advanced variant that offers precise frequency synthesis with minimal noise, making it ideal for high-speed applications. Silicon Creations’ new PLL, designed for TSMC’s 3nm process, achieves:

1. Sub-100fs RMS Jitter: This ultra-low jitter ensures signal integrity for high-speed interfaces like 200G/400G SerDes, PCIe Gen 6/7, and CXL 3.0/4.0, critical for data centers and AI workloads.
2. Power Efficiency: Optimized for TSMC’s N3E (enhanced 3nm) and N3P (performance-enhanced 3nm) nodes, it minimizes power consumption, a key factor for energy-conscious applications.
3. Compact Design: The PLL’s small footprint maximizes chip real estate, allowing more functionality in System-on-Chips (SoCs).

This PLL builds on Silicon Creations’ proven track record, with over 10 billion chips in the market incorporating their clocking solutions, from 2nm to 180nm process nodes.

Why TSMC’s 3nm Process Matters

TSMC’s 3nm process is at the forefront of semiconductor manufacturing, offering significant improvements over previous nodes:

1. Transistor Density: Approximately 20% higher than 5nm, enabling more functionality in the same chip area.
2. Performance: Up to 10–15% speed improvement or 25–30% power reduction compared to 5nm, ideal for power-sensitive applications like AI accelerators and mobile devices.
3. Applications: TSMC’s 3nm nodes (N3E, N3P) are used by industry leaders like Apple, AMD, and OpenAI for cutting-edge chips, including AI processors and high-performance computing (HPC) solutions.

Silicon Creations’ decision to target TSMC’s 3nm process aligns with the industry’s push for higher performance and efficiency. The N3E node, already in production, and the N3P node, an optical shrink offering 4% performance gains or 9% power savings, provide the perfect platform for this PLL’s deployment.

Key Features and Applications

The new Fractional-N Sub-Sampling PLL is tailored for demanding applications:

1. High-Speed SerDes: Supports 200G/400G Ethernet, crucial for next-gen data centers handling massive AI and cloud workloads.
2. PCIe Gen 6/7 and CXL: Enables ultra-fast data transfer for compute express link (CXL) protocols, enhancing memory and accelerator connectivity in AI servers.
3. SoC Integration: Its low jitter and power efficiency make it ideal for complex SoCs in 5G infrastructure, automotive ADAS (Advanced Driver Assistance Systems), and AI accelerators.
4. Silicon-Proven Reliability: Silicon Creations’ PLLs have been deployed in over 6 million wafers, ensuring robustness across diverse markets.

This versatility positions the PLL as a cornerstone for applications requiring precise timing, from autonomous vehicles to hyperscale data centers.

Silicon Creations’ Legacy of Excellence

Silicon Creations has a storied history in analog and mixed-signal IP:

1. Portfolio: Over 700 unique IP products, including 450+ PLLs, catering to precision timing, SerDes, and high-speed I/O needs.
2. Market Reach: Their IP is embedded in billions of chips across AI, automotive, consumer electronics, and 5G markets, with 1,000 production licenses sold.
3. TSMC Partnership: As a member of TSMC’s Open Innovation Platform (OIP) for over 12 years, Silicon Creations has won the TSMC OIP Partner of the Year award for eight consecutive years, reflecting their commitment to quality and innovation.

The new 3nm PLL builds on their earlier success with TSMC’s N2P process (2nm), where they taped out a chip with a novel temperature sensor and expanded clocking IP, further solidifying their expertise in advanced nodes.

Industry Implications

This announcement has far-reaching implications for the semiconductor ecosystem:

1. AI and Data Centers: The sub-100fs jitter and power efficiency of the PLL enable faster, more reliable data transfer in AI servers, addressing the growing demand for AI factories capable of scaling to millions of GPUs.
2. Automotive Innovation: With automotive applications requiring low-power, high-reliability timing for ADAS and infotainment, this PLL supports the increasing semiconductor content in vehicles.
3. 5G and IoT: The PLL’s compact design and efficiency are ideal for 5G base stations and IoT devices, where space and power are constrained.
4. Cost and Scalability: By leveraging TSMC’s 3nm process, Silicon Creations helps customers manage the rising costs of advanced nodes (3nm wafers cost ~$18,000 vs. $5,000 for 28nm) while delivering superior performance.

Challenges and Future Outlook

While the new PLL is a significant achievement, challenges remain:

1. Cost: TSMC’s 3nm wafer costs are high, and price increases for 3nm/5nm processes (5–10%) and CoWoS packaging (15–20%) starting in 2025 could impact adoption.
2. Complexity: Designing for 3nm requires precise engineering to manage heat and signal integrity, areas where Silicon Creations’ expertise shines.
3. Competition: Other IP providers and foundries are also targeting advanced nodes, but Silicon Creations’ silicon-proven track record gives it a competitive edge.

Looking ahead, Silicon Creations is well-positioned to expand its portfolio further, potentially targeting TSMC’s 2nm (N2) or 1.4nm (A14) processes, which promise even greater density and efficiency. Their focus on precision clocking will continue to drive innovation in AI, HPC, and emerging fields like robotics and AR/VR.

Conclusion

Silicon Creations’ expansion of its Clocking IP portfolio with a Fractional-N Sub-Sampling PLL on TSMC’s 3nm process is a milestone for the semiconductor industry. By delivering sub-100fs jitter, power efficiency, and silicon-proven reliability, this PLL empowers next-generation SoCs for AI, data centers, automotive, and 5G applications. As a trusted TSMC partner with a legacy of over 10 billion chips shipped, Silicon Creations is shaping the future of high-performance computing.

What does this mean for the industry? Faster, more efficient chips that power everything from AI servers to self-driving cars. How do you see advanced clocking IP transforming technology? Share your thoughts below!

Source: https://finance.yahoo.com/news/silicon-creations-expands-clocking-ip-174600813.html