Chip Talk > GUC and TSMC Make Groundbreaking Strides with UCIe Face-Up IP Technology
Published July 15, 2025
In the fast-paced world of semiconductor technology, developments regularly redefine possibilities. One such notable advancement comes from the collaboration between Global Unichip Corp. (GUC) and TSMC. This collaboration has successfully taped out the industry-leading Universal Chiplet Interconnect Express™ (UCIe™) PHY Face-Up IP on TSMC’s N5 process for integration with the TSMC SoIC®-X technology.
The new UCIe Face-Up IP is targeted toward AI, HPC, xPU, and networking applications. It delivers a breakthrough performance of 36Gbps while employing Adaptive Voltage Scaling (AVS), resulting in a power efficiency improvement of two times relative to previous solutions. This development sets a significant benchmark in bandwidth density, achieving 1.5TB/s per mm of die edge.
GUC utilizes TSMC's advanced SoIC-X and CoWoS® (Chip-on-Wafer-on-Substrate) packaging technologies, which significantly enhance integration and performance metrics. This collaboration does not exist in a vacuum; earlier in the year, GUC demoed the UCIe-32G silicon on the TSMC N3P process, further evidencing their growing prowess in the field.
You can read more about this development directly from GUC’s official press release.
The UCIe Face-Up IP represents a crucial step in addressing the burgeoning bandwidth requirements brought about by the expansion of AI, HPC, and networking technologies. By integrating Adaptive Voltage Scaling (AVS), the solution optimizes supply voltage and driving strength, enhancing power efficiency considerably. This vast improvement allows for a robust and dynamic response to varying electrical and thermal conditions, facilitating a more efficient semiconductor function.
The integration of proteanTecs’ I/O signal quality monitors enhances reliability by providing real-time performance monitoring without disrupting data transfer.
To cater to different network architectures, GUC has developed bridges for AXI, CXS, and CHI buses using the UCIe Streaming Protocol. These bridges promise high traffic density and low latency, all within a power-efficient framework.
This new development supports Dynamic Voltage and Frequency Scaling (DVFS), a technology that enables seamless digital supply voltage alterations while maintaining uninterrupted data flow, crucial for modern digital applications and infrastructure.
GUC's technological ambition doesn't stop with the current release. With plans to develop UCIe 64G IP by 2025, there is clear anticipation of future demands for higher bandwidth in next-generation chiplet-based systems. This foresight suggests a comprehensive strategy to stay ahead of industry need.
GUC’s CMO, Aditya Raina, summarized the goal succinctly, emphasizing their mission to provide the fastest and lowest-power chiplet interface IPs, a mission well on its path to fruition with the recent advancements.
As we look toward the future of semiconductor technology, this ambitious initiative between GUC and TSMC stands to accelerate innovation cycles and reduce product development times, creating tangible benefits for AI, HPC, xPU, and networking applications. The partnership is leading the transformation from monolithic SoCs to intricate, yet efficient, modular chiplet architectures, broadening the horizons of what semiconductor technology can achieve.
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