The Prelude to CMOS 2.0

For decades, the semiconductor industry has thrived on the predictable benefits of Moore's Law, steadily shrinking transistors and squeezing more onto every chip to boost performance and decrease costs. However, as we increasingly hit the physical and economic limits of shrinking down to single-digit nanometer processes, the question emerges—what happens next?

Enter CMOS 2.0, a term coined by imec for a transformative approach to chip design. By building vertically, stacking logic, power, and memory, CMOS 2.0 proposes to overcome the diminishing returns of traditional two-dimensional scaling. In this blog, we will explore the intricacies of CMOS 2.0, its technological underpinnings, and its potential challenges and benefits for the semiconductor industry.

More details can be found in CMOS 2.0: Layered Logic For The Post-Nanosheet Era.

Technological Foundation

At its core, CMOS 2.0 challenges the status quo by transitioning from a single monolithic die to multi-layered structures with specific roles. The foundation of this technology combines four pivotal concepts:

• Backside Power Delivery: This relocates the power rails from the surface to the rear of the wafer, freeing up space for signal routing and reducing IR-drop.
• Fine-Pitch Hybrid Bonding: Stacked tiers are connected using copper-to-copper interconnects at pitches significantly smaller than the traditional microbumps.
• Complementary FETs (CFETs): By stacking n- and p-type transistors vertically, density is improved and gate lengths are compressed.
• Bi-facial Processing: This allows devices to be processed on both sides of a wafer, offering new routing and integration possibilities.

These layers, each tailored for optimum performance, come together to create a vertically integrated system. Unlike 2.5D packaging, which places known-good dies side-by-side on an interposer, CMOS 2.0 attempts real wafer-scale stacking.

The Benefits of Vertical Integration

The layered architecture of CMOS 2.0 promises significant improvements in multiple dimensions:

• Higher Bandwidth and Density: By enabling much shorter signal paths, it enhances signal integrity, increasing the bandwidth available between logic and memory.
• Lower Energy Consumption: By minimizing parasitic losses, this architecture consumes less energy.
• System-Level Integration: It facilitates a more seamless integration of varied functions, akin to a 3D network-on-chip.

Luc Van den Hove, president of imec, emphasized that the shift will no longer be about transistor scaling but about scaling the entire system in three dimensions to continue progress.

Potential Challenges and Considerations

With such transformative potential, come significant challenges, particularly in designing and manufacturing:

• Wafer Alignment and Bonding: Sub-micron precision in wafer layer alignment and void-free bonding are critical.
• Thermal Management: Stacking introduces potential thermal bottlenecks that could affect performance and yield.
• EDA Tools and Design Flows: Existing electronic design automation (EDA) tools and practices need to evolve to accommodate three-dimensional design challenges.

These challenges require not just technical solutions but also transformational shifts in industry practices and collaborations.

Outlook for CMOS 2.0

The implementation of CMOS 2.0 is likely to start in fields demanding extreme performance like high-performance computing and AI accelerators, where its benefits will justify initial costs. As processes mature, broader deployment is anticipated.

The program demands a shift not just in technology but mindset, prompting changes in EDA workflows, testing, and lifecycle management strategies. The industry is at a critical juncture where collaboration will be key to overcoming these multifaceted challenges.

In conclusion, CMOS 2.0 represents a promising leap forward in semiconductor manufacturing, serving as both a technological and strategic innovation to navigate the post-nanosheet era. The question remains whether the industry as a whole can align to make this vision a reality, or if alternative approaches will prevail.

Explore more insights on early adopters and iterations in the original article on Semi Engineering.