Cadence Design Systems has once again pushed the boundaries of semiconductor IP innovation. On July 9, the company announced the industry’s first LPDDR5X-14.4Gbps memory IP, designed to meet the extreme bandwidth and power efficiency requirements of tomorrow’s AI infrastructure, edge computing, and hyperscale data centers.

This LPDDR5X solution supports data rates of up to 14.4Gbps — a full generation ahead of other IP offerings currently on the market. Developed on TSMC’s N3E process, it also provides chiplet-ready support, addressing the growing demand for advanced packaging and modular SoC architectures.

Why It Matters

AI workloads are memory-hungry, latency-sensitive, and power-intensive. As large language models (LLMs), edge inference, and high-performance computing (HPC) evolve, conventional memory solutions can quickly become bottlenecks. Cadence’s new LPDDR5X IP addresses this head-on with:

• Industry-Leading Data Rate: Up to 14.4Gbps — 50% higher than the previous 9.6Gbps standard.

• Ultra-Low Power: Optimized for mobile and edge-AI use cases, including AI PCs, automotive systems, and advanced driver assistance (ADAS).

• Advanced RAS Features: Built-in support for reliability, availability, and serviceability for mission-critical systems.

A Full-Stack Solution for Memory Subsystems

The new offering is a part of Cadence’s broader IP portfolio, which includes:

• PHY IP for LPDDR5/5X

• Memory Controller IP

• Verification IP

• Denali Memory Models

This allows SoC designers to integrate, verify, and optimize their memory subsystems with Cadence’s full-stack ecosystem, reducing development time and accelerating time-to-market.

Designed for Emerging Use Cases

According to Sanjive Agarwala, corporate VP and GM of the IP Group at Cadence:

“With rapidly expanding AI infrastructure workloads, memory bandwidth and power efficiency are more critical than ever. Cadence’s LPDDR5X-14.4Gbps IP delivers the performance, scalability, and power optimization needed for next-gen SoCs.”

Target applications include:

• AI training accelerators and inference engines

• AI-powered consumer devices (phones, AR/VR, PCs)

• Automotive electronics (ADAS, infotainment)

• Data center accelerators and chiplets

Silicon-Proven, TSMC-N3E Ready

The IP is validated in silicon and qualified on TSMC’s N3E node, which is fast becoming the process of choice for advanced compute and AI-centric SoCs. With chiplet interoperability and low-latency die-to-die support, Cadence is aligning itself with the future of disaggregated compute architectures.

Final Thoughts

As AI infrastructure evolves, memory IP is no longer an afterthought — it’s a core enabler of system performance and energy efficiency. Cadence’s leadership in launching the first LPDDR5X-14.4Gbps solution underscores its commitment to driving innovation at the edge of what’s possible in silicon.

For semiconductor companies building for AI, HPC, and edge applications, this is an IP block to watch.

👉 Read the full press release