As the demand for high-resolution imaging, low-power displays, and advanced edge processing continues to grow, SoC designers are under increasing pressure to deliver robust connectivity solutions without sacrificing performance or power efficiency. In this context, Mixel’s recent announcement is a strategic milestone—not just for the company, but for the entire embedded and edge semiconductor ecosystem.

Mixel has successfully validated its MIPI C-PHY/D-PHY Combo IP on STMicroelectronics’ 40nm Low-Power (40LP) process, a widely adopted node for automotive, IoT, medical, and industrial applications. This integration creates a compelling offering for semiconductor designers building camera and display-intensive systems.

Why This Matters

1. Combo IP = Design Flexibility

Mixel’s combo IP supports both MIPI C-PHY v2.0 and MIPI D-PHY v1.2, making it a versatile solution for a wide array of applications. This dual compatibility provides flexibility to system architects and SoC designers by:

1. Allowing a single IP block to interface with components using different PHY protocols
2. Reducing silicon footprint and BOM by enabling combo reuse
3. Supporting design convergence across product lines

For customers working on heterogeneous product portfolios—ranging from smart cameras to industrial displays—this flexibility translates into faster time-to-market and reduced development cost.

2. Impressive Data Rates on a Mature Node

The validated IP achieves data rates of:

1. Up to 6.0 Gbps per lane for D-PHY
2. Up to 5.7 Gsps per trio for C-PHY

These performance levels make the combo IP suitable for bandwidth-intensive applications like:

1. 4K/8K cameras and displays
2. Augmented/virtual reality systems
3. Automotive ADAS and infotainment
4. Medical imaging equipment

The ability to reach such speeds on the 40LP node, which is favored for its cost-effectiveness and low leakage characteristics, adds even more value for designers aiming at mass-market or power-sensitive segments.

Strategic Implications

For SoC Designers:

This validation offers a robust and silicon-proven IP path for those targeting ST’s 40nm platform. It simplifies IP sourcing, reduces design risk, and enables a faster path to silicon for products requiring MIPI interfaces.

For the Ecosystem:

This move strengthens Mixel’s leadership in the MIPI IP space, reaffirming its commitment to providing interface IP on mainstream and emerging process nodes. It also enhances the value of ST’s 40LP technology platform by enabling high-speed connectivity—an increasingly critical feature in modern SoCs.

For OEMs:

End-product manufacturers stand to benefit from better system integration, extended component interoperability, and more scalable design options—particularly in sectors where both D-PHY and C-PHY devices coexist.

Looking Ahead

As imaging, sensing, and display technologies continue to advance in edge and embedded applications, connectivity IP will play a decisive role in enabling new user experiences. Mixel’s MIPI C-PHY/D-PHY Combo IP on ST’s 40LP is a clear example of how collaborative IP development and process optimization can drive meaningful innovation—without needing to move to bleeding-edge nodes.

This validation isn't just about speeds and specs—it's about enabling the next generation of intelligent systems to be smaller, faster, and more power efficient.

🔗 Learn more: https://mixel.com/mixel-mipi-c-phy-d-phy-combo-ip-stmicroelectronics-40lp/

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