In a notable showing at the 2024 TSMC Technology Symposium, Analog Bits turned heads by demonstrating working silicon IP on TSMC’s advanced 3nm and 2nm nodes—a rare feat in the IP ecosystem and a strong testament to their innovation depth and silicon maturity.

What made the presentation compelling wasn’t just the early availability of silicon-validated IP on leading-edge nodes, but also Analog Bits’ strategic shift in how they develop and deliver IP. Rather than designing for a single process and retrofitting it later, the company now co-develops IP in tandem with foundry process development, ensuring tighter alignment, better performance, and faster time-to-market.

The company showcased a broad portfolio—including PCIe Gen5/6, SerDes, PLLs, and PVT monitors—already proven on TSMC’s 3nm process, with the 2nm IP running in the lab today. The early results are promising: lower power consumption, smaller area, and higher performance, aligning well with hyperscaler and AI/ML accelerator requirements.

The article also highlights Analog Bits’ robust customer engagement model. Their customer-first approach, combined with a flexible IP architecture and tight foundry collaboration, has allowed them to secure multiple wins—especially among top-tier hyperscalers and automotive players.

Ultimately, Analog Bits’ performance at the symposium underscored an essential message for the semiconductor IP world: having proven, production-ready IP at the most advanced nodes is a real differentiator. In an era where design complexity and time-to-market pressures continue to rise, Analog Bits is positioning itself as a go-to partner for bleeding-edge designs.