All IPs > Wireline Communication > Optical/Telecom
In the realm of wireline communication, Optical and Telecom semiconductor IPs play a pivotal role in ensuring robust connectivity and high-speed data transfer across global networks. As the demand for faster and more reliable communication channels grows, these semiconductor IPs provide the foundational technology for modern telecommunication systems and fiber optic networks.
Optical/Telecom semiconductor IPs are critical for enabling the efficient transmission and reception of data over optical fibers. These IPs include various components such as optical transceivers, modulators, and detectors, which convert electronic signals into optical signals and vice versa. This conversion is essential for high-speed data transmission over long distances, a crucial requirement for both enterprise and consumer telecommunications.
Beyond merely converting signals, Optical/Telecom semiconductor IPs must handle complex signal processing tasks to reduce errors, maximize bandwidth, and optimize data integrity. This includes forward error correction (FEC), signal modulation, and wavelength division multiplexing (WDM) technologies. Such capabilities are vital for sustaining the rapidly increasing data loads due to burgeoning internet usage, video streaming, and cloud computing services.
Products in this category of semiconductor IP range from highly sophisticated optical communication modules to integration-ready telecom processors. They are developed to support a broad array of applications, such as backbone internet infrastructures, 5G networks, data centers, and undersea cable systems. These cutting-edge solutions ensure that network providers can offer seamless and reliable service, empowering users with exceptional connectivity experiences. By leveraging advanced Optical/Telecom semiconductor IPs, industries can continue to innovate and meet the ever-evolving demands of a digitally connected world.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The Network Protocol Accelerator Platform (NPAP) is engineered to accelerate network protocol processing and offload tasks at speeds reaching up to 100 Gbps when implemented on FPGAs, and beyond in ASICs. This platform offers patented and patent-pending technologies that provide significant performance boosts, aiding in efficient network management. With its support for multiple protocols like TCP, UDP, and IP, it meets the demands of modern networking environments effectively, ensuring low latency and high throughput solutions for critical infrastructure. NPAP facilitates the construction of function accelerator cards (FACs) that support 10/25/50/100G speeds, effectively handling intense data workloads. The stunning capabilities of NPAP make it an indispensable tool for businesses needing to process vast amounts of data with precision and speed, thereby greatly enhancing network operations. Moreover, the NPAP emphasizes flexibility by allowing integration with a variety of network setups. Its capability to streamline data transfer with minimal delay supports modern computational demands, paving the way for optimized digital communication in diverse industries.
The High-Speed SerDes is an advanced solution engineered to deliver high-performance data transmission in chiplet architectures. Leveraging our innovative digital-centric design, this SerDes offers unmatched low power consumption, making it ideal for high-speed ASIC applications. It ensures optimal performance and efficiency, supporting systems with varying speeds and complexities. This SerDes is adept at handling the demands of modern data transfer, ensuring reliable and fast communication between chiplets in an integrated system. Its ability to function at high speeds while maintaining energy efficiency is what sets it apart in the domain of interconnect technologies. Designed to be scalable, it facilitates the development of systems that are not just current with today’s technological demands but are also prepared for the innovations of tomorrow. This makes it a critical component in the expansion of semiconductor capabilities, supporting diverse applications across multiple sectors.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The RWM6050 Baseband Modem is engineered to facilitate high-data rate applications across wireless communication networks. Designed to serve as a versatile component within various telecommunication systems, it processes signals with precision to enhance data throughput across diverse transmission environments. At its core, the RWM6050 is optimized for operation in complex wireless networks where bandwidth efficiency and robust signal integrity are paramount. It seamlessly integrates into wireless communication frameworks, providing the needed flexibility and scalability to support next-generation network deployments. Through its advanced capabilities, this baseband modem establishes itself as a pivotal element in ensuring reliable, high-speed data transmission. Whether supporting conventional networks or cutting-edge mmWave technology applications, the RWM6050 maintains stellar performance, thereby enhancing the efficiency of communication infrastructures in both commercial and defence sectors.
LightningBlu is designed specifically to transform the connectivity landscape of high-speed rail by providing uninterrupted, on-the-move multi-gigabit connectivity. By bridging the gap between trackside infrastructure and the train, it offers onboard services such as internet access, entertainment, and passenger information. Operating within the mmWave range, LightningBlu ensures a seamless communication experience even at high speeds, significantly enhancing the onboard experience for passengers. Integrating robust mmWave technology, the solution supports high data throughput, ensuring passengers can enjoy swift internet access and other online services while traveling. This wireless solution eliminates the need for traditional wired networks, reducing complexities and enhancing operational flexibility. With a profound ability to support high-speed data-intensive applications, LightningBlu sets a new benchmark in transportation connectivity. This platform's design facilitates smooth operation at velocities exceeding 300 km/h; coupled with its ability to maintain service over several kilometers, it is a critical component in advancing modern rail systems. LightningBlu not only meets today’s connectivity demands but also future-proofs the necessities of tomorrow's rail network implementations.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The TSN Switch for Automotive Ethernet is an advanced solution designed for the modern automotive network environment, supporting Time-Sensitive Networking (TSN) capabilities to ensure low-latency and reliable data transmission across automotive systems. This switch technology is critical for enabling real-time communication, an essential requirement for new-age automotive applications such as autonomous driving and complex onboard diagnostics. Through TSN, data traffic can be transmitted with precise timing, which is crucial in maintaining the seamless operation of safety-critical features. At its core, the TSN Switch integrates functionalities that allow for the prioritization and scheduling of network traffic, ensuring vital data is delivered on time under various conditions. This feature is important for managing the extensive array of data exchanged in modern vehicles, where different subsystems must communicate effectively to maintain overall vehicle performance and safety. In addition to its primary applications in vehicles, the TSN Switch is designed with versatility in mind, allowing it to be adapted for other industries that require robust and timely communication, such as industrial automation and control systems. The modular approach to its design enables future updates and upgrades, ensuring the switch remains relevant as technology progresses. This adaptability underscores its strategic importance in both the automotive and broader industrial contexts.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
Designed for maximum compatibility and efficiency, the ATSC 8-VSB Modulator serves both professional TV network applications and custom point-to-point radio links. Its comprehensive compliance with ATSC A/53 8-VSB standards guarantees reliable performance across multiple broadcast scenarios. The modulator's versatile design supports varied operational environments, making it indispensable for broadcasters who require versatile and robust transmission solutions. Its emphasis on delivering flawless signal integrity ensures top-notch broadcast quality for diverse applications.
The LDPC Decoder for 5G NR by Mobiveil is crafted to ensure seamless decoding within modern cellular networks. Incorporating the Min-Sum decoding algorithm, it ensures optimal performance while reducing power consumption and silicon area usage. This decoder is equipped with programmable bit widths, allowing for tailored configurations to suit specific application requirements during the compile phase. The inclusion of an early iteration termination feature, driven by an integrated parity check engine, supports efficiency by enabling preemptive exits during iterative processes. By accommodating retries with hybrid automatic repeat requests (HARQ), the decoder maintains robustness across various transmission conditions. This adaptability makes it an invaluable component for 5G networks, where data integrity and fast processing are paramount.
The DVB-T2 Modulator stands out with its powerful FPGA or ASIC implementation, designed to perform efficient modulation as per the DVB-T2 ETSI EN302 755 standards. This comprehensive solution encompasses all necessary functions to facilitate high-performance terrestrial broadcasts. The modulator is crafted for use in a range of broadcast networks, offering flexibility and adaptability in its application. This makes it a go-to solution for broadcasters aiming to leverage the power of DVB-T2 technology to deliver superior terrestrial broadcast services.
The LDACS-1 and LDACS-2 Physical Layer IPs are designed to offer robust solutions for communication systems. Leveraging the power of MATLAB for initial design and simulation, these IPs can be seamlessly converted into Verilog as per project demands. Their flexibility allows for adaptation to various requirements, ensuring they can address differing specifications for telecommunications projects effectively. These IP cores serve as an essential component for developers leveraging advanced algorithmic designs in FPGA environments. By providing a comprehensive solution for the physical layer operations of L-band Digital Aeronautical Communication Systems (LDACS), these cores facilitate a transition toward more efficient and reliable communication systems. Their implementation supports real-time processing capabilities essential for aeronautical communication, ensuring enhanced performance and reliability. Moreover, the adaptability of these IPs makes them a preferred choice for those needing tailor-made solutions in the aeronautical comms field. Developers benefit from the cores' optimized resource utilization, which ensures they can efficiently manage power and processing loads while maintaining high standards of communication integrity and throughput.
The Multi-channel ATSC 8-VSB Modulator enhances broadcasting flexibility by supporting multiple channels within ATSC A/53 8-VSB standards. Tailored to meet professional TV network and custom point-to-point radio link needs, this modulator core facilitates complex broadcast operations. It enables seamless integration and high-quality signal transmission across varied operational environments. By efficiently managing multiple channels, it empowers broadcasters to optimize signal delivery and enhance their overall transmission capabilities.
The ISDB-T Modulator delivers robust capabilities for both professional TV networks and custom point-to-point radio links. This modulator core is fully compliant with ARIB STD-B31 and ABNT NBR 15601, ensuring compatibility across a broad range of broadcasting applications. Its adaptable framework makes it suitable for diverse broadcast needs, facilitating the efficient transmission of digital television signals. Through this, broadcasters can achieve a more reliable and consistent service quality across different market segments.
**Ceva-BX2 baseband processor IP** handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming. It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size. Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators. The Ceva-BX2 combines the capabilities of signal processing and control-code execution into a single, compact DSP. Computational speed comes from quad-32×32/octal-16×16 MACs with added support for 16×8 and 8×8 MAC operations, organized into two parallel compute engines within an 11-stage pipeline. Each compute engine can add optional half- and single-precision IEEE floating-point units. These resources are directed by a five-way VLIW instruction set architecture with optimizations for single-instruction-multiple-data (SIMD) operation, including a hardware loop buffer for kernel execution. Efficient execution of control code is aided by dynamic branch prediction and a branch target cache. On signal-processing tasks the Ceva-BX2 can reach up to 16 GMACs per second, and on control workloads it can achieve up to 5.46 CoreMark/MHz. The hardware design is optimized for speed, achieving 2 GHz operation implemented in a TSMC 7nm process node with only common standard cells and memory compilers. [**Learn more about Ceva-BX2>**](https://www.ceva-ip.com/product/ceva-bx2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_bx2_page)
The SOQPSK-TG LDPC Modulator is specifically designed for aeronautical telemetry systems, offering a robust solution for efficient data transmission. This modulator implements the Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) waveform, which is widely used in telemetry to optimize bandwidth utilization and improve performance under various transmission conditions. The integration of Low-Density Parity-Check (LDPC) coding further enhances the modulator's performance by providing forward error correction. This feature is crucial for maintaining data integrity during transmission, especially in environments where signal quality can be variable or susceptible to interference. Users benefit from a modulator that delivers high data rates and reliable communications, ensuring efficient and secure transmission of telemetry data in aerospace applications. This IP core is available for implementation on various FPGA platforms, providing flexibility for different design requirements and deployment scenarios.
Rockley Photonics' Multi-Channel Silicon Photonic Chipset is engineered for high-speed data transmission applications. The chipset integrates hybrid III-V DFB lasers and electro-absorption modulators into a silicon photonics framework, allowing it to support 4×106Gb/s 400 GBASE-DR4 data rates over multiple channels. This highly efficient setup delivers significant optical modulation amplitude (OMA) and maintains a low TDECQ penalty, fully complying with IEEE standards. This chipset is particularly suited for optical communications, providing the robustness and speed necessary for demanding data centers and telecommunication infrastructures.
The QAM Demodulator offered by IPrium is a high-performance solution designed for efficient demodulation of Quadrature Amplitude Modulation signals. With capabilities to handle complex signal processing tasks, this IP is suitable for telecommunications systems requiring accurate and swift demodulation of data. Its architecture supports a variety of QAM formats, making it adaptable to numerous application scenarios like digital broadcasting, cable modems, and wireless communications. By ensuring high fidelity and minimal signal distortion, it plays a crucial role in maintaining the integrity of transmitted data. Engineered for FPGA platforms, the demodulator is easy to integrate and optimize within existing systems. Its flexibility and robustness make it an essential component for service providers aiming to enhance their communication technology offerings.
IPrium's QAM Modulator provides a high-performance solution for generating Quadrature Amplitude Modulation signals, a critical aspect of modern telecommunications and broadcasting. This IP is engineered to cater to complex modulation requirements, supporting various QAM schemes to enhance data transmission efficiency. Ideal for cable and satellite broadcasting, the QAM Modulator ensures high fidelity and efficient use of bandwidth by dynamically adjusting for optimal performance. Its robust architecture is capable of addressing the challenges presented by high-density data environments. This modulator is designed for seamless integration into existing systems, offering adaptability and scalability needed by operators seeking to upgrade their infrastructure. By leveraging FPGA technology, it delivers consistent performance improvements, making it an invaluable tool for enhancing communication networks.
The FFT / IFFT Core provided by Creonic is designed for efficient computation of Fast Fourier Transform and Inverse Fast Fourier Transform algorithms. These cores are integral to modern communication systems as they enable the transformation of signals between time and frequency domains efficiently, a crucial operation in many digital signal processing applications. Designed with adaptability in mind, Creonic's FFT / IFFT cores are capable of high-speed data processing, which is essential for applications like OFDM systems and signal analysis. This makes them particularly suitable for wireless communications, satellite, and microscopy applications where transformation efficiency and rapid processing are critical. Creonic ensures that these cores are highly configurable, supporting multiple FFT sizes which can be tailored to meet specific application demands. Additionally, these cores can be easily integrated with other communication components, enabling seamless operation across various platforms, including both FPGAs and ASICs. This capability ensures that the FFT / IFFT Cores not only meet performance requirements but also significantly contribute to system flexibility.
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