All IPs > Wireline Communication > Optical/Telecom
In the realm of wireline communication, Optical and Telecom semiconductor IPs play a pivotal role in ensuring robust connectivity and high-speed data transfer across global networks. As the demand for faster and more reliable communication channels grows, these semiconductor IPs provide the foundational technology for modern telecommunication systems and fiber optic networks.
Optical/Telecom semiconductor IPs are critical for enabling the efficient transmission and reception of data over optical fibers. These IPs include various components such as optical transceivers, modulators, and detectors, which convert electronic signals into optical signals and vice versa. This conversion is essential for high-speed data transmission over long distances, a crucial requirement for both enterprise and consumer telecommunications.
Beyond merely converting signals, Optical/Telecom semiconductor IPs must handle complex signal processing tasks to reduce errors, maximize bandwidth, and optimize data integrity. This includes forward error correction (FEC), signal modulation, and wavelength division multiplexing (WDM) technologies. Such capabilities are vital for sustaining the rapidly increasing data loads due to burgeoning internet usage, video streaming, and cloud computing services.
Products in this category of semiconductor IP range from highly sophisticated optical communication modules to integration-ready telecom processors. They are developed to support a broad array of applications, such as backbone internet infrastructures, 5G networks, data centers, and undersea cable systems. These cutting-edge solutions ensure that network providers can offer seamless and reliable service, empowering users with exceptional connectivity experiences. By leveraging advanced Optical/Telecom semiconductor IPs, industries can continue to innovate and meet the ever-evolving demands of a digitally connected world.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The EW6181 GPS and GNSS Silicon is an advanced semiconductor solution specifically engineered for high-efficiency, low-power applications. This digital GNSS silicon offers a compact design with a footprint of approximately 0.05mm2, particularly when applied in 5nm semiconductor technology. Designed for seamless integration, the EW6181 combines innovative DSP algorithms and multi-node licensing flexibility, enhancing the overall device performance in terms of power conservation and reliability. Featuring a robust architecture, the EW6181 integrates meticulously calibrated components all aimed at reducing the bill of materials (BoM) while ensuring extended battery life for devices such as tracking tags and modules. This strategic component minimization directly translates to more efficient power usage, addressing the needs of power-sensitive applications across various sectors. Capable of supporting high-reliability location tracking, the EW6181 comes supplemented with stable firmware, ensuring dependable performance and future upgrade paths. Its adaptable IP core can be licensed in RTL, gate-level netlist, or GDS forms, adaptable to a wide range of technology nodes, assuming the availability of the RF frontend capabilities.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
High-Speed SerDes for Chiplets is engineered to provide exceptional interconnect solutions tailored for chiplet architectures. This product offers ultra-low power consumption while maintaining high data transfer rates, essential for modern multi-die systems. By facilitating rapid communication between chiplets, it enhances overall system efficiency and performance. This SerDes solution is optimized for integration with a range of tech nodes, ensuring compatibility with various semiconductor manufacturing processes. Its design is focused on providing robust data integrity and reducing latency, which are crucial for efficient system operation in complex, integrated circuits. High-Speed SerDes addresses the growing demand for advanced interconnect solutions in chiplet architectures, making it an indispensable tool for developing next-generation semiconductor devices. Its ability to support high data throughput while keeping power use minimal makes it a standout choice in high-performance design environments.
The LightningBlu solution from Blu Wireless is a premier mmWave technology specifically designed to cater to the rigorous demands of high-speed rail connectivity. It provides multi-gigabit, continuous communication solutions between tracksides and trains. This connectivity ensures reliable on-board services such as internet access, entertainment, and passenger information systems. The versatile solution is engineered to perform seamlessly even at speeds greater than 300 km/h, enhancing the passenger experience by delivering consistent, high-speed internet and data services. Built to leverage the 57-71 GHz mmWave spectrum, LightningBlu guarantees carrier-grade connectivity that accommodates the surge of digital devices passengers bring aboard. The technology facilitates a robust communication network that empowers high-speed rail services amidst challenging dynamics and ensures that passengers enjoy uninterrupted service across wide geographic expanses. This significant technical prowess positions LightningBlu as an indispensable asset for the future of rail transport, effectively shaping the industry's move towards digital transformation. With a focus on sustainability, LightningBlu also supports the transition to a carbon-free transport ecosystem, providing an advanced data communication solution that interlinks seamless connectivity with environmentally responsible operation. Its application in rail systems positions it at the heart of modernizing rail services, fostering an era of enhanced rider satisfaction and operational efficiency.
The TSN Switch for Automotive Ethernet is designed to manage real-time data traffic within automotive networks. This high-performance switch provides low-latency communications, making it ideal for modern vehicle architectures that rely heavily on seamless integration and timing precision. Utilizing Time-Sensitive Networking (TSN) protocols, this switch offers enhanced coordination among automotive components, ensuring safety and efficiency in complex vehicular systems. With its robust configuration capabilities, the switch supports the intensive data rates and reliability demands of automotive networks. It's perfectly tailored for the increasingly data-centric environment of smart vehicles, where system reliability and network redundancy are paramount. The TSN Switch excels in providing guaranteed data delivery, essential for applications such as autonomous driving and advanced driver-assistance systems. The integration of this switch into vehicle networks aids in simplifying complex electronic environments, offering manufacturers a scalable solution that adapts to varying production needs. This flexibility ensures that manufacturers can optimize for both current requirements and future advancements in automotive technology. The TSN Switch's comprehensive feature set is aligned with the strict safety requirements of the automotive industry, ensuring compliance with global standards and enhancing vehicle intelligence.
This platform stands out for its ability to offload and accelerate network protocol processing at an impressive speed of up to 100 Gbps using FPGA technology. The Network Protocol Accelerator Platform is designed to enhance network-related tasks, providing distinct performance advantages by leveraging MLE's patented technology. This IP is highly suitable for those requiring efficient data processing in high-speed networking applications, offering scalable solutions from point-to-point connections to complex network systems. The platform's innovation lies in its ability to seamlessly manage a wide array of network protocols, making communication between devices efficient and effective. With its high-speed capability, the platform aids in reducing data processing time significantly. The robustness of this platform ensures that data integrity is maintained across various network tasks, including data acceleration and offloading critical network processes. Furthermore, this platform is particularly useful for industries like telecommunications and data centers where processing large volumes of data rapidly is crucial. The ability to upgrade and maintain such technology provides users with flexibility and adaptability in response to changing network demands. With its broad applicability, the Network Protocol Accelerator Platform remains a strategic asset for enhancing operational efficiency in digital infrastructure management.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The ArrayNav Adaptive GNSS Solution ushers in an era of enhanced automotive navigation, leveraging advanced adaptive antenna technology. This solution expertly applies multiple antennas to increase antenna gain and diversity, offering substantial advancements in navigation precision and operational consistency within complex environments. By integrating array-based technology, ArrayNav is tailored to improve the sensitivity and coverage necessary for sophisticated automotive systems. ArrayNav's use of adaptive antennas translates to significant reductions in issues such as multipath fading, which often affects navigation accuracy in urban canyons. With these enhancements, the solution ensures more reliable performance, boosting accuracy even in challenging terrains or when faced with potential signal interference. This solution has been specifically engineered for applications that demand robustness and precision, such as automotive advanced driver-assistance systems (ADAS). By employing the ArrayNav technology, users can benefit from higher degrees of jamming resistance, leading to safer and more accurate navigation results across a broad range of environments.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The eSi-Comms suite from EnSilica stands as a highly parametizable set of communications IP, integral for developing devices in the RF and communications sectors. This suite focuses on enhancing wireless performance and maintaining effective communication channels across various standards. The modular design ensures adaptability to multiple air interface standards such as Wi-Fi, LTE, and others, emphasizing flexibility and customizability.\n\nThis communication IP suite includes robust components optimized for low-power operation while ensuring high data throughput. These capabilities are particularly advantageous in designing devices where energy efficiency is as critical as communication reliability, such as in wearables and healthcare devices.\n\nMoreover, eSi-Comms integrates seamlessly into broader system architectures, offering a balanced approach between performance and resource utilization. Thus, it plays a pivotal role in enabling state-of-the-art wireless and RF solutions, whether for next-gen industrial applications or advanced consumer electronics.
The 5G NR LDPC Decoder resource by Mobiveil supports advanced LDPC decoding capabilities optimized for modern telecommunication needs. Employing the Min-Sum LDPC decoding algorithm, it allows for programmable bit widths and features early exit iteration capabilities. Support for Hybrid Automatic Repeat Request (HARQ) ensures robustness by accumulating computed LLR values, increasing its efficacy in error correction scenarios.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
PhantomBlu by Blu Wireless represents a cutting-edge advancement in tactical defense communications. This mmWave technology solution is expertly constructed to deliver stealthy, gigabit-level connectivity on the move, supporting high-speed tactical operations. PhantomBlu's low SWAP (Size, Weight, and Power) tactical solutions, configurable as PCP (hub) or STA (client), align with dynamic defense needs by providing dependable communications at range. The system capitalizes on spectrum availability and equipment flexibility, offering interoperability for both legacy systems and future assets without dependence on traditional networks. This capability makes PhantomBlu an invaluable tool for military forces requiring swift, secure, and adaptable communications to maintain operational efficacy in complex environments. The PhantomBlu system plays a pivotal role in transforming how modern military operations are conducted by seamlessly integrating with existing communications bases and enhancing mission-based applications. The flexibility of the configurable options supports high-performance execution, ensuring that military communication networks are responsive and robust in the face of evolving tactical demands.
**Ceva-BX2 baseband processor IP** handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming. It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size. Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators. The Ceva-BX2 combines the capabilities of signal processing and control-code execution into a single, compact DSP. Computational speed comes from quad-32×32/octal-16×16 MACs with added support for 16×8 and 8×8 MAC operations, organized into two parallel compute engines within an 11-stage pipeline. Each compute engine can add optional half- and single-precision IEEE floating-point units. These resources are directed by a five-way VLIW instruction set architecture with optimizations for single-instruction-multiple-data (SIMD) operation, including a hardware loop buffer for kernel execution. Efficient execution of control code is aided by dynamic branch prediction and a branch target cache. On signal-processing tasks the Ceva-BX2 can reach up to 16 GMACs per second, and on control workloads it can achieve up to 5.46 CoreMark/MHz. The hardware design is optimized for speed, achieving 2 GHz operation implemented in a TSMC 7nm process node with only common standard cells and memory compilers. [**Learn more about Ceva-BX2>**](https://www.ceva-ip.com/product/ceva-bx2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_bx2_page)
Designed for maximum compatibility and efficiency, the ATSC 8-VSB Modulator serves both professional TV network applications and custom point-to-point radio links. Its comprehensive compliance with ATSC A/53 8-VSB standards guarantees reliable performance across multiple broadcast scenarios. The modulator's versatile design supports varied operational environments, making it indispensable for broadcasters who require versatile and robust transmission solutions. Its emphasis on delivering flawless signal integrity ensures top-notch broadcast quality for diverse applications.
The ISDB-T Modulator delivers robust capabilities for both professional TV networks and custom point-to-point radio links. This modulator core is fully compliant with ARIB STD-B31 and ABNT NBR 15601, ensuring compatibility across a broad range of broadcasting applications. Its adaptable framework makes it suitable for diverse broadcast needs, facilitating the efficient transmission of digital television signals. Through this, broadcasters can achieve a more reliable and consistent service quality across different market segments.
The DVB-T2 Modulator stands out with its powerful FPGA or ASIC implementation, designed to perform efficient modulation as per the DVB-T2 ETSI EN302 755 standards. This comprehensive solution encompasses all necessary functions to facilitate high-performance terrestrial broadcasts. The modulator is crafted for use in a range of broadcast networks, offering flexibility and adaptability in its application. This makes it a go-to solution for broadcasters aiming to leverage the power of DVB-T2 technology to deliver superior terrestrial broadcast services.
Korusys presents the 12G-SDI Playback and Capture System, engineered for high-resolution video operations. It supports 4K UHD playback and capture with its quad bi-directional 3G-SDI capabilities. Featuring test pattern generation for comprehensive system diagnostics, this solution is ideal for professional environments requiring reliable high-definition video processing. Included as part of a package deal with the High Performance FPGA PCIe Accelerator Card, it offers seamless integration into existing infrastructures for enhanced media capabilities.
The Multi-channel ATSC 8-VSB Modulator enhances broadcasting flexibility by supporting multiple channels within ATSC A/53 8-VSB standards. Tailored to meet professional TV network and custom point-to-point radio link needs, this modulator core facilitates complex broadcast operations. It enables seamless integration and high-quality signal transmission across varied operational environments. By efficiently managing multiple channels, it empowers broadcasters to optimize signal delivery and enhance their overall transmission capabilities.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The Time Sensitive Network (TSN) IP Core by LeWiz Communications is designed to deliver precise, fault-tolerant networking capabilities for mission-critical and space applications. It offers scalability from 1Gbps to 10Gbps, featuring advanced functions such as Babbling Protection and Anti-Masquerading for secure and reliable communication. Utilizing an AXI standard interface, this IP core ensures an easy and seamless integration process with existing systems, enhancing both its usability and functionality. LeWiz has tailored this TSN IP Core to cater to environments where consistent network delivery and timing precision are vital. Its scalability makes it an ideal solution for high-stakes environments within aerospace and defense sectors, where maintaining regular communication and data integrity is imperative. Additionally, the IP core supports various fault-tolerant measures, reducing the potential for network failures and ensuring continuous operation. Designed to comply with stringent industry standards, this IP core can be configured to support a range of virtual links or data streams, aligning with specific customer requirements. Its comprehensive support for time-sensitive applications positions it as a powerful tool in the development of sophisticated networking solutions, providing enhanced reliability and security across complex systems.
The 5G ORAN Base Station is set to redefine the landscape of mobile networking, vastly enhancing wireless data capacity and paving the way for innovative wireless applications. This product is designed to augment connectivity in both urban and rural settings, offering robust data handling capabilities and superior performance. By incorporating open RAN technology, it facilitates interoperability and vendor-neutral platforms, promoting innovation and flexibility. This cutting-edge base station supports a plethora of applications, allowing service providers to deliver high-speed 5G connectivity tailored to specific client needs. Its advanced architecture ensures seamless integration with existing network infrastructure, streamlining the adoption of next-gen technologies. Furthermore, the base station boasts energy-efficient design principles, presenting a sustainable option for expanding mobile broadband offerings. With its modular design, the 5G ORAN Base Station is versatile and scalable, suiting a range of deployment scenarios, from dense urban centers to remote and underserved areas. The inclusion of open interface standards accelerates innovation and reduces deployment costs, offering an optimal solution for service providers aiming to maximize their 5G network investments.
Rockley Photonics' Multi-Channel Silicon Photonic Chipset is engineered for high-speed data transmission applications. The chipset integrates hybrid III-V DFB lasers and electro-absorption modulators into a silicon photonics framework, allowing it to support 4×106Gb/s 400 GBASE-DR4 data rates over multiple channels. This highly efficient setup delivers significant optical modulation amplitude (OMA) and maintains a low TDECQ penalty, fully complying with IEEE standards. This chipset is particularly suited for optical communications, providing the robustness and speed necessary for demanding data centers and telecommunication infrastructures.
The QAM Demodulator from IPrium is a crucial component for modern communication systems, known for its ability to precisely demodulate quadrature amplitude modulated signals. This tool is pivotal for applications requiring the efficient reception and processing of complex data signals. QAM Demodulators decode the amplitude and phase information of signals, providing critical functionalities in systems that demand high bandwidth and reliable data integrity. These demodulators are extensively used in digital television, broadband communications, and data broadcasting, reflecting their versatility in handling high-speed data streams. By utilizing advanced algorithms, IPrium's QAM Demodulator achieves enhanced performance, ensuring minimal signal distortion and high data accuracy. It is designed to cope with varying channel conditions, making it a staple in both commercial and high-end communication systems worldwide.
The DVB-S2X LDPC Decoder from TurboConcept targets satellite communication systems, offering improved error correction for high-throughput data transmission. It complies with the DVB-S2X standard, making it suitable for both broadcast and broadband applications. By incorporating advanced LDPC coding techniques, this decoder enhances signal reliability, reducing the error rate significantly even in challenging atmospheric conditions. This core is perfect for those looking to optimize satellite link performance while maintaining efficient bandwidth utilization. Category IDs: [305, 306]
The SpaceWire Node is a specialized network interface designed to meet the stringent standards of SpaceWire communications. It provides high-speed data transfer up to 200 Mbps and features an AXI-Stream interface for seamless data management, making it ideal for aerospace and defense applications.
Tetrivis' TRV003TSM40LP is a highly advanced RFIC tailored for the LEOSAT market, operating in the Ku-Band range from 10.7GHz to 12.75GHz. This quad Rx-Path device supports dual-beam and dual-polarization configurations, making it ideal for phased array smart antenna systems. The design is realized in a 40nm CMOS process, facilitating enhanced performance and reliability with a 1.1V supply voltage.
The TRV004TSM40LP addresses the demands of LEOSAT systems by delivering a phased array RFIC designed for electronically steerable antennas. It operates within the Ku-Band spectrum, specifically from 14GHz to 14.5GHz, supporting dual-beam, dual-polarization setups. Manufactured using a 40nm CMOS process, this RFIC ensures optimal performance with a supply voltage of 1.1V, providing a robust solution for satellite communications.
The P19800B is a 4GHz RF spectrometer ASIC that represents the second generation of advanced spectrometric analysis. This ASIC is built to facilitate precise RF measurement and analysis, making it an ideal choice for applications where frequency accuracy and signal integrity are paramount. Designed with advanced CMOS and SiGe technology, it promises remarkable performance under various demanding conditions. One of the standout features of the P19800B is its ability to work in complex RF environments with high selectivity and sensitivity. This makes it a valuable tool in fields like telecommunications, remote sensing, and advanced research where accurate RF detection is crucial. Built to handle expansive bandwidths, this spectrometer ASIC aids in maintaining signal clarity and reduces noise interference, enhancing overall operational efficiency. With a focus on delivering superior performance at reduced power consumption, the P19800B accommodates varying design needs. Its robust architecture ensures long-term reliability and adaptability, catering to evolving technological demands. Whether integrated into larger systems or used in standalone roles, this spectrometer ASIC is a versatile component that keeps pace with the fast-changing landscape of advanced RF technology.
An improvement upon its predecessor, the P19800C continues the legacy of precise 4GHz RF analysis by providing enhanced features for even more rigorous applications. Harnessing cutting-edge CMOS technology, this third-generation spectrometer offers a high balance of performance and efficiency, catering to sophisticated RF analysis tasks across varied settings. With an expanded feature set, the P19800C addresses the needs of modern telecommunication systems and remote diagnostics. It boasts an improved noise floor and signal resolution, allowing operators to monitor and control spectral integrity with unmatched precision. The device's versatility allows it to perform in a diverse array of environments, meeting the ever-evolving demands of the RF spectrum. Designed for low power consumption while maintaining high output, the P19800C presents a balance that suits both large and compact systems. Its architecture supports high-level integration with existing platforms, facilitating easy adoption in ongoing projects. As the spectrum's analytical demands grow, the P19800C positions itself as a critical tool in achieving superior RF management and analysis.
The P23801A is an advanced dual-channel spectrometer ASIC renowned for its capability to operate at 10GHz with polarimetric analysis features. This device is engineered specifically for environments demanding high-frequency RF measurements and nuanced spectral analysis, offering functionalities that support complex diagnostics and communication strategies. Featuring dual-channel processing, the P23801A significantly enhances spectral analysis by handling multiple inputs with precision and speed. It is particularly effective in polarimetric contexts, which demand detailed distinction between orthogonal signal components. This capability is invaluable in applications such as advanced radio astronomy, remote sensing, and high-frequency broadband communications. Capable of integrating seamlessly into existing analytic frameworks, the P23801A’s innovative design enhances signal clarity and bandwidth utilization. Its architecture facilitates a comprehensive analysis of both spectral and polarimetric data, thus providing users with a thorough understanding of the RF environment. Such versatility ensures that the P23801A remains a staple for state-of-the-art spectrum analytics.
The AV143 provides a robust platform for high-speed data conversion and signal processing solutions. Built on AMD Virtex Ultrascale+ architecture, it combines advanced ADC and DAC capabilities with high processing power, making it ideally suited for electronic warfare and wideband radar applications. The AV143 supports various communication standards, offering adaptability and flexibility for diverse uses. It has a full suite of software drivers for seamless integration and system management, effectively facilitating data handling and operations across critical applications.
The AV145 is part of a comprehensive suite of high-speed data conversion solutions based on the VPX standard. It features AMD's Zynq Ultrascale+ RFSoC, providing eight 14-bit ADC and DAC channels perfectly aligned for embedded processing in electronic warfare and wideband radar applications. The board supports various communication protocols and stands out with its flexible external reference options, making it highly adaptable for different operational requirements. With powerful processing capabilities and integrated DDR4-2400 SDRAM, it stands as a reliable choice for intensive signal processing tasks.
The AV153 is a leader in ultra-wideband radar and electronic warfare systems. Built on the VITA47 VPX standard, it features cutting-edge Direct-RF technology for seamless integration of FPGA processing and RF operations. With 8x 10-bit ADC and DAC and supporting up to 20 GHz analog bandwidth, the AV153 stands out for applications necessitating high-performance processing and precise RF capabilities. Its comprehensive SOSA compliance ensures smooth interoperability and system integration, making it a favored choice for developers focusing on next-gen radar and telecom solutions.
The AV155 board is a high-performance component in ultra wideband radar, ECM, and SIGINT systems. This 3U VPX platform, powered by the AMD Versal RF VR1652 or VR1952, offers exceptional data processing capabilities with up to 8 channels of 32 Gsps 14-bit ADC and 8 channels of 16 Gsps 14-bit DAC. Designed according to the SOSA standard, it ensures seamless interoperability across radar, electronic warfare, and communication systems. The board features robust DDR5 memory and conduction-cooled design, making it suitable for deployment in harsh environments while ensuring precise timing and data operations.
The P19810B is a specialized correlation radiometer ASIC capable of handling signals up to 10GHz, with a focus on dual-sideband, dual-input operations across 64 channels. This ASIC delivers remarkable performance in signal detection and correlation, pivotal for fields like metrology, atmospheric science, and telecommunications. This correlation radiometer is designed to offer high sensitivity and accuracy, crucial for capturing the subtle nuances in RF signal environments required for precise measurements. The dual-sideband technology allows for greater bandwidth utilization within limited spectral resources, enhancing the effectivity of signal differentiation and analysis. Equipped with robust processing abilities, the P19810B supports complex applications that necessitate detailed correlation of signal inputs. Its multifaceted approach provides the flexibility required in modern analytic tools, ensuring that varying data types are addressed with precision. The P19810B stands as a cornerstone in environments where exactitude and robust analysis are mandatory, integrating seamlessly into larger systems to enhance performance efficiencies.
The AV150 board is engineered for high-speed data conversion and signal processing, adhering to the VPX standard. Equipped with AMD Virtex UltraScale+ FPGA, it combines powerful ADC and DAC capabilities with diverse communication protocol support, including PCIe and Gigabit Ethernet. The AV150 is designed for applications needing extensive I/O and high transceiver bandwidth, maximizing data throughput for real-time processing demands. The platform's flexibility and high integration make it suitable for phased-array radar systems and electronic warfare applications, where adaptability and reconfiguration are key.
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