All IPs > Wireline Communication > Fibre Channel
Fibre Channel semiconductor IPs are crucial components in the infrastructure of high-speed data transfer systems tailored to enterprise storage networking. Known for their reliability and high performance, these semiconductor IPs enable efficient data communication essential for critical data center environments. Fibre Channel technology is a key driver in maintaining seamless connectivity and data flow across enterprise storage networks, ensuring that shared storage resources are accessible, robust, and efficient.
In the realm of wireline communication, Fibre Channel is often chosen for its ability to handle substantial amounts of data traffic with low latency, making it an indispensable technology in settings that require rapid storage and retrieval of information. This technology significantly boosts data handling capabilities and is particularly efficient in managing complex storage area networks (SANs). Moreover, the inherent scalability of Fibre Channel IPs offers enterprises the flexibility to expand and adapt their storage solutions as their data management needs evolve.
Products in this category of semiconductor IP range from basic cores designed for integration into larger system solutions to more advanced IP modules that provide comprehensive functionalities necessary for Fibre Channel implementation. These may include transceiver modules, protocol engines, and physical layer interfaces, all meticulously designed to adhere to industry standards and interoperability requirements. By using Fibre Channel IPs, developers can ensure that their products support high-speed data processing, offering an edge in competitive markets where performance and reliability are paramount.
The adoption of Fibre Channel semiconductor IPs in enterprise networks translates into higher efficiency and enhanced capability to support applications that require substantial bandwidth, such as virtualization and large transactional databases. As data demands continue to grow, leveraging Fibre Channel technology becomes even more critical in the strategic planning of network and storage architecture, providing foundational support for future technological advancements in data management systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The EW6181 GPS and GNSS solution from EtherWhere is tailored for applications requiring high integration levels, offering licenses in RTL, gate-level netlist, or GDS formats. This highly adaptable IP can be ported across various technology nodes, provided an RF frontend is available. Designed to be one of the smallest and most power-efficient cores, it optimizes battery life significantly in devices such as tags and modules, making it ideal for challenging environments. The IP's strengths lie in its digital processing capabilities, utilizing cutting-edge DSP algorithms for precision and reliability in location tracking. With a digital footprint approximately 0.05mm² on a 5nm node, the EW6181 boasts a remarkably compact size, aiding in minimal component use and a streamlined Bill of Materials (BoM). Its stable firmware ensures accurate and reliable position fixations. In terms of implementation, this IP offers a combination of compact design and extreme power efficiency, providing substantial advantages in battery-operated environments. The EW6181 delivers critical support and upgrades, facilitating seamless high-reliability tracking for an array of applications demanding precise navigation.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
The hellaPHY Positioning Solution from PHY Wireless is crafted to optimize IoT deployments across various environments using 5G networks. It melds advanced algorithms with cutting-edge edge computing capabilities to deliver stunningly accurate and efficient location services. The technology, by leveraging existing cellular infrastructures, achieves superior accuracy akin to GNSS systems but at a fraction of the power and data cost, making it ideal for environments where traditional systems falter. What distinguishes hellaPHY is its ability to independently estimate locations within the device, preserving user privacy by avoiding external storage or cloud computation of location data. This self-sufficiency not only ensures data security but also dramatically reduces network congestion, furthering its utility in dense IoT networks. The hellaPHY solution boasts adaptability to existing infrastructure, providing operators with unprecedented spectral efficiency. It allows seamless integration into various devices with minimal impact on current setups, providing a compelling reason for firms to employ this breakthrough technology for boosting IoT scalability and performance.
StreamDSP's MIPI Video Processing Pipeline offers a comprehensive solution for integrating video streams into FPGA-based environments. Supporting Avalon and AXI-4 Streaming protocols, it is highly adaptable to different sensor video formats and frame rates, extending capability to 4K resolutions at 60fps. The pipeline is adept at handling complex processing tasks, including Bayer demosaicing and gamma correction, designed to enhance video output while maintaining minimal latency through optional frame buffering.
SMPTE ST 2110 is a sophisticated protocol designed to facilitate the transport of media over IP networks, commonly used in broadcast and professional AV settings. This IP solution enhances the ability to transmit a variety of media types such as video, audio, and ancillary data via IP, leveraging the modularity to achieve optimal resource efficiency. Supporting an array of sub-standards, including uncompressed video (ST 2110-20) and compressed video (ST 2110-22), this IP bolsters transmission quality and reliability, ensuring consistent system timing and seamless traffic shaping. With its robust support for both gateway and synthetic essence operations, SMPTE ST 2110 enables effective integration with legacy systems and ensures a future-ready setup for the transmission of high-quality media content over IP. The core is highly configurable, allowing users to tailor features according to specific broadcast requirements while maintaining resource efficiency. By utilizing only necessary RTL logic, it minimizes overhead while offering a versatile solution for both professional AV equipment and broadcast systems. Integrated into an ecosystem of proven interoperable standards, this IP ensures smooth transitions between digital and traditional workflows, establishing itself as a pivotal component in AV-over-IP infrastructures. The design includes capabilities to handle various media types, making it adaptable to different operational needs. Nextera’s SMPTE ST 2110 IP is supported by a comprehensive reference design project, inclusive of necessary drivers and control software, enabling rapid system prototyping and deployment. Customers benefit from a well-documented setup that fosters swift development cycles and reduces time-to-market, underpinned by Nextera's emphasis on sustained performance and innovation within IP media experiences.
The CTAccel Image Processor for Intel PAC is crafted to elevate the processing capabilities of data centers by transferring intensive image processing tasks from CPU to FPGA. By exploiting the strengths of Intel's Programmable Acceleration Card (PAC), this IP offers substantial improvements in throughput, latency, and Total Cost of Ownership (TCO). This IP enhances data center efficiency with increased image processing speeds ranging from four to fivefold over traditional CPU solutions, alongside reduced latency by two to threefold. The result is fewer servers needed, translating into lower maintenance and energy costs. Its compatibility with well-known image processing tools ensures that users need not alter their existing setups substantially to benefit from the acceleration offered by the FPGA. Moreover, the CTAccel Image Processor leverages advanced FPGA partial reconfiguration, allowing users to update and adjust computational cores remotely, maximizing performance for specific applications without downtime. This flexibility is pivotal for scenarios involving varied processing loads or evolving computational demands, ensuring uninterrupted performance enhancement.
ARDSoC is a pioneering embedded DPDK solution tailored for ARM-based SoCs, specifically engineered to enhance ARM processor performance by bypassing the traditional Linux network stack. This solution brings the efficiencies of DPDK, traditionally reserved for datacenter environments, into the embedded and MPSoC sphere, extending DPDK functionalities to a broader range of applications. The architecture of ARDSoC allows users to minimize power consumption, decrease latency, and reduce the total cost of ownership compared to conventional x86 solutions. This IP product facilitates packet processing applications and supports various technologies such as VPP, Docker, and Kubernetes, ensuring hardware-accelerated embedded network processing. Designed for integration across Xilinx Platforms, ARDSoC also offers high flexibility with the ability to run existing DPDK programs with minimal modification. It is optimized for performance on ARM A53 and A72 processors, ensuring that data structures are efficiently produced and consumed in hardware, thereby providing robust and reliable network data handling capabilities.
Certus Semiconductor's RF/Analog solutions encompass state-of-the-art ultra-low power wireless front-end technologies. These include silicon-proven RF IPs, full-chip RF products, and next-generation wireless IPs. The RF IPs are compatible with various process nodes, offering comprehensive transceiver solutions integrated with digital controls and modern power management strategies. Specialized for wireless applications, these products include transceivers for LTE, Wifi, GNSS, and Zigbee, each meticulously designed to enhance communication reliability and efficiency in any technology node, from 12nm to 65nm processes.
Serving as a counterpart to the INAP375T, the INAP375R receives high-speed data over a single cable with similar capabilities. This receiver can handle video and audio data without errors, owing to its implementation of the error-correction protocol AShell. It supports flexible connectivity options, adapting to different video interfaces and data configurations required in modern infotainment systems within cars. The robust design ensures compatibility with older APIX devices, thereby delivering seamless integration in automotive communication networks.
APIX3 stands as the third generation of Inova’s APIX technology, engineered to elevate the capacity and functionality of automotive infotainment systems. APIX3 enables the transmission of UHD video over singular or multiple channels, reaching speeds of up to 12 Gbps with quad twisted pair cables. This latest version maintains backwards compatibility with APIX2 and includes advanced diagnostic tools to monitor cable integrity. Its advanced features offer enhanced Ethernet and serial protocol support, meeting a broad spectrum of automotive communication needs.
Ethernet solutions are a suite of sophisticated design and verification IPs tailored for high-speed networking applications. They are continuously enhanced to comply with the latest specifications while ensuring compatibility with previous standards.\n\nThese solutions encompass a wide range of Ethernet MAC, PCS, and switch components, supporting speeds from 1G to 800G. They are strategically built to manage various data transfer requirements, providing robust performance across networks of different capacities and infrastructures. Additionally, support for AFDX, CPRI, and eCPRI controllers widens the scope for telecommunications and aerospace applications.\n\nPRSemicon's Ethernet IPs are critical for building efficient, high-speed networks that provide the backbone for modern communication systems. Their comprehensive support and adaptability make them a preferred choice in ensuring resilient and reliable connectivity across numerous platforms.
The INAP590T combines advanced transmission capabilities with cutting-edge security features like HDCP support. It facilitates the secure transmission of video and audio data, supporting high-definition multimedia interfaces. Aimed primarily at automotive infotainment systems, this transmitter offers scalable bandwidth options, ensuring that even with the transmission of multiple video streams, data integrity and speed are not compromised. Its ability to adapt to various transmission setups makes it a core component in the latest infotainment architectures.
The Ethernet 10/100 MAC provided by MosChip is engineered to enable seamless network connectivity for embedded devices. This IP core is designed to support both 10 and 100 Mbps data transfer rates, ensuring versatile network communication in a variety of applications. The architecture of this Ethernet MAC is optimized for low power consumption and high-speed operation, which is ideal for integration into consumer electronics and industrial IoT devices. This module features a highly configurable design, allowing it to be seamlessly integrated into existing systems with minimal modification required. It also possesses robust support for both full-duplex and half-duplex modes, catering to diverse networking environments. The IP core includes advanced functionalities such as VLAN support and checksum offload, enhancing its utility in complex networking setups. Additionally, the Ethernet 10/100 MAC is compliant with IEEE 802.3 standards, ensuring compatibility and interoperability with a wide range of networking equipment. This makes it a key component in projects that demand reliable and efficient network interfaces, further bolstering MosChip's reputation as a provider of high-quality semiconductor solutions.
The INAP375T is a feature-rich transmitter designed for high-speed differential data transmission. It uses APIX2 technology, enabling efficient data transfer over a single twisted pair (STP) cable at speeds up to 3Gbps. This transmitter supports flexible frame configurations filled with video, audio, and data, adaptable to various automotive applications. The device incorporates advanced protocols such as AShell for safety-critical data transmission and offers backward compatibility with previous APIX versions, making it versatile for integrated into existing and new systems.
Specifically designed for WiFi 7, the 14-bit 1Gsps Pipeline ADC offers advanced analog-to-digital conversion capabilities, essential for managing high-bandwidth data streams. This ADC supports fast data rates, ensuring seamless signal processing in applications that experience intense data loads. As an integral part of next-generation communication protocols, this Pipeline ADC stands out in its ability to maintain high fidelity while processing large volumes of information, a necessity for the robust demands of WiFi 7 technology. The ADC's architecture supports swift data handling, minimizing latency and facilitating high-speed operations. With an adaptable structure designed to handle rapid environmental changes, this ADC integrates intelligence features like self-calibration and automatic error correction, enhancing long-term reliability. Its cutting-edge design positions it as a key component in the advancement of high-speed wireless communication systems.
The Dual Channel 12-bit 640MS/s ADC has been crafted for WiFi 6 applications, focusing on delivering efficient and accurate analog-to-digital conversions. This component supports dual signal processing, allowing for enhanced data capture and conversion that meets the high-speed demands of the latest wireless networks. By offering dual processing channels, this ADC excels in managing multiple data streams, ensuring that wireless communication signals are converted swiftly and with high accuracy. Its architecture is designed to cope with substantial data rates, confirming its suitability for advanced telecom protocols. Features like real-time adaptive calibration bolster the ADC's capability to maintain consistent operation in dynamic network conditions. This adaptability is fundamental for extending the functionality and effectiveness of WiFi 6 infrastructure, supporting seamless operations and high data integrity.
The RT125 by Rafael Micro is a 28Gbps SR CDR/LA/TIA designed to address the high-speed demands of optical communication systems. This component integrates a Clock Data Recovery (CDR) module, Limiting Amplifier (LA), and Trans-Impedance Amplifier (TIA) in a coherent architecture aimed at providing robust signal integrity even in demanding data rates. Engineered for high-speed environments, the RT125 optimizes data recovery processes with its CDR component, ensuring accuracy in signal timing alignment and reducing jitter. The Limiting Amplifier provides optimal signal amplification, refining signal resolution without introducing significant noise. Complementing this is the Trans-Impedance Amplifier, which transforms optical signals into usable electronic formats with heightened sensitivity. This integrated solution is particularly advantageous in data center interconnects and high-speed telecommunication networks. Its ability to handle complex optical signals with precision and efficiency distinguishes it in the arena of short-reach communication systems, where rapid data processing and minimal error rates are critical. Rafael Micro's RT125 paves the way for advancements in quick and dependable high-speed data link developments.
The Dual Channel 12-bit 1GS/s ADC is developed for the advanced needs of 5G and WiFi 6 protocols. This ADC caters to the high-speed processing requirements essential for modern wireless communication standards, enabling rapid and precise conversion of analog signals for enhanced digital interpretation. The dual-channel capability facilitates simultaneous processing of two independent streams, optimizing the ADC for multi-signal environments typical in wireless communication systems. With a focus on handling large data volumes efficiently, it plays a crucial role in maintaining data integrity and throughput in communication networks. Designed with a robust architecture, this ADC integrates dynamic tuning features and self-calibration to ensure optimum performance amidst variable network conditions. These functionalities enhance the reliability and longevity of the device, supporting its use in cutting-edge communication technologies.
Optimized for the ever-evolving demands of 5G and WiFi 6 technologies, the Dual Channel 12-bit 4GS/s ADC supports dual data processing with high precision. This ADC is designed to manage the tremendous data transfer rates required by modern telecommunications infrastructure, ensuring efficient and accurate analog-to-digital conversion. The device's impressive speed facilitates substantial data handling capabilities, making it ideal for extensive signal environments. Its double-channel configuration ensures seamless processing of simultaneous data streams, crucial for keeping pace with the rapid development of wireless technologies. Dynamic calibration and adaptive intelligence are core features of this ADC, enabling it to maintain peak performance amidst shifts in operational conditions. Such attributes are critical to extending the lifecycle and reliability of data transfer systems, enabling them to meet and exceed future communication standards.
This Dual Channel 12-bit 2GS/s ADC is engineered to support the massive data requirements of 5G and WiFi 6, offering dual processing channels to handle complex signal architectures. Designed for high-speed digital conversion, it ensures precise and rapid interpretation of analog signals in demanding telecommunication systems. With these robust capabilities, this ADC significantly enhances data throughput and error resilience, crucial for maintaining high efficiency and reliability in modern communication networks. The dual-channel interface allows for parallel data processing, enhancing processing efficiency and system performance. Embedded with advanced real-time calibration and error correction technology, this ADC ensures consistent operation across a range of conditions, fostering longevity and reliability. Its capacity to sustain high data rates makes it indispensable in modern digital infrastructure.
This ADC, with a 14-bit resolution and a sampling rate of 3.2Gsps, paired with a 75MHz bandwidth, is crafted for advanced radar systems. The impressive specifications ensure high-speed, accurate, analog-to-digital conversions which are critical in accurately capturing and processing radar signals. High-speed sampling allows for rich data capture, imperative for systems requiring precise detection and measurement capabilities. The wide bandwidth of 75MHz ensures a broad array of frequencies can be effectively managed, further enhancing the radar's detailed analytical capacity. Incorporating intelligent design features, this ADC utilizes self-tuning and error mitigation techniques to adjust to varying operational conditions, thus ensuring stable, continuous performance. These attributes make it invaluable in military and civil radar applications seeking high levels of accuracy and reliability.
The 14-bit 1.3Gsps ADC with a 40MHz bandwidth is tailored for radar applications, providing the critical precision required in environments where detecting even minute changes in radar signals is imperative. This ADC is instrumental in converting high-frequency analog signals to digital form with superb speed and accuracy. Designed for radar systems, it supports high sampling rates, allowing real-time data processing and analysis which is vital for timely and accurate response to changing conditions. The expansive bandwidth ensures that a wide range of frequencies can be captured and analyzed effectively. Adapted to function under both typical and extreme conditions, this ADC maintains performance through advanced calibration and error correction features. It emphasizes reliability and operational longevity, enabling its integration into complex radar environments where precision is paramount.
The RT923 by Rafael Micro is a 10Gbps Trans-Impedance Amplifier (TIA) tailored for optical communication environments demanding high sensitivity and precision signal amplification. This TIA is an integral component in converting optical signals to electronic signals, ensuring clean and amplified outputs essential for effective data interpretation. With a design focused on minimizing noise, the RT923 excels in delivering high signal-to-noise ratios, crucial for maintaining signal integrity during high-speed data transmissions. Its wide dynamic range allows it to accommodate varying input conditions while preserving the fidelity of the received signal, making it ideal for diverse communication scenarios. This amplifier finds its application in fiber-optic communication systems, enabling efficient transmission over long distances without degradation. Whether used in data centers, telecommunication networks, or consumer electronics, its precise signal processing capabilities enhance both the performance and reliability of these systems. Rafael Micro's RT923 TIA is a testament to advanced engineering for modern digital communication solutions.
KMX 10G MAC and PCS core, which includes media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC defined in IEEE 802.3 Clause 108 with independent bit error detection and bit error correction. It connects to user logic via AXI4-Stream interface of 64 bits at 156.25MHZ and to 10G PCS core via XGMII interface of 64 bits at 156.25 MHZ. It also connects to user logic via AXI4-Lite interface. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It receives packets from 10G PCS via XGMII interface and generates new format packet by removing Preamble/SFD and 32 bit CRC after CRC checking. It supports Pause Frame processing for flow control and Implements Deficit Idle Count algorithm to ensure maximum possible throughput at the transmit interface. It implements internal XGMII loopback for debug purpose, which at the XGMII interface, the data flow on TX path is redirected to RX path and no data is forwarded to XGMII TX interface. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q. KMX 10G PCS module connects to 10G MAC module via XGMII of 64 bits at 156.25MHZ and connects to transceiver interface at 64 bits at 161.1328125MHZ. The PCS core is compliant with IEEE 802.3ba specifications. The core supports the following features: It implements 64b/66b encoding/decoding. The core supports 10G scrambling/descrambling of polynomial 1 + x^39 + x^58. It implements gearbox on both TX and RX. The 66-bit block synchronization algorithm implementation is included. The BIP-8 generation/insertion on TX and checking on RX are supported. It implements Bit Error Rate (BER) for monitoring excessive error ratio. The transceiver interface loopback for debug purpose is implemented, which at transceiver interface, the data flow on TX path is redirected to the RX path and no data is forwarded to transceiver TX interface. The core supports link signaling protocol.
Zipcores' Binary-PSK Demodulator offers a precise solution for Binary Phase Shift Keying demodulation, providing exceptional performance in low-cost radio links. It handles symbol rates up to 10 Mbps effectively, delivering reliable reception across several hundred meters. The demodulator’s simplified setup does away with the need for complex Phase-Locked Loop (PLL) tuning, allowing for quick deployment with minimal configuration. Its inherent strengths include excellent noise immunity and a wide dynamic range, ensuring robust communication and data integrity in demanding radio frequency (RF) environments. Its design is optimized for ease of integration, making it a valuable asset in RF systems requiring efficient phase demodulation.
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