All IPs > Wireline Communication > Fibre Channel
Fibre Channel semiconductor IPs are crucial components in the infrastructure of high-speed data transfer systems tailored to enterprise storage networking. Known for their reliability and high performance, these semiconductor IPs enable efficient data communication essential for critical data center environments. Fibre Channel technology is a key driver in maintaining seamless connectivity and data flow across enterprise storage networks, ensuring that shared storage resources are accessible, robust, and efficient.
In the realm of wireline communication, Fibre Channel is often chosen for its ability to handle substantial amounts of data traffic with low latency, making it an indispensable technology in settings that require rapid storage and retrieval of information. This technology significantly boosts data handling capabilities and is particularly efficient in managing complex storage area networks (SANs). Moreover, the inherent scalability of Fibre Channel IPs offers enterprises the flexibility to expand and adapt their storage solutions as their data management needs evolve.
Products in this category of semiconductor IP range from basic cores designed for integration into larger system solutions to more advanced IP modules that provide comprehensive functionalities necessary for Fibre Channel implementation. These may include transceiver modules, protocol engines, and physical layer interfaces, all meticulously designed to adhere to industry standards and interoperability requirements. By using Fibre Channel IPs, developers can ensure that their products support high-speed data processing, offering an edge in competitive markets where performance and reliability are paramount.
The adoption of Fibre Channel semiconductor IPs in enterprise networks translates into higher efficiency and enhanced capability to support applications that require substantial bandwidth, such as virtualization and large transactional databases. As data demands continue to grow, leveraging Fibre Channel technology becomes even more critical in the strategic planning of network and storage architecture, providing foundational support for future technological advancements in data management systems.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
The Jotunn 8 is heralded as the world's most efficient AI inference chip, designed to maximize AI model deployment with lightning-fast speeds and scalability. This powerhouse is crafted to efficiently operate within modern data centers, balancing critical factors such as high throughput, low latency, and optimization of power use, all while maintaining a sustainable infrastructure. With the Jotunn 8, AI investments reach their full potential through high-performance inference solutions that significantly reduce operational costs while committing to environmental sustainability. Its ultra-low latency feature is crucial for real-time applications such as chatbots and fraud detection systems. Not only does it deliver high throughput needed for demanding services like recommendation engines, but it also proves cost-efficient, aiming to lower the cost per inference crucial for businesses operating at a large scale. Additionally, the Jotunn 8 boasts performance per watt efficiency, a major factor considering that power is a significant operational expense and a driver of the carbon footprint. By implementing the Jotunn 8, businesses can ensure their AI models deliver maximum impact while staying competitive in the growing real-time AI services market. This chip lays down a new foundation for scalable AI, enabling organizations to optimize their infrastructures without compromising on performance.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
APIX3 technology represents the pinnacle of data communication solutions for advanced automotive infotainment and cockpit systems. It supports ultra-high definition video resolutions, facilitated by its capacity for multi-channel high-speed data transmission. The technology enables a scalable bandwidth that adapts from entry-level to luxurious, high-end automotive systems, ensuring a broad range of application compatibilities. APIX3 modules are engineered to transmit data at rates of up to 6 Gbps over a shielded twisted pair cable and up to 12 Gbps over a quad twisted pair. This makes them invaluable in systems requiring high levels of data integrity and precision, such as those found in modern, connected vehicle architectures. In addition to supporting complex video channels, APIX3 is compatible with 100 Mbps Ethernet and integrates advanced diagnostic capabilities for cable monitoring, which allows for predictive maintenance by detecting cable degradation. Its backwards compatibility with APIX2 ensures seamless integration and upgradability in existing infrastructures, reinforcing its status as a future-proof solution.
The iCan PicoPop® System on Module offers a compact solution for high-performance computing in constrained environments, particularly in the realm of aerospace technology. This system on module is designed to deliver robust computing power while maintaining minimal space usage, offering an excellent ratio of performance to size. The PicoPop® excels in integrating a variety of functions onto a single module, including processing, memory, and interface capabilities, which collectively handle the demanding requirements of aerospace applications. Its efficient power consumption and powerful processing capability make it ideally suited to a range of in-flight applications and systems. This solution is tailored to support the development of sophisticated aviation systems, ensuring scalability and flexibility in deployment. With its advanced features and compact form, the iCan PicoPop® System on Module stands out as a potent component for modern aerospace challenges.
The INAP375R Receiver complements its transmitter counterpart in offering comprehensive high-speed data reception for automotive applications. It supports multiple video and audio channels, facilitating seamless data conversion and transfer for automotive entertainment systems. Designed to work effectively with up to 12 meters of cable, the receiver ensures consistent data fidelity over distance. Incorporating an advanced current mode logic, the INAP375R efficiently handles differential signals, maintaining data integrity even in demanding environments. Its capacity to deliver up to 3Gbps over a single cable ensures compatibility with various automotive applications, be it infotainment or safety-related systems. The versatile interface options of the INAP375R enable it to adapt to varying automotive standards while ensuring reliable performance. With built-in support for AShell protocol for error detection and correction, the receiver guarantees the safe and accurate transmission of critical data across automotive networks, underpinning its suitability for high-reliability applications.
Designed specifically for high-speed automotive data communication, the INAP590T transmitter handles demanding data loads effectively. This device supports robust video data transmission and is innovatively tailored for automotive environments, ensuring high levels of integration and performance. The INAP590T is built with features that accommodate HDMI and DSI interfaces, ensuring seamless adaptability. Its capacity for managing dual video channels highlights its applicability in complex automotive infotainment systems. The INAP590T also supports AShell channels and Ethernet functionalities, underscoring its versatility in handling comprehensive automotive data transmission requirements. Notably, the transmitter supports dual-port communication, enhancing its utility in modern automotive networking. With its focus on high-fidelity data transfer and the ability to handle diverse formats, it represents a pivotal component in advancing vehicle connectivity and infotainment solutions.
Terminus Circuits' SerDes PHY is engineered to accommodate a diverse array of market needs, spanning network communication, PC interconnects, data storage, and beyond. This IP provides unmatched power efficiency and latency reduction, integral for industries such as aerospace, defense, and industrial applications that demand dependable data communication solutions. Offering tight integration with existing controllers ensures seamless interoperability and enhances the potential for tailored system solutions. The PHY's quad configuration supports multiple data lanes, optimizing the balance between bandwidth and latency across various standards such as PCI Express, USB, and DisplayPort. Equipped with advanced features such as tightly-controlled termination resistors, adaptive equalization, and loopback modes, this SerDes PHY ensures robust performance across all operational scenarios. Its ultra-low latency and low power usage make it a prime candidate for high-performance environments demanding reliability and efficiency.
StreamDSP's MIPI Video Processing Pipeline is crafted for seamless integration into advanced embedded systems, offering a turnkey solution for video handling and processing. It supports the MIPI CSI-2 and DSI-2 standards, allowing it to process various video formats and resolutions efficiently, including ultra-high-definition video. The architecture is designed to work with or without frame buffering, depending on latency needs, enabling system designers to tailor performance to specific application requirements. This flexibility ensures that StreamDSP's video pipeline can handle the demands of cutting-edge video applications like real-time video analysis and broadcast video streaming, while maintaining optimal resource usage.
The CTAccel Image Processor for Intel PAC is crafted to elevate the processing capabilities of data centers by transferring intensive image processing tasks from CPU to FPGA. By exploiting the strengths of Intel's Programmable Acceleration Card (PAC), this IP offers substantial improvements in throughput, latency, and Total Cost of Ownership (TCO). This IP enhances data center efficiency with increased image processing speeds ranging from four to fivefold over traditional CPU solutions, alongside reduced latency by two to threefold. The result is fewer servers needed, translating into lower maintenance and energy costs. Its compatibility with well-known image processing tools ensures that users need not alter their existing setups substantially to benefit from the acceleration offered by the FPGA. Moreover, the CTAccel Image Processor leverages advanced FPGA partial reconfiguration, allowing users to update and adjust computational cores remotely, maximizing performance for specific applications without downtime. This flexibility is pivotal for scenarios involving varied processing loads or evolving computational demands, ensuring uninterrupted performance enhancement.
Ethernet Solutions from PRSsemicon deliver cutting-edge network interfaces ranging from 1G to 800G, including MAC, PCS, and switch components. This extensive suite enables robust and scalable networking capabilities suited to various environments, including data centers and enterprise networks. The solutions are designed to support both traditional Ethernet and advanced functionalities, ensuring optimal performance, reliability and data integrity across various applications in telecommunications and beyond.
ARDSoC introduces Data Plane Development Kit (DPDK) capabilities to the ARM-based System on Chip (SoC) domain, bypassing the traditional Linux network stack to save valuable ARM processor cycles. Designed specifically for embedded MPSoC environments, ARDSoC streamlines the transition of existing DPDK programs with minimal adjustments, bringing powerful data manipulation capabilities to devices with ARM architecture. This solution is particularly beneficial in reducing the power, latency, and total cost of ownership for applications transitioning from x86 frameworks to ARM structures. ARDSoC provides a zero-copy memory structure enhancing cache performance, along with an optimized Poll Mode Driver (PMD) that ensures minimal latency by maintaining data proximity to processing nodes. Notably, it harmonizes with a range of applications, from embedded protocol bridges to cloud-edge networks that demand robust packet processing. Among its many features, ARDSoC enables seamless packet vector and container-aware processing, supporting various platforms like VPP and Kubernetes. Compatible with Xilinx platforms, ARDSoC facilitates swift integration and testing, allowing developers to leverage the inherent flexibility and performance advantages in diverse networking and cloud computing scenarios.
The INAP375T Transmitter is a high-performance device engineered to enhance serial data transmission. Leveraging state-of-the-art technology, this transmitter offers robust support for high-speed video channels, Ethernet, as well as audio channels, making it ideal for applications in automotive infotainment. The device features current mode logic for its physical layer, ensuring reliable and long-distance data transmission over a single twisted pair cable. This flexibility in transmission format allows the INAP375T to cater to various use cases, from video streaming to audio data interchange. Designed with versatility in mind, the INAP375T supports up to 12 meters of transmission distance at impressive gigabit speeds. This makes it suitable for complex automotive architectures where reliability and data integrity are paramount. The transmitter includes advanced AShell protocol support to optimize data handling and ensure error-free communication. The INAP375T is equipped to handle dual video channels with RGB/LVDS support, enabling seamless integration in advanced automotive video systems. The device’s diverse configuration options, accessible via SPI and I2C interfaces, enhance usability and adaptability. This transmitter is well-matched for high-demand environments where precision and high data throughput are critical.
Certus Semiconductor's RF/Analog solutions encompass state-of-the-art ultra-low power wireless front-end technologies. These include silicon-proven RF IPs, full-chip RF products, and next-generation wireless IPs. The RF IPs are compatible with various process nodes, offering comprehensive transceiver solutions integrated with digital controls and modern power management strategies. Specialized for wireless applications, these products include transceivers for LTE, Wifi, GNSS, and Zigbee, each meticulously designed to enhance communication reliability and efficiency in any technology node, from 12nm to 65nm processes.
The Ethernet 10/100 MAC by MosChip is designed to streamline networking capabilities with a focus on flexibility and efficiency. This module is pivotal for guaranteeing high-speed and stable networking connections within integrated systems. Suitable for diverse applications, it supports various communications that require robust data transfer rates.
The Akeana 1000 Series represents a mid-range selection of high-performance processors tailored for data-driven applications involving extensive computation. Featuring a 64-bit RISC-V architecture, these processors are designed for flexibility and customization, supporting multi-threading and both in-order and out-of-order execution to deliver optimal performance across a variety of uses. These processors are highly suitable for applications such as edge AI, industrial automation, and automotive sensing. With configurable instruction width (from one to four ways) and robust memory management features, including a TLB of up to 512 entries, they efficiently handle a wide span of computational demands. Furthermore, the series is equipped with Rich OS systems support, embracing features like hypervisor and vector extensions to enhance their computation capabilities. Among the standout features of the Akeana 1000 Series are its multi-threaded architectures and scalable functionalities, which allow seamless integration into smart homes, wearables, and automotive environments. This series is designed to handle sophisticated software and hardware interactions with ease, ensuring quick adaptability in rapidly advancing technological domains.
KMX 10G MAC and PCS core, which includes media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC defined in IEEE 802.3 Clause 108 with independent bit error detection and bit error correction. It connects to user logic via AXI4-Stream interface of 64 bits at 156.25MHZ and to 10G PCS core via XGMII interface of 64 bits at 156.25 MHZ. It also connects to user logic via AXI4-Lite interface. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It receives packets from 10G PCS via XGMII interface and generates new format packet by removing Preamble/SFD and 32 bit CRC after CRC checking. It supports Pause Frame processing for flow control and Implements Deficit Idle Count algorithm to ensure maximum possible throughput at the transmit interface. It implements internal XGMII loopback for debug purpose, which at the XGMII interface, the data flow on TX path is redirected to RX path and no data is forwarded to XGMII TX interface. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q. KMX 10G PCS module connects to 10G MAC module via XGMII of 64 bits at 156.25MHZ and connects to transceiver interface at 64 bits at 161.1328125MHZ. The PCS core is compliant with IEEE 802.3ba specifications. The core supports the following features: It implements 64b/66b encoding/decoding. The core supports 10G scrambling/descrambling of polynomial 1 + x^39 + x^58. It implements gearbox on both TX and RX. The 66-bit block synchronization algorithm implementation is included. The BIP-8 generation/insertion on TX and checking on RX are supported. It implements Bit Error Rate (BER) for monitoring excessive error ratio. The transceiver interface loopback for debug purpose is implemented, which at transceiver interface, the data flow on TX path is redirected to the RX path and no data is forwarded to transceiver TX interface. The core supports link signaling protocol.
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