All IPs > Wireline Communication > Error Correction/Detection
In the realm of wireline communication, ensuring the integrity and reliability of data transmission is a critical concern. This is where Error Correction and Detection semiconductor IPs play a pivotal role. These IPs are designed to identify and rectify errors that occur during data transmission, thus enhancing the overall performance and reliability of wireline communication systems. Whether it involves correcting single-bit errors or detecting complex data discrepancies, these IPs are essential for maintaining the fidelity of data transmission.
Error Correction and Detection IPs utilize various sophisticated algorithms and techniques such as Reed-Solomon, Hamming Code, and Cyclic Redundancy Check (CRC). These technologies work by adding redundancy to the data being transmitted, allowing the receiver to detect errors and, in many cases, automatically correct them. This process not only protects data integrity but also ensures higher quality of service, reducing the need for retransmissions and improving network efficiency.
These semiconductor IP blocks are implemented in a wide array of applications including broadband networks, data centers, and telecommunication systems where uninterrupted and accurate data transmission is paramount. For engineers and developers, leveraging these IPs can significantly accelerate the development process of wireline systems by providing ready-to-integrate solutions that uphold communication standards.
In this category, you will find a vast selection of Error Correction and Detection semiconductor IPs suited for various applications. These IPs are available from leading suppliers, offering solutions that support multiple protocols and data rates. With these IPs, developers can ensure their wireline communication products are robust, reliable, and capable of delivering the highest levels of performance needed in today's data-driven world.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
AccelerComm's LDPC solution stands out for its innovative design that marries block-parallel and row-parallel architectures to deliver peak performance and efficiency. Primarily designed for 5G NR use cases, this product supports both data and control channels, proving its versatility across different communication requirements. With a focus on maximizing throughput and minimizing latency, the LDPC decoder is optimized for various hardware formats, including ASIC, FPGA, and software implementations. It supports a wide range of configurations, allowing it to adapt to specific performance requirements across applications. This LDPC solution has been rigorously validated against IEEE standards and offers enhanced error correction capabilities within a compact design. By reducing resource demands while improving overall communication reliability, it exemplifies AccelerComm's commitment to leading-edge technological solutions.
AccelerComm's High PHY Accelerators provide a suite of IP cores designed to boost signal processing capabilities for 5G New Radio applications. Integrating patented high-performance algorithms, this library of accelerators ensures peak throughput and efficiency, facilitating robust signal processing across ASIC, FPGA, and SoC platforms. These accelerators are characterized by their ability to significantly reduce latency and improve spectral efficiency, making them indispensable in high-demand environments. By supporting a wide array of features, including high-throughput modulation/demodulation and sophisticated error correction techniques, the accelerators empower systems to handle intricate data transmission with precision. Moreover, these accelerators seamlessly integrate with existing hardware platforms, offering a versatile solution for enhancing signal processing in diverse network scenarios. Their robust design and functionality reflect AccelerComm's commitment to driving innovation in communication technologies.
Polar encoding and decoding for 5G NR leverages AccelerComm's expertise in creating sophisticated IP that reduces resource and memory demands while delivering superior BLER performance. This solution, selected for 5G NR control channels, utilizes PC- and CRC-aided SCL polar decoding techniques to achieve high error correction accuracy. The polar IP is fully compliant with 3GPP NR standards, encompassing the entire encoding and decoding chain required for seamless integration. It offers high levels of parallel processing and scalability, making it suitable for diverse applications, from simple to complex data transmission systems. With its configurable design, the Polar IP allows adjustments in decoder list size to best fit specific BLER and PPA requirements. This flexibility, combined with its efficient integration capabilities, underscores its role as a critical enabler of efficient, high-performance wireless communication solutions.
The High Speed Data Bus (HSDB) solution offers a comprehensive hardware implementation for the HSDB's PHY and MAC layers. Designed to facilitate seamless integration into high-speed data transfer environments, this component ensures reliable communication within F-22 compatible systems. Its easy-to-integrate frame interface supports rapid deployment in complex aerospace applications, making it invaluable for organizations seeking robust data transmission solutions in mission-critical scenarios. By focusing on delivering superior bandwidth operations, this core supports stringent performance standards for high-speed data usage, essential in modern aerospace and defense settings. The HSDB IP Core prioritizes seamless communications with minimal latency, catering specifically to real-time applications. Its architecture is engineered for adaptability and high-speed operations, meeting the rigorous demands presented by intricate military communications systems. Overall, the HSDB solution represents a pinnacle of high-precision engineering, tailor-made for defense-related data operations.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The nxFeed Market Data System is an FPGA-based feed handler that revolutionizes market data processing by using hardware to enhance speed and efficiency. By normalizing data feeds into a simple and consistent API, nxFeed significantly reduces the server resources and latency associated with data handling. This system is especially beneficial for electronic trading applications requiring synchronized and fast market data updates. Designed to integrate easily into existing systems, nxFeed offers both local PCIe delivery and UDP multicast for distributed applications, allowing for flexibility in deployment. Its robust API ensures that integration can be achieved rapidly, often within a week, without the need for dedicated FPGA hardware during development. The system offers a central management structure with tools for latency statistics and live monitoring. With nxFeed, developers can focus on core business logic while the system handles complex feed arbitration, decoding, and normalization. It's particularly useful for firms looking to develop proprietary trading algorithms or manage volatile exchange feeds. The solution supports up to 250,000 symbols per card, making it an ideal choice for high-demand trading environments.
Arteris's Ncore Cache Coherent Interconnect IP addresses the complex challenges of multi-core ASIC development, offering a scalable, highly configurable solution for coherent network-on-chip designs. This IP supports multiple protocols, including Arm and RISC-V, and is engineered to comply with ISO 26262 for safety-critical applications. Ncore enables seamless communication and cache coherence across varied processor cores, enhancing performance while meeting stringent functional safety standards. Its capability to automate Fault Modes Effects and Diagnostic Analysis (FMEDA) further simplifies safety compliance, proving its value in advanced SoCs where reliability and high throughput are critical.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The DVB-S2-LDPC-BCH core is Wasiela's robust solution for digital video broadcasting, particularly geared towards satellite applications. It implements a sophisticated forward error correction system combining LDPC and BCH codes, enabling operations close to the theoretical limits of error-free communication. The system features an irregular parity check matrix and utilizes a layered decoding process accompanied by the minimum sum algorithm for soft decision decoding. The BCH aspect operates on specified finite fields, capable of correcting multiple error variations, making this core highly reliable for broadcasting environments.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Dual-Drive™ Power Amplifier FCM2801-BD represents another leap forward in Falcomm's quest to redefine power efficiency in mmWave-based devices. Centered at 28 GHz, this power amplifier emerges as a pivotal component for next-generation wireless communication technology. The architecture of the FCM2801-BD is engineered to deliver industry-leading drain efficiencies, optimizing both power consumption and performance. It is notably characterized by its robust reliability and exceptional energy management capabilities, tailored for applications where performance excellence is paramount. With a core design that exploits the potentials of GaN and SiGe technologies, the FCM2801-BD ensures superior amplification with minimized energy wastage. Its sophisticated signal processing enhances device output without significant power blowouts. The advanced manufacturing processes adopted promise reduced manufacturing footprint, making it an ideal choice for highly compact and low-footprint technology designs. Engineered for space communications, wearables, and innovative telecommunication systems, the FCM2801-BD champions Falcomm’s vision of marrying exceptional performance with eco-friendly designs. This model’s dependability in high-demand scenarios complements its capability to lower operational expenses across communication systems internationally. In conclusion, the FCM2801-BD is not only a technological marvel from Falcomm but also a commitment to the ethos of sustainability and resource efficiency.
AccelerComm offers a comprehensive physical layer solution for 5G New Radio (NR), tailored to high-performance satellite and O-RAN applications. This solution seamlessly integrates with existing systems and optimizes power, performance, and area considerations. The product's inherent flexibility allows it to adapt to a variety of platforms, including ARM processors, FPGAs, and ASICs, ensuring broad applicability across different hardware environments. The Complete 5G NR Physical Layer makes use of patented signal processing algorithms to deliver high link performance, aiding in the reduction of latency and enhancement of spectral efficiency. Designed with 3GPP compliance in mind, the solution supports the entire processing chain, ensuring that users benefit from reduced errors and maximized throughput. Furthermore, this physical layer solution is enhanced by its support for cutting-edge features like rate matching and HARQ protocols. Highly configurable, it allows for integration with various platforms, which underscores AccelerComm's commitment to providing versatile and efficient solutions tailored for modern 5G networks.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Optimized for leading FPGA architectures, the UDP/IP Ethernet IP core facilitates seamless Ethernet communication using the UDP protocol. It is engineered to enable high-speed data transmission at up to 1 Gbit/sec, with the capability of operating across various media independent interfaces, including MII, RMII, GMII, and RGMII. The IP core simplifies the integration of Ethernet communication by handling full UDP, IPv4, and Ethernet layer processing. It supports automatic ARP reply generation and allows UDP and Ethernet frame checks to ensure reliable data transmission. With a design that minimizes FPGA resource usage, it provides robust communication solutions for test and measurement, embedded processing, and automation tasks. This IP core's architecture supports multiple UDP port operations with dedicated interfaces for transmitting and receiving data. Its selective header processing capabilities allow for custom handling of UDP/IP/ETH headers, enriching the customization potential for complex communication needs. The inclusion of raw Ethernet ports further expands its utility beyond traditional UDP applications.
The DVB-C Demodulator is a specialized core designed for decoding digital video broadcast signals, specifically tailored toward cable systems. Compliant with the DVB-C and J83 modulation standards, this demodulator is crucial for cable networks aiming to provide high-quality digital video and broadband data services. With integrated FEC (Forward Error Correction) capabilities, this core enhances signal quality and reliability, ensuring that subscribers receive superior service. It's optimized for modern cable networks, where efficient data transmission and minimal error rates are paramount. The DVB-C Demodulator plays a vital role in cable systems, ensuring consistent and accurate decoding of broadcast signals. Its compatibility with various cable configurations and modulation standards makes it a versatile and dependable choice for service providers who aim to uphold high standards of cable and digital communication.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The PCE04I Inmarsat Turbo Encoder is engineered to optimize data encoding standards within satellite communications. Leveraging advanced state management, it enhances data throughput by utilizing a 16-state encoding architecture. This sophisticated development enables efficient signal processing, pivotal for high-stakes communication workflows. Furthermore, the PCE04I is adaptable across multiple frameworks, catering to diverse industry requirements. Innovation is at the forefront with the option of integrating additional state Viterbi decoders, tailoring performance to specific needs and bolstering reliability in communications.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
The TCP/IP Offload Engine from Chevin Technology represents a major advancement in network performance for FPGAs. Capable of supporting up to 100 Gbps, this IP core offloads TCP processing from the CPU to the FPGA, freeing up valuable processing resources and enhancing overall device efficiency. This shift means significantly faster data throughput and reduced latency for high-speed, high-demand networking applications. Designed as an all-RTL solution, this engine ensures robust, reliable transmission over networks using advanced methods for checksum calculations and congestion management. The TCP/IP Offload Engine integrates seamlessly with existing FPGA projects and is configurable to adapt to different data traffic conditions, optimizing performance according to specific project requirements. Industries such as telecommunications, data centers, and broadcasting, which demand high data bandwidth and performance, will find this engine invaluable. Furthermore, Chevin Technology offers flexible licensing and ample support to facilitate easy incorporation into diverse FPGA architectures.
The Turbo Encoder and Decoder cores by Creonic are engineered to deliver high efficiency in error correction, catering to standards like DVB-RCS2 and 4G LTE. These cores are vital in systems where low latency and high throughput are crucial, such as mobile communications and satellite transponders. Turbo coding technology is renowned for its capacity to approach the Shannon limit, offering near-optimal performance. Creonic's Turbo solutions are meticulously designed to support a wide gamut of applications from space communications to terrestrial wireless networks. Their enhanced algorithms allow for simplified integration and operational efficiency, drastically reducing the error rate in data transmission. The cores are particularly beneficial in environments that encounter significant noise and interference. By using these Turbo Cores, businesses can optimize their communication systems, thereby minimizing the engineering challenges related to complex transmission environments. These products are a testament to Creonic’s expertise in providing robust, versatile solutions that can be tailored to meet very specific customer needs.
The 5G Polar encoding and decoding solutions provided by TurboConcept deliver state-of-the-art error correction for 5G networks. These solutions are crafted to efficiently handle polar code challenges, ensuring high data throughput with minimal latency. Designed for both FPGA and ASIC implementations, the cores enhance the performance of 5G systems by providing robust error correction, essential for reliable communication in varying conditions. TurboConcept's 5G Polar solutions are instrumental in facilitating the sophisticated demands of modern communication networks, supporting a wide range of applications from mobile data to critical IoT infrastructures.
MEMTECH's D-Series DDR5/4/3 Controller is crafted to optimize the performance of memory systems by enhancing their data handling capabilities. Intended for use in various technological domains such as data centers and consumer electronics, this controller maximizes throughput with its architecture tailored for latency reduction and optimal bandwidth usage. The controller supports standard DFI interfaces, ensuring compatibility and functionality across a wide range of applications. Equipped with over 300 customizable features, it allows businesses to tailor the controller according to specific needs, enhancing versatility and adaptability. Its advanced command schedulers and enhanced error correction mechanisms fortify data integrity, crucial for environments demanding high operational accuracy. The D-Series controller represents MEMTECH's commitment to engineering solutions that breach boundaries of conventional performance, offering expansive support for both modern and legacy systems. By integrating robust data management features, this controller is a perfect fit for applications needing extensive data processing capabilities with minimized power consumption.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The Interlaken PHY Solution by StreamDSP serves as a high-performance interface solution designed for high-speed data systems. It employs the Interlaken protocol, which is specialized in managing chip-to-chip communications at high data rates while ensuring minimal overhead. The solution is optimized to provide a balance between performance and resource utilization, supporting a wide range of operating environments and requirements. Its versatility makes it ideal for networking, data center, and high-performance computing applications, where reliable and rapid data transmission is crucial.
The Convolutional Encoder and Viterbi Decoder IP is a versatile digital signal processing module that offers error correction capabilities essential for maintaining data integrity in communication channels. It employs convolutional encoding coupled with Viterbi decoding, aiming to correct errors that occur during data transmission over noisy channels. This IP core is adaptable, able to work with any polynomial used for encoding, ensuring that it can be tailored specifically to the user's diverse application demands. It finds extensive use in environments where reliability and accuracy of data transmission are of paramount importance, such as in telecommunications and networking sectors. By providing robust error detection and correction functionalities, it helps mitigate the adverse effects of channel noise, thereby bolstering the efficiency of data communications. This enhances user experience by supporting uninterrupted communication with fewer errors. Designed with flexibility in mind, this module supports various standards and can be deployed across multiple platforms. Its architecture is optimized for resource utilization, adapting to the specific needs of different technological environments without unnecessary complexity or cost. This adaptability ensures that the IP core can seamlessly integrate into existing systems, providing a substantial technological advantage in competitive markets.
The TCP/IP Offload Engine by Design Gateway is a hardware-based solution designed to offload TCP/IP processing tasks from CPUs, optimizing network performance and providing greater processing efficiencies. This core implements a full TCP/IP stack in hardware, reducing the processing burden on central CPUs, thus enabling higher data throughput with minimal latency. Its applicability spans across data-intensive environments such as network routers, switches, and high-frequency trading platforms where reduced CPU load leads directly to performance enhancements. The core's design allows for minimal setup and integration effort, matching well with FPGA-based network systems needing robust, low-latency connectivity.
This suite offers flexible and powerful error correction capabilities through LDPC and Turbo coding. Aimed at enhancing communication systems, the cores are designed for seamless integration with broadband and broadcast environments. They are particularly beneficial in applications requiring high data integrity and error correction, such as satellite and terrestrial communications. The TurboConcept designs support various architectures, catering to the unique demands of both high-capacity networks and specialized communication systems. These cores are built to ensure efficient and effective data error management, enabling optimal performance in various digital transmissions.
Specially designed for 1KB correction blocks, the G14/G14X series caters to NAND devices with 8KB page sizes. Its versatility allows support for both 512B and 1024B blocks, accommodating SLC and MLC flash requirements effectively. It enhances controller performance with provisions for extended wear leveling and robust error correction across various generations of flash technology. The series also offers customization possibilities to meet diverse latency, bandwidth, or spatial demands.
With the increasing speed of serial links, the need for efficient forward error correction (FEC) has become paramount to maintain data integrity over lossy mediums. CoMira's Error Correction technology addresses this by implementing various FEC algorithms that optimize data recovery functionality in high-speed Ethernet applications. Drawing from standards such as the 802.3 Ethernet, CoMira's FEC solutions incorporate both FireCode and Reed Solomon methods. These are pivotal for applications such as 100GBASE-KR4 and 50GBASE-R2, providing substantial gains in error correction performance. The IP architecture ensures seamless integration with CoMira's UMAC, enhancing overall system efficiency. Significantly, CoMira's FEC cores can be deployed standalone, or as part of the UMAC configuration, which adds to their flexibility. By allowing error correction processes to be bypassed when necessary, these cores reduce latency, further optimizing their operation for use in Ethernet and beyond.
TurboConcept's 4G multi-mode CTC decoder is engineered for modern broadband wireless communications, ensuring efficient and error-free data exchange. Designed to handle the complexity of decoding convolutional turbo codes, this core offers flexibility and high performance across various 4G applications. It seamlessly integrates with existing systems to enhance data transmission quality, effectively managing multiple modes to cater to diverse network requirements. By providing robust error correction, this decoder enhances network reliability and supports high-speed data operations, making it essential for competitive 4G LTE platforms.
The G12 module is engineered for 256B correction blocks and provides support for error corrections up to 16 bits. This unique capability is valuable for specialized applications where smaller block sizes are crucial. The design features optimized ECC dynamics, allowing for an adaptable block size range from 2 to 450 bytes. It is further customizable to maximize area efficiency by tailoring the maximum ECC level with set parameters. Additionally, it supports various configuration modes, catering to both single and multi-channel setups.
Creonic offers a comprehensive range of LDPC Encoder and Decoder cores, expertly engineered for high-speed data throughput. These cores cater to numerous standards such as DVB-S2X and CCSDS, providing flexible, robust solutions for error correction in digital communication systems. They are designed to maximize performance in demanding environments, supporting varied applications from satellite communications to next-generation mobile networks. Key products like the 5G-NR LDPC and DVB-S2X LDPC/BCH cores exemplify sophisticated designs that deliver exceptional data integrity and throughput. Each specific LDPC product aligns with industry-standard protocols, ensuring compatibility and ease of integration into existing infrastructures. The modular design provides adaptability to different use cases, particularly in the rapidly evolving 5G infrastructure landscape. LDPC technology is critical for high-efficiency error correction, and Creonic's offerings are designed to minimize latency while maximizing reliability. These cores play an integral role in maintaining the integrity and performance standards of modern communication systems, ensuring that data is transmitted accurately over various channels.
The 5G NR LDPC Decoder by Mobiveil is a specialized IP core designed to deliver exceptional error correction performance in wireless communication applications. Employing the Min-Sum algorithm, it allows for customizable bit-widths and iteration settings. Its architecture includes early iteration termination based on parity checking, enhancing efficiency. This decoder optimally handles decoding for 5G data, supporting the accumulation of LLRs for HARQ, and thus provides robust performance in high-demand wireless networks.
The Polar Encoder and Decoder solutions from Creonic are at the forefront of communication technology, aiming to optimize data transmission reliability. Adhering to numerous standards, these Polar Codes are especially effective in environments with fluctuating signal integrity, commonly seen in mobile networks and data communications. Designed with modern algorithms, Creonic’s Polar solutions offer superior performance by utilizing a method of encoding data that facilitates easier error detection and correction. This approach ensures reduced processing times and lower error rates, making it highly suitable for next-generation wireless communication systems. These Polar Cores are ideal for businesses aiming to enhance data handling and improve error resiliency, offering a versatile, adaptive solution suitable for high-performance contexts. The cores streamline the flow of information, ensuring that communication lines remain clear and efficient even under significant load conditions and disturbances.
Designed to meet the demands of next-generation wireless networks, the 5G LDPC core is a high-performance forward error correction solution for both FPGA and ASIC applications. It facilitates robust data transmission by providing efficient error correction capabilities, crucial for reliable communications in the rapidly evolving 5G ecosystem. This solution is particularly suited for high-speed data applications where low latency and high-throughput performance are paramount. The core can be easily integrated into existing systems, supporting seamless upgrades and enhancing overall network efficiency.
Swissbit introduces the D2200, a high-performance PCIe SSD crafted specifically for data centers and enterprise environments where robust data storage and rapid access are critical. It offers enhanced performance through its PCIe interface, supporting high sustained throughput and read/write speeds, ensuring optimal data handling capabilities. This SSD is ideal for systems demanding consistent performance and reliability even under intense workloads, making it suitable for critical applications and services in demanding data environments. Its architecture is built to reduce latency and enhance data center efficiency, ultimately contributing to a lower total cost of ownership for ITS clients.
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