All IPs > Wireline Communication > Error Correction/Detection
In the realm of wireline communication, ensuring the integrity and reliability of data transmission is a critical concern. This is where Error Correction and Detection semiconductor IPs play a pivotal role. These IPs are designed to identify and rectify errors that occur during data transmission, thus enhancing the overall performance and reliability of wireline communication systems. Whether it involves correcting single-bit errors or detecting complex data discrepancies, these IPs are essential for maintaining the fidelity of data transmission.
Error Correction and Detection IPs utilize various sophisticated algorithms and techniques such as Reed-Solomon, Hamming Code, and Cyclic Redundancy Check (CRC). These technologies work by adding redundancy to the data being transmitted, allowing the receiver to detect errors and, in many cases, automatically correct them. This process not only protects data integrity but also ensures higher quality of service, reducing the need for retransmissions and improving network efficiency.
These semiconductor IP blocks are implemented in a wide array of applications including broadband networks, data centers, and telecommunication systems where uninterrupted and accurate data transmission is paramount. For engineers and developers, leveraging these IPs can significantly accelerate the development process of wireline systems by providing ready-to-integrate solutions that uphold communication standards.
In this category, you will find a vast selection of Error Correction and Detection semiconductor IPs suited for various applications. These IPs are available from leading suppliers, offering solutions that support multiple protocols and data rates. With these IPs, developers can ensure their wireline communication products are robust, reliable, and capable of delivering the highest levels of performance needed in today's data-driven world.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
Designed to cater to high-performance networking needs, this offload engine integrates multiple functionalities including TCP offloading, MAC, PCIe, and host interface in one low-latency package. It enables a complete bypass of the host CPU processing, drastically reducing the load and enhancing data throughput. The solution boasts an ultra-low latency of 77 ns, ensuring robust performance suited for critical applications that demand high-speed data processing. The architecture of this offload engine supports a vast number of concurrent TCP and UDP sessions, offering a consistent latency and impressive data transfer rate per session. By offloading network processing tasks, this solution frees up CPU resources, thus achieving efficient operation and lower power consumption. It is particularly advantageous for deployment in data-intensive environments such as cloud computing infrastructures and modern data centers. Equipped with dual-10G ports and advanced features like enterprise-class reliability and scalability, it has been widely adopted for its capability to execute networking tasks efficiently while consuming minimal resources. This engine integrates architecture that is designed to be immune to network jitter, providing a seamless networking experience across multiple ports.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
TT-Ascalon™ is a versatile RISC-V CPU core developed by Tenstorrent, emphasizing the utility of open standards to meet a diverse array of computing needs. Built to be highly configurable, TT-Ascalon™ allows for the inclusion of 2 to 8 cores per cluster complemented by a customizable L2 cache. This architecture caters to clients seeking a tailored processing solution without the limitations tied to proprietary systems. With support for CHI.E and AXI5-LITE interfaces, TT-Ascalon™ ensures robust connectivity while maintaining system integrity and performance density. Its security capabilities are premised on equivalent RISC-V primitives, ensuring a reliable and trusted environment for operations involving sensitive data. Tenstorrent’s engineering prowess, evident in TT-Ascalon™, has been shaped by experienced personnel from renowned tech giants. This IP is meant to align with various performance targets, suited for complex computational tasks that demand flexibility and efficiency in design.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The Ncore Cache Coherent Interconnect from Arteris is engineered to overcome challenges associated with multicore SoC designs. It delivers high-bandwidth, low-latency interconnect fabric enhancing communication efficiency across various SoC components and multiple dies. Designed to ensure reliable performance and scalability, this coherent NoC addresses complex tasks by implementing heterogeneous coherency, and it is scalable from small embedded systems to extensive multi-die designs. Ncore promotes effective cache management, providing full coherency for processors and I/O coherency for accelerators. It supports various coherency protocols including CHI-E and ACE, and comes with ISO 26262 certification, meeting stringent safety standards in automotive environments. The inherent AMBA support allows seamless integration with existing and new SoC infrastructures, enhancing data handling efficiency. By offering automated generation of diagnostic analysis and fault modes, Ncore aids developers in creating secure systems ready for advanced automotive and AI applications, thereby accelerating their time-to-market. Its configurability and extensive protocol support position it as a trusted choice for industries requiring flexible and robust system integration solutions.
AccelerComm offers an innovative LDPC solution specifically for 5G NR systems, pushing the boundaries of performance with its advanced block-parallel and row-parallel architectures. This sophisticated solution enhances data channel performance by utilizing a combination of scalability, high throughput, and low latency to maintain optimal communication systems. The LDPC solution effectively addresses standard 5G data channels, achieving substantive gains in resource utilization efficiency. By improving the already stringent latency specifications to support numerology 4, the solution ensures comprehensive code and transport block processing capabilities. It also upholds IEEE standards, providing a compliant pathway for high reliability and operational efficiency. Designed for integration across multiple platforms, including ASIC, FPGA, and software form factors, LDPC’s flexibility allows for deployment in a range of network conditions. Its open standard software interfaces make it easily adaptable, presenting a robust and versatile framework for companies to enhance their 5G network communication protocols with minimal effort.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The High Speed Data Bus (HSDB) IP Core by New Wave Design provides a comprehensive physical (PHY) and MAC layer hardware implementation. It is engineered to deliver full-rate data throughput, facilitating seamless integration into network infrastructures. With a particular focus on compatibility, it features a design that aligns with F-22 interface standards, ensuring smooth application within related military avionics systems. This core is central to maintaining robust and high-speed data transmission in demanding environments.
Polar coding, a relatively recent addition to the 5G NR suite of technologies, is embraced by AccelerComm through their unique design that facilitates higher degrees of parallel processing. This advancement ensures operational efficiency and minimizes resource usage, thereby improving system robustness and throughput in 5G NR control channels. By employing a patented architecture, Polar coding exhibits flexibility and scalability, key to supporting high-performance 5G requirements. The reduced burden on hardware resources enables it to deliver superior BLER performance, crucial for meeting the stringent demands of modern telecommunications standards. Delivering across a spectrum of platforms, whether hardware-based like ASIC and FPGA or software-driven, Polar coding maintains a high degree of integration ease. This allows rapid deployment and alignment with existing infrastructure, ensuring seamless communication and data integrity in a wide array of network scenarios.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
QUIC Protocol Core is engineered to handle high-speed data transmission efficiently, making it suitable for environments prone to network congestion and packet loss. By eschewing traditional TCP/IP methods, this core delivers up to 400 times the performance improvement, ensuring data transfers are both secure and swift. The core is particularly adept in FPGA environments, offering low memory footprint and high data processing capabilities. It provides the essential high-level security via integrated TLS 1.3, supporting robust encryption throughout its operation.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Secure Protocol Engines are high-performance IP blocks that focus on enhancing network and security processing capabilities in data centers. Designed to support secure communications, these engines provide fast SSL/TLS handshakes, MACsec and IPsec processing, ensuring secure data transmission across networks. They are particularly useful for offloading intensive tasks from central processing units, thereby improving overall system performance and efficiency. These engines cater to data centers and enterprises that demand high throughput and robust security measures.
The TCP/IP Offload Engine offered by Chevin Technology significantly enhances FPGA efficiency by managing TCP/IP protocol processing, freeing the main processor for other tasks. Available in both 10G and 25G versions, this offload engine is an ideal choice for applications requiring high-speed and reliable network interactions. The engine's robust design supports high-density installations while maintaining significant computational capacity, allowing integrators to optimize their hardware for specific needs. It's particularly beneficial for data-intensive sectors such as cloud computing, financial services, and real-time analytics, providing the necessary backbone for high-volume data management. With a focus on reducing latency and increasing data throughput, the Chevin Technology TCP/IP Offload Engine integrates seamlessly into existing systems. Its capability to handle offloaded tasks independently of the main CPU contributes substantially to lowering power consumption and enhancing system stability, making it a preferred solution for energy-conscious enterprises.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
The Complete 5G NR Physical Layer solution by AccelerComm is designed to provide exceptional performance for demanding applications in O-RAN and satellite networks. This all-encompassing solution integrates high-accuracy signal processing technology, ensuring optimal link performance and efficient power usage. The physical layer is inherently flexible, allowing performance optimizations tailored to meet specific requirements of specialized network applications. This solution navigates the complex real-world dynamics involved in high-performance network scenarios, including both terrestrial and space-based communications. By leveraging advanced algorithms and architectures, the 5G physical layer supports customizable configurations, leading to power and area efficiency improvements. Through interoperability with multiple hardware platforms, it maximizes the performance of 5G networks, enhancing the user experience by minimizing latency and maximizing throughput. Delivered as openly-licensable intellectual property, the 5G NR Physical Layer can function across a wide range of platforms, such as ARM software and FPGA, ensuring broad compatibility. This strategic approach facilitates quicker project advancements through seamless integration and testing processes on multiple development boards, thereby reducing project risks effectively.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
The 8b/10b Decoder from Roa Logic is an intricate implementation of the 8b10b encoding/decoding standard developed by Widmer and Franaszek. This decoder is equipped with features like automatic comma detection and the capability to recognize K28.5 code groups, making it a robust choice for error-checking applications where data integrity is of paramount importance.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
The UDP/IP Ethernet Communication core is expertly crafted to facilitate seamless networking capabilities in FPGA-based subsystems through the use of the User Datagram Protocol (UDP). It provides an efficient mechanism for enabling communication over Ethernet, catering to applications that require rapid and reliable data exchange but do not have stringent requirements for guaranteed delivery. This core is an excellent choice for scenarios that prioritize speed and low latency, such as real-time data streaming and sensor networks. Leveraging the simplicity of UDP, it minimizes the overhead associated with more robust protocols like TCP, thereby ensuring efficient transmission of data packets across networks. The core's compatibility with various Ethernet standards ensures its suitability for a wide range of networking environments. The UDP/IP Ethernet Communication core offers flexibility in configuration, allowing designers to tailor its operation to the unique requirements of their systems. It supports integration into existing FPGA designs without necessitating extensive system modifications, thus offering a quick path to enhanced network connectivity. Overall, it is a powerful tool for implementing fast and efficient Ethernet communications within FPGA-based solutions.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
Designed for high reliability and efficiency, the BCH Error Correcting Code ECC from Secantec, Inc. ensures robust protection against errors in data communication systems. This IP utilizes the BCH algorithm, renowned for its capability to correct multiple errors within data sequences, making it an essential component in environments prone to error injection. The BCH code is ideally suited for systems that need to support high-speed data transfer with stringent reliability requirements. It offers a flexible architecture that can be implemented in diverse environments, whether in digital communication systems or error-tolerant storage systems. By adapting to varying levels of error and noise, the BCH code provides a consistent performance benchmark in safeguarding data integrity. This IP's versatility allows it to be incorporated into both hardware and software solutions, addressing a broad array of use cases from wireless communications to robust error correction in static memories. Its scalable design ensures that it can be tailored to fit specific application needs, delivering unmatched performance under various operational conditions.
The Stream Buffer Controller is engineered to serve as a versatile bridge between streaming data and memory-mapped DMA operations. Its design focuses on enabling efficient data handling and transfer in high-performance computing environments where data throughput, latency, and reliability are critical to the system's success. By offering a direct pathway for data transactions, it minimizes bottlenecks and optimizes the overall data flow. This controller is particularly suited for applications involving high-speed data processing and transmission, where managing data efficiency is a top priority. It supports a broad set of data protocols and standards, ensuring that integration with diverse systems is straightforward and trouble-free. Compatibility with memory-mapped architectures allows for flexible system design and enhances interoperability. The Stream Buffer Controller's architecture is designed to be easily configurable, allowing developers to adjust parameters in response to specific project demands. This adaptability ensures that systems utilizing the controller can achieve optimal performance, even as requirements evolve. Overall, it provides an effective solution for managing data-intensive applications with minimal overhead, facilitating smoother and more efficient operations.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The DVB-C Demodulator is engineered to meet the specific needs of cable video and broadband data transmission systems with an integrated Forward Error Correction (FEC) capability. This core is structured to enhance demodulation processes, streamlining communications and ensuring data reliability across transmission channels. Suitable for a variety of digital broadcasting requirements, it serves as a critical component in maintaining signal integrity and performance.
Secantec's Reed Solomon Error Correcting Code ECC is engineered to deliver high reliability in data transmission environments, correcting both burst and random errors. This IP is recognized for its effectiveness in environments where high-speed data transfer aligns with strict error performance standards. Designed to enhance data integrity in systems subjected to noise and signal distortion, this code is adaptable to various application requirements, ensuring minimal error rates in data transmissions. The Reed Solomon code is crucial for scenarios such as optical communications, satellite systems, and broadcasts, where error minimization is essential. Its implementation offers the flexibility to handle different data block sizes and error correction capacities, making it suitable for customization according to specific needs. This adaptability allows it to seamlessly integrate into systems requiring consistent data accuracy and reliability, marking it as a staple in dependable communication solutions.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The PCE04I Inmarsat Turbo Encoder is engineered to optimize data encoding standards within satellite communications. Leveraging advanced state management, it enhances data throughput by utilizing a 16-state encoding architecture. This sophisticated development enables efficient signal processing, pivotal for high-stakes communication workflows. Furthermore, the PCE04I is adaptable across multiple frameworks, catering to diverse industry requirements. Innovation is at the forefront with the option of integrating additional state Viterbi decoders, tailoring performance to specific needs and bolstering reliability in communications.
Hamming Code ECC developed by Secantec, Inc. offers a straightforward yet powerful method for error correction in digital communications. This IP is engineered to correct single-bit errors and detect double-bit errors, making it a critical component in systems where reliability is paramount. This code is particularly useful in environments where small data integrity issues can result in significant operational setbacks. Not only does it provide effective error correction, but it also enhances overall system performance by reducing the need for costly data retransmissions. Its simplicity and ease of implementation make it suitable for a wide range of applications, from computer memory systems to complex networking solutions. Through its efficient error detection and correction capabilities, the Hamming Code ECC ensures data reliability without imposing significant resource demands. Its robust design is ideal for integration into systems that benefit from cost-effective and efficient error rectification techniques, promoting smooth and uninterrupted data flow.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The LDPC Decoder caters to 5G Network Release (NR) standards, providing a reliable decoding process crucial for modern communication systems. Utilizing the Min-Sum decoding algorithm, it offers configurable bit widths and supports early termination through a concurrent parity check engine, enhancing decoding efficiency. In addition, the decoder’s architecture accommodates flexible iteration settings, optimal for applications reliant on re-transmission protocols such as HARQ. Embedded in its design is a focus on reducing power usage and maximizing throughput, suitable for various network scenarios and demanding 5G applications.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The UDP Offload Engine IP core from Atomic Rules is designed to boost application throughput across multiple 10/25/40/50/100/400 GbE Ethernet interfaces. It offloads UDP processing tasks from software to hardware, providing efficient data handling at remarkable speeds while ensuring compliance with the UDP/IPv4 standards. This engine implements checksum, segmentation, and reassembly functionalities in hardware, allowing developers to streamline operations without manually manipulating datagrams. It supports super-jumbo frames up to 16K bytes, enhancing data transfer rates significantly for demanding network applications. Designed to work seamlessly with the Internet Protocol suite, the UDP Offload Engine makes it possible to achieve exceptional data transfer rates and reduce the overhead associated with data handling in FPGA architectures. This optimization helps applications meet modern requirements for high-bandwidth communication without interrupting existing workflows.
The Reed Solomon Erasure Code offered by Secantec, Inc. is tailored for applications that require high reliability in data transmission where the location of erasure is clear, but the original values are not. This code allows the recovery of original data after computation on the received code words, leveraging redundant symbols that accompany the data. It has notable utility in systems like RAID, where it mitigates the risk of data loss from disk drive failures, and in communications where precise error location is advantageous. This IP finds its strength in rectifying errors introduced during transmission, aiding systems that suffer from frequent noise disturbances, thus ensuring stability and reducing downtime. The Reed Solomon Erasure Code works efficiently in environments with known erasure locations, combining error correction with storage recovery features to maintain the integrity of data being transmitted. The flexibility and efficiency of this code make it ideal for environments where some of the data might be incorrect, such as in communication systems dealing with high-speed data streams or storage devices. Through precise error correction capabilities, it supports durability and consistency in data handling, pushing the boundaries of secure communications.
XtremeSilica's 100G UDP Offload Engine is engineered to manage UDP data packet processing with exceptional speed and efficiency. This technical solution is vital for applications requiring real-time data streaming, such as financial services and live media broadcasts. The engine supports network configurations that demand robust data handling capabilities and minimal latency.\n\nBy offloading UDP tasks from the central processor, this engine frees up critical CPU resources, allowing for smoother and faster network operations. Its high-speed capabilities ensure it can keep up with the demands of modern data-centric industries, providing reliable performance across a wide range of use cases.\n\nXtremeSilica's UDP Offload Engine is adaptable to various network settings, ensuring seamless integration with existing infrastructure. By enhancing data streaming efficiency, this offload engine is a critical innovation for industries looking to maximize throughput without sacrificing system performance.
The FCM2801-BD is a 28GHz CMOS Power Amplifier, specifically designed for applications in the 5G mmWave spectrum. It operates across a frequency range of 23 to 36 GHz and delivers a gain of 22 dB with a Psat of 19.55 dBm. Boasting a PAE of 53%, this amplifier suits high-frequency telecommunications, offering improved range and reduced energy consumption. The design minimizes thermal output, which further aids in reducing system maintenance costs.
The Interlaken PHY Solution by StreamDSP serves as a high-performance interface solution designed for high-speed data systems. It employs the Interlaken protocol, which is specialized in managing chip-to-chip communications at high data rates while ensuring minimal overhead. The solution is optimized to provide a balance between performance and resource utilization, supporting a wide range of operating environments and requirements. Its versatility makes it ideal for networking, data center, and high-performance computing applications, where reliable and rapid data transmission is crucial.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The 12G-SDI Playback and Capture solution by Korusys offers high-definition video handling capabilities through versatile FPGA images. Designed for seamless integration with PCIe interfaces and companion Linux-based software, it facilitates video capture and playback via Quad 3G-SDI. This system can generate test patterns and engage in user-friendly data transfer, optimized for extensive video processing needs. The solution is engineered to support high throughput and low latency requirements, making it suitable for demanding video applications that require efficient signal transmission and handling. Its flexible framework supports user-defined configurations, allowing it to be tailored for specific project requirements.
Specially designed for 1KB correction blocks, the G14/G14X series caters to NAND devices with 8KB page sizes. Its versatility allows support for both 512B and 1024B blocks, accommodating SLC and MLC flash requirements effectively. It enhances controller performance with provisions for extended wear leveling and robust error correction across various generations of flash technology. The series also offers customization possibilities to meet diverse latency, bandwidth, or spatial demands.
The G12 module is engineered for 256B correction blocks and provides support for error corrections up to 16 bits. This unique capability is valuable for specialized applications where smaller block sizes are crucial. The design features optimized ECC dynamics, allowing for an adaptable block size range from 2 to 450 bytes. It is further customizable to maximize area efficiency by tailoring the maximum ECC level with set parameters. Additionally, it supports various configuration modes, catering to both single and multi-channel setups.
With the increasing speed of serial links, the need for efficient forward error correction (FEC) has become paramount to maintain data integrity over lossy mediums. CoMira's Error Correction technology addresses this by implementing various FEC algorithms that optimize data recovery functionality in high-speed Ethernet applications. Drawing from standards such as the 802.3 Ethernet, CoMira's FEC solutions incorporate both FireCode and Reed Solomon methods. These are pivotal for applications such as 100GBASE-KR4 and 50GBASE-R2, providing substantial gains in error correction performance. The IP architecture ensures seamless integration with CoMira's UMAC, enhancing overall system efficiency. Significantly, CoMira's FEC cores can be deployed standalone, or as part of the UMAC configuration, which adds to their flexibility. By allowing error correction processes to be bypassed when necessary, these cores reduce latency, further optimizing their operation for use in Ethernet and beyond.
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