All IPs > Wireline Communication > ATM / Utopia
ATM (Asynchronous Transfer Mode) and Utopia (Universal Test & Operations Physical Interface for ATM) are vital technologies associated with wireline communication. These protocols and interfaces ensure a robust and efficient transfer of digital data across networks. The ATM / Utopia semiconductor IP category comprises designs developed to implement these protocols on silicon, enhancing performance and integrating seamlessly within various communication systems.
ATM technology is lauded for its ability to deliver a range of different types of traffic—such as voice, video, and data—on the same network, each with its unique quality of service (QoS) requirements. The ATM semiconductor IPs cater to these needs by providing solutions that support high throughput and low latency. These IP blocks are crucial in environments where data integrity and transmission speed are paramount, such as in telecommunications and enterprise networking systems.
Utopia, on the other hand, serves as the interface standard for linking an ATM layer device to the underlying physical layer. Utopia semiconductor IPs are designed to ensure compatibility and seamless interaction between these layers, thereby optimizing the data transfer process. These IPs allow manufacturers to develop hardware that meets specific standards with minimal compatibility issues, leading to faster market deployment.
In this category, you will find a range of semiconductor IPs that can be integrated into a variety of products, including network routers, switches, and telecommunications equipment. The ATM/ Utopia IP offerings in Silicon Hub are crafted to meet the exacting needs of modern communication networks, ensuring reliability, efficiency, and high performance in every application.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
The High Speed Data Bus (HSDB) IP Core by New Wave Design provides a comprehensive physical (PHY) and MAC layer hardware implementation. It is engineered to deliver full-rate data throughput, facilitating seamless integration into network infrastructures. With a particular focus on compatibility, it features a design that aligns with F-22 interface standards, ensuring smooth application within related military avionics systems. This core is central to maintaining robust and high-speed data transmission in demanding environments.
The SMPTE ST 2110 core from Nextera facilitates the transmission and reception of professional media over IP networks. It supports various sub-standards, including the management of uncompressed video, audio, and associated data streams. This IP core is invaluable for broadcast and professional environments aiming to leverage IP standards for seamless media transportation and processing, ensuring high-quality outputs with flexibility in resource allocation and network adaptability.
The TSN Switch for Automotive Ethernet is designed to facilitate real-time data transmission across automotive networks. It supports the latest standards for time-sensitive networking, ensuring minimal latency and maximum data throughput. The switch integrates seamlessly into existing automotive infrastructure, providing reliable and efficient connectivity solutions for modern vehicles. Enhancing the communication framework, this switch is optimized for vehicular environments, accommodating complex data streams and ensuring robustness even in harsh conditions. Its design is meticulously detailed to support advanced automotive protocols, providing a stable platform for future automotive innovations. The switch enables safe and synchronized data exchange, vital for the growing demands of connected vehicles. With a focus on cost-efficiency and deployment flexibility, it is an essential component for building the next generation of intelligent transportation systems.
Under its eSi-Comms brand, EnSilica delivers a suite of highly parameterized communications IP solutions that play a crucial role in supporting modern communication standards such as 4G, 5G, Wi-Fi, and DVB. These IP blocks are designed to streamline the development of ASIC designs by providing a robust platform for OFDM-based modem solutions. The IP suite features advanced DSP algorithms for synchronization, equalization, demodulation, and channel decoding, ensuring robust communication links. It's optimized for integration into systems requiring flexibility and high performance.
On the transmitter side, the turbo -phi encoder architecture is based on a parallel concatenation of two double -binary Recursive Systematic Convolutional (RSC) encoders, fed by blocks of K bits (N=K/2). It is a 16-state double-binary turbo encoder. On the receiver side, the turbo decoder engine is built using two functioning soft-in/soft-out modules (SISO). The outputs of one SISO, after applying the scaling and interleaving are used by its dual SISO in the next half iteration. Both the turbo encoder and decoder are fully compliant with the DVB-RCS2, supporting all its code rates and block sizes. In order to achieve higher throughput, the turbo decoder uses parallel MAP decoders. The sliding window algorithm is used to reduce the internal memory sizes. Turbo decoder accepts input LLR’s and outputs the hard decision bits after completing the decoder iterations.
QUIC Protocol Core is engineered to handle high-speed data transmission efficiently, making it suitable for environments prone to network congestion and packet loss. By eschewing traditional TCP/IP methods, this core delivers up to 400 times the performance improvement, ensuring data transfers are both secure and swift. The core is particularly adept in FPGA environments, offering low memory footprint and high data processing capabilities. It provides the essential high-level security via integrated TLS 1.3, supporting robust encryption throughout its operation.
The Tentiva Video FMC by Parretto is engineered to serve as a high-performance modular Video FMC board, optimized for demanding video processing tasks. Its design enables adaptability through the inclusion of two modular PHY slots, which can accommodate various PHY cards, expanding its functionality and application range. These PHY slots are equipped to handle data rates up to 20 Gbps, providing a robust interface between Tentiva and PHY cards. This configuration makes Tentiva suitable for a vast array of advanced video applications, with support for DisplayPort 2.1 TX/RX PHY cards for seamless high-definition video transmission and reception. Built for compatibility, Tentiva can be integrated with FPGA development boards featuring FMC headers, allowing developers to integrate it effortlessly within diverse development environments. Its modular architecture ensures significant flexibility, permitting easy PHY card upgrades or replacements as required by specific project needs.
The LTE Lite processor offered by Wasiela is a streamlined implementation of the Long-Term Evolution (LTE) standard, specifically configured for user equipment (UE) supporting CAT 0 and CAT 1 PHY layers. This design delivers flexible input bandwidth options, ranging from 1.4 MHz to 20 MHz, accommodating various deployment scenarios. LTE Lite supports a range of modulation schemes including QPSK, 16QAM, and 64QAM, facilitating adaptability to diverse communication environments. Incorporating an automated operation managed by a master finite state machine, the LTE Lite processor integrates seamlessly with RF tuners via an external analog-to-digital converter. This allows for effective handling of frequency offsets and ensures precise timing and frequency correction, capable of compensating offsets up to 500 kHz. The LTE Lite processor offers both parallel and serial output configurations, enhancing its versatility in application integration. Designed as synthesizable Verilog-2001 IP, the LTE Lite is portable across platforms, ensuring a wide range of deployment options. With Matlab simulation models and robust documentation included, the LTE Lite processor provides a powerful toolset for manufacturers aiming to implement LTE technologies efficiently and effectively. Its compact and adaptable design is ideal for meeting the demands of modern mobile communications.
Specialized for telecommunications networks, the SONET/SDH Framer handles the intricate task of framing data streams within high-speed optical networks. This component is designed to support the high reliability and synchronization standards required in modern SONET/SDH infrastructure.
The 100G Transponder CAUI-10 facilitates seamless optical-to-electrical signal conversion, doubling as an efficient intermediary in high-capacity network systems. These transponders are invaluable for telecommunications setups that demand high data rates and extended reach, providing the necessary tools to manage complex digital signal demands.
The SafeIP SinglePHY is a leading-edge solution for the development of Safe Communication Technology, specifically designed with a data rate of 100 MBit/s. Its small footprint and ultra-low power consumption make it ideal for a wide range of applications. This product is equipped with capabilities such as Open Alliance TC10 Sleep/Wake, streaming of debug data, and transmission interruption to ensure safety states. This innovative solution also flags potential safety violations via a safety interrupt and supports CRC calculation. Furthermore, it establishes an Ethernet physical layer link-up and transmits Ethernet data efficiently between MII and MDI interfaces. The SafeIP SinglePHY can diagnose cable faults and offers a Logic Built-In Self Test (LBIST) for assurance, with EMC compliance according to Open Alliance standards. The architecture supports Automotive Grade 1 and is built on 22FDX technology. The product is optimized with Media-Independent Interface (MII) and APB interfaces, alongside support for IEEE 1500, reinforcing its reliability. Typical power consumption is a remarkably low 34mW, making it both secure and efficient for industries demanding robust safety measures.
The 100BASE-T1 Ethernet PHY presents a streamlined solution for low-cost, high-speed communications over a single unshielded twisted pair cable. Designed to improve space efficiency without compromising performance, this product supports the sending and receiving of data at 100 Mbps with reduced cabling requirements. Its effective use in Ethernet communication makes it ideal for modern networking infrastructure where reducing space and cost is essential. This Ethernet PHY capitalizes on a lightweight architecture which ensures high data throughputs while maintaining low energy consumption. This balance makes it suitable not only for automotive applications but also for any industry where compact, efficient communication systems are crucial. By embracing the latest in Ethernet technology, this PHY ensures robust connectivity with minimized latency, translating to better performance in real-world applications. Engineered for easy integration and broad adaptability, the 100BASE-T1 Ethernet PHY supports seamless deployment across various systems. Its compatibility with existing and future tech trends guarantees its role in forward-looking communication networks, assuring users of continued reliability and performance in a dynamically changing tech landscape.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
The VITA 17.1 Serial FPDP Solution from StreamDSP is designed for high-speed data transfer applications. This solution leverages industry-standard interfaces to facilitate efficient serial data communications, ensuring seamless data flow in demanding environments. It's ideal for applications that require robust data integrity and low-latency transmission, making it a perfect fit for military and aerospace operations. By supporting a range of configurations and offering flexibility in integration, this solution helps address specific user needs while maintaining compatibility with widely used FPGA devices.
StreamDSP's VITA 17.3 Serial FPDP Gen3 Solution is an advanced high-speed communication framework designed to meet the latest standards in data transfer technology. This solution offers improved data throughput and enhanced interoperability with existing systems, making it an invaluable asset for applications demanding the utmost precision and speed. Leveraging enhanced protocol designs, this IP solution integrates seamlessly with a broad array of FPGA platforms, providing users with unmatched performance and reliability in critical data communication setups. This makes it indispensable for applications in fields such as defense, scientific research, and real-time data processing.
The NB-IoT (LTE Cat NB1) Transceiver is a versatile module built to adhere to the 3GPP Release 13 standard, with additional capability for Release 14 compliance. Its design offers high performance for both transmitter and receiver functions, meeting stringent 3GPP specifications with margin for enhanced reliability.\n\nOperating predominantly within cellular bands, the transceiver utilizes a low-power profile to ensure efficiency, offering analog interfaces for straightforward integration and testing. Its programmability via an SPI interface makes it suitable for a wide range of applications and testing environments.\n\nEngineered to interface effortlessly with baseband and MAC layers, this transceiver is an optimal solution for IoT implementations where long battery life and reliable connection quality are paramount. The NB-IoT module provides the necessary signal control for correcting DC offsets, ensuring consistent performance and facilitating integration across various IoT applications.
The SafeIP DualPHY is designed to cater to both 100 and 1000 MBit/s bandwidth requirements, dynamically engaging with these modes through autonegotiation with partner devices. Known as a customer favorite, this product assures safety in communication technologies implemented in automotive applications, equipped with advanced EMC compliance. The DualPHY operates on a typical power consumption of 250mW with a macro size of 1.800mm by 0.850mm, suited for demanding environments requiring robust and efficient operation. It implements functionalities such as Open Alliance TC10 Sleep/Wake, and advanced diagnostic features to detect cable defects. Offering compliance with Automotive Grade 1 DRC, this IP ensures the delivery of two media-dependent interfaces tailored with distinct capabilities while maintaining a single media-independent interface for effective communication. Through its stability in safety-critical environments, the DualPHY reinforces Siliconally’s commitment to pushing the safety envelope in communication solutions.
Capable of handling data rates from 1 to 112Gbps, the ePHY-11207 is a powerful solution designed for 7nm node technologies. It is specifically tailored for environments requiring ultra-low latency and robust error correction capabilities, making it a perfect fit for high-performance data center and 5G network applications. The ePHY-11207 integrates an advanced DSP-based receiver that ensures adaptability to various signaling conditions and insertion loss scenarios, therefore boosting operational reliability across complex systems.
Aliathon's 2.5G GFP-F Framer offers a cutting-edge solution for packet framing in next-generation transport networks. It efficiently packages and aligns data for rapid transmission, optimizing bandwidth while minimizing latency, crucial for supporting dynamic communication applications in modern networks.
The LDPC Decoder caters to 5G Network Release (NR) standards, providing a reliable decoding process crucial for modern communication systems. Utilizing the Min-Sum decoding algorithm, it offers configurable bit widths and supports early termination through a concurrent parity check engine, enhancing decoding efficiency. In addition, the decoder’s architecture accommodates flexible iteration settings, optimal for applications reliant on re-transmission protocols such as HARQ. Embedded in its design is a focus on reducing power usage and maximizing throughput, suitable for various network scenarios and demanding 5G applications.
The UDP Offload Engine IP core from Atomic Rules is designed to boost application throughput across multiple 10/25/40/50/100/400 GbE Ethernet interfaces. It offloads UDP processing tasks from software to hardware, providing efficient data handling at remarkable speeds while ensuring compliance with the UDP/IPv4 standards. This engine implements checksum, segmentation, and reassembly functionalities in hardware, allowing developers to streamline operations without manually manipulating datagrams. It supports super-jumbo frames up to 16K bytes, enhancing data transfer rates significantly for demanding network applications. Designed to work seamlessly with the Internet Protocol suite, the UDP Offload Engine makes it possible to achieve exceptional data transfer rates and reduce the overhead associated with data handling in FPGA architectures. This optimization helps applications meet modern requirements for high-bandwidth communication without interrupting existing workflows.
The SMS OC-3/12 Transceiver Core is engineered for SONET/SDH applications, providing comprehensive support for OC-3 and OC-12 data rates. This core is designed with a deep sub-micron single poly CMOS architecture to ensure compliance with ANSI, Bellcore, and ITU-T specifications for jitter tolerance and generation.\n\nFeaturing innovative architecture, this transceiver core integrates high-frequency PLLs with on-chip loop filters, reducing external component requirements and simplifying design processes. Proprietary advanced signal processing techniques enhance signal integrity, mitigating external and PCB noise issues that commonly affect traditional transceiver designs.\n\nThe core is optimized for multiport SOC designs, allowing for easy process migration and adaptability for new application domains. It includes custom configurable serializer-deserializer (SERDES) options, further enhancing its suitability for complex system integrations and high-performance requirements in networking infrastructure.
The Centralized Network Configurator (CNC) developed by Comcores serves as a pivotal component of Time-Sensitive Networking (TSN) infrastructure. Aimed at coordinating TSN-based Ethernet networks, the CNC is designed to manage and optimize traffic flows, synchronizing network behaviors across various devices and network nodes. This synchronization is vital for applications requiring precise timing and reliable data exchange, especially in automotive, industrial, and aerospace environments. The CNC supports advanced TSN standards, ensuring network components work harmoniously by scheduling network resources with minimal delay and maximum efficiency. Through such precise configuration, it enhances the overall resiliency and adaptability of the network, meeting stringent demands for data integrity and timing accuracy.
InnoSilicon's 56G SerDes Solution is engineered for high-speed serialized data transmission, applicable in data communication and storage technologies. This SerDes (serializer/deserializer) supports a variety of interfaces, ensuring versatile compatibility with existing and future protocols, such as PCIe and Ethernet, among others. The 56G SerDes Solution is designed to deliver exceptional data integrity and low latency, enhancing system performance across different platforms. The architecture supports data rates up to 56Gbps, making it a suitable choice for environments requiring robust data processing capabilities. Power efficiency is a core aspect of this solution, achieved through advanced modulation techniques and power-saving features. It enables a reduction in overall system energy consumption while maintaining peak data throughput, which is crucial for high-density data centers and communication systems. The design also incorporates advanced error correction to boost reliability and reduce data loss during transmission, providing a comprehensive high-speed data transfer solution.
For environments requiring advanced data aggregation and multiplexing at large scales, the 100G Muxponder OTL4.10 provides a sophisticated interface solution. This module is integral to high-speed communication networks, offering functionalities that ensure data flows efficiently across multiple channels.
The 100G Regenerator/Repeater OTL4.10 is essential in scenarios where signal integrity over long distances is critical. This technology rejuvenates weakened signals, essential for networks aiming to maintain robust data integrity and high-quality communication links, thereby extending the range and reliability of optical networks.
The ePHY-5607 stands out for its PPA-optimized configuration, offering data rates from 1 to 56Gbps targeting the 7nm technology node. This IP is engineered for data center applications including routers, switches, and AI storage solutions. With an emphasis on superior BER and robust clock data recovery, the ePHY-5607 ensures efficient handling of high-speed data traffic. This product's distinctive feature set includes rapid temperature tracking and multi-reference clock configurations, which provide enhanced adaptability in fluctuating environments.
The 39GHz 1W Power Amplifier is tailored for 5G mmWave applications, boasting significant power efficiency. Fabricated with 0.15um PHEMT technology, this amplifier operates between 38 to 42GHz, delivering 19dB of gain with a third-order intercept point (IP3) of 40dBm. With a power of 31dBm at P-1dB, it's housed in a surface-mount technology (SMT) package, ensuring optimal integration in high-frequency systems.
The 28GHz Pin Diode SP4T Switch is designed to provide high isolation and low insertion loss for RF applications. Operating from 24 to 32GHz, this switch exhibits a loss of 0.8dB while providing isolation greater than 23dB. This switch is engineered using compact design principles suitable for integration into microwave systems requiring multiple signal paths.
The Wireless Baseband IP from Low Power Futures is designed to optimize ultra-low-power consumption while minimizing footprint and code size. It includes a comprehensive configuration of baseband processor hardware IP, link layer, or medium access control layer firmware, built specifically for IoT applications including beacons, smart sensors, connected audio, and more. The IP offers easy integration into systems on a chip (SoC) and has been fully validated on an FPGA platform to ensure standards compliance and ease of use for developers. Built-in security features further enhance its suitability for secure IoT device deployments.
The 100BASE-TX 2ch Ethernet PHY is engineered to deliver dual-channel Ethernet communication efficiently and cost-effectively. This device features a compact design that contributes to significant space-saving on production lines, a key advantage for industrial applications requiring streamlined solutions. Each channel can handle high-speed data transmission, supporting Ethernet communication needs with reliability and precision. With built-in support for dual-channel operations, this PHY is adept at handling complex networking demands in an automated environment. It underpins seamless and concurrent transmission of data across two channels, promoting enhanced connectivity. This dual-channel PHY not only broadens the scope of Ethernet applications but also ensures critical data paths are maintained within industrial controls or network systems. A highlight of the 100BASE-TX 2ch Ethernet PHY is its adaptability to a variety of industrial settings, including plant automation and machinery operation. Its durable design ensures it can withstand rigorous industrial conditions while delivering consistent performance. This PHY is an integral component in modernizing Ethernet frameworks for higher efficiency and productivity in diverse technical environments.
Built to facilitate low-power, short-range communications, Low Power Futures' IEEE 802.15.4 WPAN offering is crafted to include both the physical and MAC layers for compliance with recent amendments of the IEEE standard. The design supports BPSK and OQPSK modulations with optional GFSK modulator, covering sub-gigahertz and 2.4 GHz frequency bands. It's equipped with built-in security features, making it fitting for applications requiring reliable, low-power networking such as home automation, smart metering, and industrial IoT communications.
The SOQPSK-TG LDPC Modulator is specifically designed for aeronautical telemetry systems, offering a robust solution for efficient data transmission. This modulator implements the Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) waveform, which is widely used in telemetry to optimize bandwidth utilization and improve performance under various transmission conditions. The integration of Low-Density Parity-Check (LDPC) coding further enhances the modulator's performance by providing forward error correction. This feature is crucial for maintaining data integrity during transmission, especially in environments where signal quality can be variable or susceptible to interference. Users benefit from a modulator that delivers high data rates and reliable communications, ensuring efficient and secure transmission of telemetry data in aerospace applications. This IP core is available for implementation on various FPGA platforms, providing flexibility for different design requirements and deployment scenarios.
Wasiela's DVB-S2 LDPC Decoder is designed to maximize the efficiency of satellite digital video broadcasting. It employs advanced low-density parity-check (LDPC) codes combined with Bose-Chaudhuri-Hocquenghem (BCH) codes, forming a robust error correction sub-system that approaches the limits of error-free transmission as defined by Shannon's theory. This decoder supports soft decision decoding and utilizes a minimum sum algorithm, which contributes to its ability to manage error correction with precision, even under fluctuating signal conditions. The architecture of the DVB-S2 LDPC Decoder facilitates several key enhancements, such as its irregular parity check matrix and layered decoding process. These features assist in improving the throughput and reliability of data transmission. The decoder is versatile, capable of adapting to varying degrees of error correction requirements by configuring the number of iterations used during the decoding process. This flexibility ensures comprehensive error management, making it suitable for a wide range of satellite communication applications. Compliant with the ETSI EN 302 307-1 standard, this decoder provides a solution that aligns with industry standards, ensuring interoperability and reliability in digital broadcasting systems. With synthesized Verilog available for ASIC implementations, system models in Matlab, and comprehensive test benches, Wasiela’s DVB-S2 LDPC Decoder is equipped to integrate seamlessly into a broad spectrum of applications requiring robust error correction and high data integrity.
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