All IPs > Wireless Communication > Digital Video Broadcast
The Digital Video Broadcast (DVB) semiconductor IP category comprises an array of IP cores specifically tailored to facilitate reliable and efficient video broadcasting over wireless communication networks. As the demand for high-quality video content continues to rise, the need for robust broadcasting solutions that can handle diverse environments and large audiences becomes crucial. Our collection includes IPs that cater to emerging and established digital broadcasting standards, ensuring versatility and compliance with international specifications.
These semiconductor IPs empower developers to integrate advanced video broadcast capabilities into their next-generation wireless communication products, such as set-top boxes, digital televisions, and mobile broadcasting devices. By leveraging state-of-the-art modulation and error correction techniques, our DVB semiconductor IP offerings streamline the delivery of high-definition and standard-definition video content over various frequencies and platforms. This inclusivity is crucial for manufacturers aiming to capture a broad market share across different regions and user bases.
Moreover, our DVB semiconductor IP solutions are designed with scalability and adaptability in mind. They enable easy integration into diverse broadcasting systems, supporting functionalities such as video encoding, multiplexing, and transmission over wireless channels. This adaptability not only shortens the development cycle but also ensures that the products remain future-proof, allowing manufacturers to deliver cutting-edge features to end-users without extensive redesigns.
Whether you are developing a niche video broadcasting application or a mainstream media distribution product, our Digital Video Broadcast semiconductor IPs provide the essential building blocks needed to ensure high performance, reliability, and compatibility. With a focus on innovation and efficiency, these IPs help you meet the stringent requirements of modern wireless broadcast environments, paving the way for the next wave of digital media consumption experiences.
The Akida 2nd Generation represents a leap forward in the realm of AI processing, enhancing upon its predecessor with greater flexibility and improved efficiency. This advanced neural processor core is tailored for modern applications demanding real-time response and ultra-low power consumption, making it ideal for compact and battery-operated devices. Akida 2nd Generation supports various programming configurations, including 8-, 4-, and 1-bit weights and activations, thus providing developers with the versatility to optimize performance versus power consumption to meet specific application needs. Its architecture is fully digital and silicon-proven, ensuring reliable deployment across diverse hardware setups. With features such as programmable activation functions and support for sophisticated neural network models, Akida 2nd Generation enables a broad spectrum of AI tasks. From object detection in cameras to sophisticated audio sensing, this iteration of the Akida processor is built to handle the most demanding edge applications while sustaining BrainChip's hallmark efficiency in processing power per watt.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
LightningBlu is a cutting-edge solution provided by Blu Wireless, designed specifically to serve the high-speed rail industry. This technology offers consistent, on-the-move multi-gigabit connectivity between trackside and train, which ensures a reliable provision of on-board services. These services include seamless internet access, enhanced entertainment options, and real-time information, creating a superior passenger experience while traveling. Utilizing mmWave technology, LightningBlu is capable of offering carrier-grade performance, supporting Mobility applications with remarkable consistency even at speeds exceeding 300 km/h. Such capabilities promise to revolutionize the connectivity standards within the high-speed rail networks. By integrating this advanced system, railway operators can ensure uninterrupted communication channels, thus optimizing their operations and boosting passenger satisfaction. The solution primarily operates within the mmWave spectrum of 57-71 GHz, making it a future-proof choice that aligns with the expanding global demand for high-quality, high-speed railway communications. With LightningBlu, Blu Wireless is spearheading the movement towards carbon-free, robust connectivity solutions, setting a new standard in the transportation sector.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The Polar ID is an innovative biometric security system that elevates facial recognition technology through its use of sophisticated meta-optics. By capturing and analyzing the unique polarization signature of a face, Polar ID delivers a new standard in security. This system can detect spoofing attempts that incorporate 3D masks or other similar deceptive tactics, ensuring high security through accurate human authentication. Polar ID minimizes the complexity typically associated with face recognition systems by integrating essential optical functions into a single optic. Its compact design results in cost savings and reduces the space required for optical modules in devices like smartphones. Operating in near-infrared light, Polar ID can consistently deliver secure face unlock capabilities even under challenging lighting conditions, dramatically outperforming traditional systems that may fail in bright or dark environments. The platform does not rely on time-of-flight sensors or structured light projectors, which are costly and complex. Instead, Polar ID leverages the simplicity and efficiency of its single-shot identification process to deliver immediate authentication results. This makes it a potent tool for securing mobile transactions and providing safer user experiences in consumer technology.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Hyperspectral Imaging System developed by Imec is designed to capture images across numerous wavelengths, enabling detailed analysis of spectral information beyond conventional imaging. This hyperspectral imaging technology is pivotal in extracting valuable insights in fields such as precision agriculture, environmental monitoring, and industrial inspection. With its versatile applications, it offers enhanced capabilities in material identification, chemical analysis, and quality control processes. This system incorporates state-of-the-art sensors that capture data with high spectral and spatial resolution, providing a comprehensive spectral fingerprint of the imaged scene. It excels in distinguishing subtle differences in material properties by analyzing the light reflected from different surfaces across various spectral bands. By using this advanced imaging system, users can perform complex analyses such as vegetation monitoring, pollution detection, and mineral mapping with unprecedented precision. It allows for non-destructive testing, which is crucial for industries like food safety, pharmaceutical production, and environmental science.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
The RF-SOI and RF-CMOS platform is distinguished by its ability to optimize wireless communication components for high frequencies and low power consumption applications. Building on Silicon on Insulator (SOI) technology, this platform allows for improved isolation and reduced parasitic capacitance, enhancing RF performance. This combination of SOI and CMOS technology provides the versatility needed to address stringent requirements in RF signal processing, making it a prime choice for designing cutting-edge wireless devices. The technology's capabilities support advancements in 5G networks and IoT devices, where precision and efficiency are critical. Designed for scalability, the RF-SOI and RF-CMOS platform empowers engineers to leverage component miniaturization while maintaining excellent performance, catering to the demands of complex infrastructure requirements in the telecommunications industry.
ParkerVision's Energy Sampling Technology is a state-of-the-art solution in RF receiver design. It focuses on achieving high sensitivity and dynamic range by implementing energy sampling techniques. This technology is critical for modern wireless communication systems, allowing devices to maintain optimal signal reception while consuming less power. Its advanced sampling methods enable superior performance in diverse applications, making it a preferred choice for enabling efficient wireless connectivity. The energy sampling technology is rooted in ParkerVision's expertise in matched filter concepts. By applying these concepts, the technology enhances the modulation flexibility of RF systems, thereby expanding its utility across a wide range of wireless devices. This capability not only supports devices in maintaining consistent connectivity but also extends their battery life due to its low energy requirements. Overall, ParkerVision's energy sampling technology is a testament to their innovative approach in RF solutions. It stands as an integral part of their portfolio, addressing the industry's demand for high-performance and energy-efficient wireless technology solutions.
VocalFusion is a cutting-edge voice processing solution by XMOS, designed to deliver superior voice interaction capabilities in various applications. It integrates advanced beamforming, noise suppression, and voice command processing, ensuring flawless operation even in challenging environments. VocalFusion handles wake-word detection efficiently, providing a seamless interface for voice-enabled devices, ranging from smart home speakers to automotive assistants and interactive kiosks. This chip ensures that voice interactions occur swiftly and accurately without cloud dependency, thus maintaining data privacy. Embedded with XMOS's sophisticated DSP and real-time processing capabilities, VocalFusion ensures low-latency performance, making it a suitable choice for environments where quick response and precise voice input are crucial. Its architecture accommodates complex audio processing tasks, including active noise cancellation and echo reduction, contributing to clear and intelligible voice communication. The integration of VocalFusion into a system simplifies the design and reduces components needed, enhancing both functionality and system cost-effectiveness. In addition to consumer electronics, VocalFusion finds applications in industrial and automotive sectors, where its determinism and reliability are pivotal. By optimizing voice capture and processing, it supports the development of innovative solutions that require high-quality voice input. VocalFusion is a quintessential example of XMOS's expertise in delivering state-of-the-art voice technology that meets the evolving needs of modern interactive systems.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
The DVB-S2 Modulator is engineered to accommodate both DVB-S2 and DVB-S2X satellite forward-link specifications. This high-performance modulator core supports (A)PSK modulation schemes and is particularly suitable for both broadcasting and interactive applications. Its design is focused on delivering advanced functionalities while ensuring compliance with dynamic satellite communication standards. This makes it well-suited for a variety of professional and commercial telecommunications applications. The modulator is ideal for delivering superior broadcast experiences with increased efficiency and reliability.
The HDR Core from ASICFPGA addresses the frequent issue of capturing images with a high dynamic range that surpasses the sensor’s capabilities. By acquiring multiple exposures at different levels, this core synthesizes them into a single image that adequately preserves details across various lighting conditions. Incorporating advanced motion detection and compensation algorithms, it minimizes ghosting and compresses the high dynamic range to fit within the display device's capabilities through a unique tone mapping procedure.
The DVB-Satellite Modulator is a high-performance modulator core designed to adhere to DVB-S, DSNG, DVB-S2, and DVB-S2X satellite forward-link specifications. This versatile modulator core is engineered for both broadcasting and interactive applications, accommodating a variety of modulation schemes including (A)PSK. Its robust framework is capable of delivering efficient and reliable operations in challenging satellite communication environments. The modulator's design prioritizes support for advanced satellite communication standards, ensuring its place in future-ready satellite systems.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
The PCE04I Inmarsat Turbo Encoder is engineered to optimize data encoding standards within satellite communications. Leveraging advanced state management, it enhances data throughput by utilizing a 16-state encoding architecture. This sophisticated development enables efficient signal processing, pivotal for high-stakes communication workflows. Furthermore, the PCE04I is adaptable across multiple frameworks, catering to diverse industry requirements. Innovation is at the forefront with the option of integrating additional state Viterbi decoders, tailoring performance to specific needs and bolstering reliability in communications.
Focused on meeting the ETSI DVB-CID carrier identification standard (EN103129), the DVB-CID Modulator integrates both modulation and channel coding functionalities into a single cohesive core. This integration is aimed at addressing specific carrier identification requirements within satellite communication systems. By streamlining these processes, the modulator enhances operational efficiencies while ensuring adherence to key industry standards. The DVB-CID Modulator effectively supports sophisticated satellite communication systems demanding reliable carrier identification capabilities.
The DVB-S2-LDPC-BCH decoder is pivotal for digital video broadcasting applications, particularly in satellite transmissions requiring robust FEC subsystems. The IP employs LDPC codes integrated with BCH codes to deliver a near-error-free operation closely approaching the Shannon limit. Key technologies supporting this include the irregular parity check matrix for enhanced correction, layered decoding for improved efficiency, and the minimum sum algorithm allowing for soft decision processing. This sophisticated decoding approach ensures high-performance data transmission, adhering to stringent industry standards.
The 5G ORAN Base Station is designed to be a cornerstone in the next generation of mobile networking. With 5G, wireless communication will see unprecedented growth in data capacity and opportunities for novel wireless applications. This base station enhances the efficiency and coverage of mobile networks, fostering the growth of smart cities, connected devices, and industrial automation. It integrates seamlessly with various network architectures, making it a versatile component in the telecommunications sector.
High-performance and versatile, the DVB-S Demodulator is designed to comply with DVB-S and DSNG satellite forward-link specifications. The core processes (A)PSK modulation schemes, suitable for both broadcast and interactive applications. This demodulator enhances signal clarity and integrity, enabling robust satellite communication operations. Its design is optimized for the demands of modern satellite broadcast environments, ensuring reliability and superior performance.
Built to support the advanced DVB-S2 and DVB-S2X satellite forward-link standards, the DVB-S2 Demodulator offers high-performance functionality for modern broadcasting needs. The core is designed to efficiently process (A)PSK signals, effectively enhancing the transmission quality of both broadcast and interactive services. It is integral to operations requiring compliance with sophisticated satellite communication protocols, helping deliver consistent, high-quality broadcast content.
The IMG CXM GPU represents a milestone in efficient graphics processing, being Imagination’s smallest GPU that supports HDR user interfaces. Engineered for versatility, this GPU is designed to deliver high-quality, vibrant graphics even in space-constrained devices, such as wearable tech and smart home systems. By utilizing Tiny Frame Buffer Compression v2, the IMG CXM achieves significant reductions in power and memory bandwidth usage, maintaining superior visual experiences at lower energy costs. This high-efficiency GPU is also well-suited for diverse applications, from digital televisions and set-top boxes to AR/VR systems, where cost-effectiveness is as important as performance. Its gesture recognition capabilities are particularly beneficial in enhancing interactive user interfaces, allowing manufacturers to incorporate AI functionalities while maintaining a small silicon footprint. CXM GPUs feature Imagination’s unique architecture innovations that emphasize minimum area usage while maximizing graphical output, leading to a superior balance of performance and energy consumption. For content providers aiming to elevate consumer experiences with cinematic-style UIs, the CXM GPU supports advanced graphical features, such as high-dynamic-range (HDR), ensuring that devices deliver crisp, detailed visuals that engage users effectively.
The SBR6201 transceiver from SaberTek supports dual compatibility with 802.15.4g and 802.11ah standards, making it a versatile choice for applications like wireless metering and smart grid communications. This transceiver is optimized for performance in challenging environments, providing reliable networking capabilities even in dense area deployments. It excels in forming mesh networks that are resilient in harsh conditions, offering solid performance well above standard requirements.
Creonic's demodulation IP cores deliver robust capabilities for fast synchronization and adaptive equalization, essential for satellite ground stations and space communication systems. They are compatible with standards like DVB-S2X and DVB-RCS2, as well as other demanding protocols, ensuring versatility across different communication setups. These cores are engineered to handle real-world signal challenges, maintaining robustness and functionality under varying conditions. Their flexible design allows for the customization of waveforms to meet specific user needs, making them indispensable in today's complex communication environments. Utilizing Creonic's demodulation technology, users can achieve enhanced signal integrity and performance, whether used in terrestrial or satellite infrastructure. These cores provide a reliable solution for efficient data processing in high-stakes communication fields.
Designed for high-speed signal processing, the RFSoC-Module with AMD Zynq UltraScale+ ZU47DR-1E integrates RF data converters directly onto the Zynq platform. This integration simplifies the design of high-frequency applications, such as radar systems and wireless infrastructure, by reducing latency and improving signal integrity. It supports rapid prototyping and deployment in the field with its powerful processing and real-time capabilities.
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