All IPs > Wireless Communication > 3GPP-5G
The evolution of mobile communication technology has reached a pivotal stage with the introduction of 3GPP-5G, a standard that promises to transform wireless communications. In the realm of semiconductor IP, 3GPP-5G solutions encompass a wide range of technologies that are integral to developing and deploying next-generation communication networks. These semiconductor IPs provide the foundational architecture required for high-speed data transfer, ultra-reliable low latency, and massive connectivity, supporting the diverse and demanding use cases of modern mobile and IoT applications.
3GPP-5G semiconductor IP solutions are crucial for manufacturers and developers looking to design cutting-edge communication systems. These IPs enable the seamless integration of 5G capabilities into a variety of devices, from smartphones and smart home appliances to industrial IoT sensors and autonomous vehicles. They are designed to handle complex signal processing, support multiple frequency bands, and deliver enhanced performance metrics such as increased bandwidth and improved energy efficiency. By leveraging these semiconductor IPs, companies can significantly reduce time-to-market and development costs while ensuring that the end devices meet stringent 5G standards.
Within this category, you'll find a broad array of semiconductor IP products tailored to meet the specific challenges and opportunities posed by 5G networks. These include baseband processors, RF transceivers, and advanced modulation solutions, all of which are engineered to support the high demands of 5G technology. Furthermore, these IPs often come with software support and development kits that facilitate faster adoption and implementation into existing systems.
As the world moves towards more interconnected and intelligent systems, 3GPP-5G semiconductor IPs provide the essential building blocks for future innovations. By enabling the next generation of wireless communication, these IPs not only enhance current technologies but also pave the way for new applications and services that were previously unimaginable. Whether you are developing solutions for consumer electronics, automotive, healthcare, or smart cities, the 3GPP-5G semiconductor IP category offers the tools and technologies to bring your vision to life.
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
The Digital PreDistortion (DPD) Solution from Systems4Silicon is a comprehensive adaptive technology aimed at improving the efficiency of RF power amplifiers. It is designed to maximize amplifier performance by allowing operation in the non-linear region while significantly reducing distortion. The solution is highly scalable, allowing for resource optimization across bandwidth, performance, and multiple antenna configurations. It is technology-agnostic, supporting various transistor technologies such as LDMOS and GaN, and can be adapted to different amplifier topologies including Doherty configurations. Benefits of the DPD technology include achieving over 50% efficiency improvements when utilized alongside the latest GaN devices, with amplifier distortion improvements of over 45 dB. This IP also supports multi-carrier and multi-standard transmissions, covering a broad array of standards such as 3G, 4G, 5G, DVB, and many more. It is compliant with the O-RAN standard for 7-2x deployments, making it a versatile solution for modern wireless communication systems. Systems4Silicon's DPD solution includes comprehensive integration and performance analysis tools, backed by expert support from experienced radio systems engineers. Designed for both FPGA/SoC and ASIC platforms, it provides a low resource footprint while ensuring maximum efficiency across diverse applications.
The 802.11ah HaLow Transceiver is engineered to fulfill the demands of modern IoT applications, where low power consumption and extended range are critical. It aligns with the IEEE 802.11ah standard, commonly termed as Wi-Fi HaLow™, and offers exceptional flexibility for new generations of IoT and mobile devices.\n\nBoasting features like low noise direct conversion and integrated calibration for I/Q pathways, this transceiver supports multiple modulation bandwidths, including 1 MHz, 2 MHz, and up to 4 MHz. With its capabilities spanning significant frequency ranges, the design ensures stable connectivity with minimum latency and enhanced receiver sensitivity.\n\nOne of its strengths lies in extensibility, providing superb integration potential either as a part of a broader system-on-chip (SoC) or as a standalone communication module. Designed with minimal power draw, it also allows using external power amplifiers to enhance transmission power, aligning with diverse application needs such as asset tracking, building security, and broader sensor networks.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The mmWave PLL offers precise high-frequency synthesis capabilities, ideal for mmWave communication applications. Designed to support the demanding requirements of modern telecommunications, this phase-locked loop circuit excels in providing stable and low phase noise performance at extremely high frequencies. This product is tailored for next-generation wireless systems, including 5G networks and beyond, where high data rates and low latency are critical. Its robust architecture allows it to deliver exceptional performance in bandwidth-intensive environments, making it a critical component in advanced RF front-end solutions. mmWave PLL's ability to maintain frequency stability while handling various interference and environmental variables highlights its importance in the seamless operation of high-speed communication infrastructures.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
AccelerComm offers an innovative LDPC solution specifically for 5G NR systems, pushing the boundaries of performance with its advanced block-parallel and row-parallel architectures. This sophisticated solution enhances data channel performance by utilizing a combination of scalability, high throughput, and low latency to maintain optimal communication systems. The LDPC solution effectively addresses standard 5G data channels, achieving substantive gains in resource utilization efficiency. By improving the already stringent latency specifications to support numerology 4, the solution ensures comprehensive code and transport block processing capabilities. It also upholds IEEE standards, providing a compliant pathway for high reliability and operational efficiency. Designed for integration across multiple platforms, including ASIC, FPGA, and software form factors, LDPC’s flexibility allows for deployment in a range of network conditions. Its open standard software interfaces make it easily adaptable, presenting a robust and versatile framework for companies to enhance their 5G network communication protocols with minimal effort.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
Polar coding, a relatively recent addition to the 5G NR suite of technologies, is embraced by AccelerComm through their unique design that facilitates higher degrees of parallel processing. This advancement ensures operational efficiency and minimizes resource usage, thereby improving system robustness and throughput in 5G NR control channels. By employing a patented architecture, Polar coding exhibits flexibility and scalability, key to supporting high-performance 5G requirements. The reduced burden on hardware resources enables it to deliver superior BLER performance, crucial for meeting the stringent demands of modern telecommunications standards. Delivering across a spectrum of platforms, whether hardware-based like ASIC and FPGA or software-driven, Polar coding maintains a high degree of integration ease. This allows rapid deployment and alignment with existing infrastructure, ensuring seamless communication and data integrity in a wide array of network scenarios.
The pPLL08 Family is a state-of-the-art lineup of all-digital RF frequency synthesizer PLLs engineered for high-frequency applications including 5G and WiFi. These PLLs are designed to deliver ultra-low jitter performance, achieving less than 300 femtoseconds RMS, while supporting frequencies up to 8GHz. Their exceptionally compact area of less than 0.05 square millimeters and low power consumption of under 15 milliwatts make them suitable for demanding RF environments. Built using Perceptia's second-generation digital PLL technology, the pPLL08 Family excels in maintaining consistent output regardless of PVT conditions, offering robust performance in RF applications as a local oscillator or clocking solution for high-performance ADCs and DACs. Its digital architecture minimizes interference from shared die circuits, ensuring superior signal-to-noise ratio performance. The PLLs in this family are available across numerous process technologies, including leading foundries like UMC and TSMC, ensuring flexibility and broad applicability. Perceptia also provides extensive integration support and adaptability for customization, tailoring solutions to meet specific hardware requirements and optimizing integration into various system architectures.
A trailblazer in high-speed rail connectivity, LightningBlu offers a groundbreaking, track-to-train multi-gigabit mmWave solution. This technology is renowned for its seamless integration with train networks, providing stable and fast connections crucial for high-speed transport. LightningBlu operates efficiently over a rail-friendly frequency range from 57-71 GHz and delivers an impressive data throughput of up to 3.5 Gbps. The system comprises both trackside and train-top nodes, each featuring innovative two-sector radios to ensure continuous, dynamic connection between the train and the trackside infrastructure. The design includes components qualified for rugged rail environments, promising extended service life and low maintenance needs. The solution significantly boosts operational efficiency for rail networks, being deployed in key infrastructures like South Western Railways and Caltrain in Silicon Valley. Versatile and resilient, LightningBlu adapts to varied complexities found in high-speed transport contexts. It communicates data faster than 5G while maintaining lower power consumption than traditional mobile networks, ensuring a superior commuter experience through its reliability and speed.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The RWM6050 is a power-efficient baseband modem designed for high-capacity mmWave communication, ideal for market segments that require cost-effective and high-performance solutions. Developed in partnership with Renesas, this modem pairs seamlessly with mmWave RF chipsets to provide a highly configurable radio interface suitable for access and backhaul applications. Equipped with flexible channelisation and modulation coding capabilities, the RWM6050 can scale bandwidth to support multi-gigabit data transfers, boasting dual modem features and a mixed-signal front-end. This flexible architecture supports versatile deployment scenarios, enabling robust and high-speed connectivity over moderate distances. The RWM6050’s beamforming capabilities, enhanced by a phased array antenna, and advanced digital front-end processing, make it ideal for sophisticated data links. The modem integrates network synchronization and provides programmable real-time scheduling, affirming its role as a pivotal element in delivering reliable mmWave communication.
The MVUM1000 represents MEMS Vision's leading-edge innovation in ultrasound technology for medical imaging. This compact 256-element linear ultrasound array is designed using state-of-the-art capacitive micromachined ultrasound transducers (CMUTs), allowing for exceptional integration with interface electronics. Known for its energy efficiency and high sensitivity, the MVUM1000 delivers precise acoustic pressure detection, crucial for advanced imaging techniques. Supporting multiple imaging modes such as time-of-flight and Doppler, it is highly suited for applications ranging from point-of-care to cart-based ultrasound systems. The MVUM1000 array, with its 4.5 MHz center frequency and up to 256 elements, strikes a balance between fine resolution and powerful imaging capabilities, critical for medical diagnostics. The array's flexible design includes features like integrated front-end electronics and adjustable voltage inputs, enhancing its versatility in various contexts. Such capabilities not only improve imaging clarity but also support quick deployment in medical devices, further solidifying MEMS Vision's role in medical sensor innovation.
Under its eSi-Comms brand, EnSilica delivers a suite of highly parameterized communications IP solutions that play a crucial role in supporting modern communication standards such as 4G, 5G, Wi-Fi, and DVB. These IP blocks are designed to streamline the development of ASIC designs by providing a robust platform for OFDM-based modem solutions. The IP suite features advanced DSP algorithms for synchronization, equalization, demodulation, and channel decoding, ensuring robust communication links. It's optimized for integration into systems requiring flexibility and high performance.
AccelerComm's Software-Defined High PHY is a malleable solution, catered to the ARM processor framework, capable of fulfilling the diverse requirements of modern telecommunications infrastructures. This technology is renowned for its optimization capabilities, functioning either with or without hardware acceleration, contingent on the exigencies of the target application with regards to power and capacity. The implementation of Software-Defined High PHY signifies a leap in configuring PHY layers, facilitating adaptation to varying performance and efficiency mandates of different hardware platforms. The technology supports seamless transitions across platforms, making it applicable for a spectrum of use cases, harmonizing with both flexible software protocols and established hardware standards. By uniting traditional hardware PHY layers with modern software innovations, this solution propels network performance while reducing latency, enhancing data throughput, and minimizing overall system power consumption. This adaptability is vital for enterprises aiming to meet the dynamic demands for quality and reliability in wireless communication network setups.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The 802.15.4 Transceiver Core is specifically crafted to support low-power, wireless personal area networks. As a standard for Zigbee, it aims at enabling robust and reliable communication between devices in applications such as home automation, smart metering, and industrial controls. This transceiver core is characterized by its excellent RF performance and energy efficiency, ensuring prolonged device operation with minimal power consumption. This IP core's architecture features advanced error correction and modulation schemes, bolstering performance even in environments with interference. It is engineered for ease of integration, ensuring that manufacturers can seamlessly incorporate it into their products, enabling rapid development cycles and time-to-market. Through its interoperability with other 802.15.4 devices, this transceiver facilitates the creation of extensive wireless network applications. Ideal for both consumer and industrial applications, it allows for flexible network configurations and robust data handling, making it a cornerstone for IoT development.
TES's Ultra-Wideband (UWB) technology is crafted to provide high precision and secure wireless communication solutions. UWB technology is characterized by its ability to transmit large amounts of data over short distances with minimal power usage, making it perfect for applications requiring high-speed data transfer and low-power consumption. This technology is particularly beneficial in scenarios such as indoor positioning and short-range communications, where accuracy and reliability are crucial. TES's UWB IP integrates seamlessly with various devices, offering enhanced connectivity options for applications in automotive, industrial, and consumer electronics. Its robust architecture supports real-time data processing and secure connectivity, making it ideal for environments where precise wireless communications are imperative.
The LTE Lite processor offered by Wasiela is a streamlined implementation of the Long-Term Evolution (LTE) standard, specifically configured for user equipment (UE) supporting CAT 0 and CAT 1 PHY layers. This design delivers flexible input bandwidth options, ranging from 1.4 MHz to 20 MHz, accommodating various deployment scenarios. LTE Lite supports a range of modulation schemes including QPSK, 16QAM, and 64QAM, facilitating adaptability to diverse communication environments. Incorporating an automated operation managed by a master finite state machine, the LTE Lite processor integrates seamlessly with RF tuners via an external analog-to-digital converter. This allows for effective handling of frequency offsets and ensures precise timing and frequency correction, capable of compensating offsets up to 500 kHz. The LTE Lite processor offers both parallel and serial output configurations, enhancing its versatility in application integration. Designed as synthesizable Verilog-2001 IP, the LTE Lite is portable across platforms, ensuring a wide range of deployment options. With Matlab simulation models and robust documentation included, the LTE Lite processor provides a powerful toolset for manufacturers aiming to implement LTE technologies efficiently and effectively. Its compact and adaptable design is ideal for meeting the demands of modern mobile communications.
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems, so a powerful FEC code is needed. The New Radio (NR) FEC for the control channel is designed based on Polar codes, allowing close to the Shannon limit/Capacity operation. It features Polar code successive cancellation decoding, as needed for the 3GPP physical layer standard, with Parity Check bits that simplify the pruning of the search tree. The encoding of the NR Polar code is performed in GF(2), structured using static reliabilities from the ETSI standard. This IP Core supports a maximum code block length of 1024 bits and a minimum of 32 bits. It can be easily integrated with interleavers and Rate matching circuitry to support all rates required by 5G NR. Additional features include successive cancellation decoding with list decoding, soft decision decoding, high peak rates, low latency, and compliance with the 3GPP TS 38.212 V15.1.1 standard. The IP Core is suitable for applications such as 3GPP-LTE Rel. 15 control channels, 5G NR air interfaces, machine-to-machine communication, and high traffic IoT.
Tower Semiconductor’s RF-SOI and RF-CMOS platforms are crucial for developing state-of-the-art wireless communication systems. These technologies offer enhanced performance for RF applications, featuring efficient power handling and reduced interference, which are critical for high-frequency wireless communication. RF-SOI technology provides isolation benefits that enhance overall RF performance by minimizing crosstalk and interference. Meanwhile, RF-CMOS backs this with lower power consumption and integration capability, pivotal for the stringent demands of modern wireless protocols. The versatility of these platforms allows their application in next-generation wireless technologies and infrastructure, supporting everything from consumer devices to telecommunications equipment. The collaboration of SOI and CMOS technologies in radio frequency align with industry trends towards miniaturization and energy efficiency in wireless communication devices.
The Complete 5G NR Physical Layer solution by AccelerComm is designed to provide exceptional performance for demanding applications in O-RAN and satellite networks. This all-encompassing solution integrates high-accuracy signal processing technology, ensuring optimal link performance and efficient power usage. The physical layer is inherently flexible, allowing performance optimizations tailored to meet specific requirements of specialized network applications. This solution navigates the complex real-world dynamics involved in high-performance network scenarios, including both terrestrial and space-based communications. By leveraging advanced algorithms and architectures, the 5G physical layer supports customizable configurations, leading to power and area efficiency improvements. Through interoperability with multiple hardware platforms, it maximizes the performance of 5G networks, enhancing the user experience by minimizing latency and maximizing throughput. Delivered as openly-licensable intellectual property, the 5G NR Physical Layer can function across a wide range of platforms, such as ARM software and FPGA, ensuring broad compatibility. This strategic approach facilitates quicker project advancements through seamless integration and testing processes on multiple development boards, thereby reducing project risks effectively.
ParkerVision's Energy Sampling Technology is a state-of-the-art solution in RF receiver design. It focuses on achieving high sensitivity and dynamic range by implementing energy sampling techniques. This technology is critical for modern wireless communication systems, allowing devices to maintain optimal signal reception while consuming less power. Its advanced sampling methods enable superior performance in diverse applications, making it a preferred choice for enabling efficient wireless connectivity. The energy sampling technology is rooted in ParkerVision's expertise in matched filter concepts. By applying these concepts, the technology enhances the modulation flexibility of RF systems, thereby expanding its utility across a wide range of wireless devices. This capability not only supports devices in maintaining consistent connectivity but also extends their battery life due to its low energy requirements. Overall, ParkerVision's energy sampling technology is a testament to their innovative approach in RF solutions. It stands as an integral part of their portfolio, addressing the industry's demand for high-performance and energy-efficient wireless technology solutions.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
The RFicient chip stands out for its ultra-low power consumption and remarkable efficiency, making it particularly suitable for Internet of Things (IoT) applications. This chip is designed to operate in energy-constrained environments, delivering high performance while maintaining minimal energy usage. It is engineered to facilitate long-term, maintenance-free operations in IoT devices, which are often deployed in remote or hard-to-reach locations. With a focus on sustainability, the RFicient chip significantly reduces energy consumption, extending the battery life of IoT devices. Its compact and robust design allows for seamless integration into various IoT systems, from smart homes to industrial IoT networks, providing reliable connectivity and data transmission under diverse environmental conditions. This chip not only supports the efficient gathering and processing of IoT data but also furthers ecological goals by reducing the carbon footprint associated with IoT deployments.
The PCS2100 is a cutting-edge modem chip, specifically designed to facilitate the deployment of Wi-Fi HaLow networks, an extension of the Wi-Fi standard that enhances IoT connectivity. Based on the IEEE 802.11ah norm, this chip caters primarily to IoT devices, functioning proficiently within a network spearheaded by the PCS2500 access point. Its strength lies in its ability to operate over sub-gigahertz frequencies, offering extended transmission range that reaches over one kilometer.\n\nIncorporating innovative network management functions tailored for IoT, the PCS2100 ensures a robust and scalable connection with low power consumption, essential for densely packed IoT scenarios. The chip supports modulation schemes that enhance its capacity to manage receiver sensitivity and correct phase noise, contributing to its efficient transmission and reception.\n\nFocused on extending battery life while ensuring consistent IoT connectivity, features such as resource allocation windowing and target wake time optimize the network's power usage. This makes the PCS2100 an ideal candidate for long-term operational devices like sensors, providing extended communication life cycles while maintaining high data throughput.
Specializing in advanced communication technologies, this module is tailored for WiFi6, LTE, and 5G networks. It is engineered to optimize RF front-end performance for next-generation wireless communication standards. This module ensures reliable and fast data transfer rates, crucial for applications ranging from mobile networks to IoT (Internet of Things) infrastructure, enabling high-speed connectivity and reduced latency.
This Complete RF Transceiver is engineered to operate efficiently within the 433, 868, and 915 MHz ISM bands, making it ideal for industrial IoT and smart metering applications. The transceiver supports extensive data rates ranging from 1.2 k to 500 kbps, adapting to various communication requirements. Built to comply with IEEE 802.15.4-2015 standards, it offers robust wireless communication with minimal interference. The transceiver is designed using low-power technology to ensure long-lasting performance in battery-operated devices, providing competitive advantage in energy-sensitive applications.
The PUSCH Equalizer by AccelerComm aims to improve the spectral efficiency of systems operating with multiple antennas, focusing on eliminating noise and interference through sophisticated signal processing. It's an essential feature for uplink communications, making it a perfect fit for next-generation 5G networks where performance integrity is crucial. Built upon advanced equalization algorithms, this solution integrates harmoniously with existing PUSCH Decoder units, seamlessly supporting Universal Communication Identifier (UCI) over PUSCH with the addition of an Equalizer block. It excels in enhancing spectral efficiency in various deployment scenarios by seamlessly incorporating equalization, demodulation, LDPC, and polar decoding functions. The PUSCH Equalizer is known for providing significant cost-efficiency and power reduction per bit processed. It’s available for both FPGA and ASIC platforms, meeting varied application requirements for interoperability and minimizing time-to-market timelines—ideal for enterprises keen on reducing deployment and operational costs while maximizing network performance.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
The NB-IoT (LTE Cat NB1) Transceiver is a versatile module built to adhere to the 3GPP Release 13 standard, with additional capability for Release 14 compliance. Its design offers high performance for both transmitter and receiver functions, meeting stringent 3GPP specifications with margin for enhanced reliability.\n\nOperating predominantly within cellular bands, the transceiver utilizes a low-power profile to ensure efficiency, offering analog interfaces for straightforward integration and testing. Its programmability via an SPI interface makes it suitable for a wide range of applications and testing environments.\n\nEngineered to interface effortlessly with baseband and MAC layers, this transceiver is an optimal solution for IoT implementations where long battery life and reliable connection quality are paramount. The NB-IoT module provides the necessary signal control for correcting DC offsets, ensuring consistent performance and facilitating integration across various IoT applications.
The Crest Factor Reduction (CFR) Technology developed by Systems4Silicon serves to enhance RF power amplifier efficiency by curbing the transmit signal envelope. This technology operates agnostically to communication standards, allowing it to be deployed across various systems with ease. FlexCFR is dynamically reprogrammable, making it highly adaptable to both single and multi-standard operations. By managing the Peak to Average Power Ratio (PAPR), it facilitates more efficient amplifier operation, thus reducing overall amplifier costs by enabling the use of more cost-effective power transistors. FlexCFR's design ensures that it is vendor-independent, offering compatibility with any FPGA or ASIC platform, and includes flexible licensing terms to fit different business models. The technology minimizes its resource footprint, maintaining system efficiency without compromising performance. Its deterministic behavior allows for reliable off-line system modeling, which is advantageous for predicting and optimizing system performance. This CFR solution is compatible with other technologies like digital predistortion (DPD) and envelope tracking, making it a comprehensive solution for power amplifier efficiency enhancement. Supported by advanced tools and knowledgeable radio systems engineers, it ensures smooth integration and robust operation in a wide range of deployment scenarios.
The FCM3801-BD is designed for those requiring 39GHz CMOS Power Amplification within the 5G mmWave range. It supports frequencies from 32 to 44 GHz, featuring a 19 dB gain and a Psat of 18.34 dBm. With a PAE of 45%, this amplifier is engineered for high-power applications where efficiency and thermal management are crucial. It's particularly suited for modern telecom environments requiring minimal energy use and weight savings.
Cobalt is an ultra-low-power GNSS receiver designed specifically for chipset integration to expand the market capabilities of IoT System-on-Chip (SoC) products. This GNSS receiver stands out for its ability to drastically reduce energy consumption while maintaining high performance in geolocation tasks. This makes Cobalt an ideal choice for IoT applications where battery life is critical, such as in wearable technology and remote asset tracking devices. By integrating Cobalt into chipsets, developers can enhance their products with robust and reliable GNSS functionalities without eliminating critical power resources, thus maintaining extended operational periods for their IoT devices. Cobalt's design caters to evolving needs in IoT infrastructures by supporting efficient satellite communication, essential for precise and reliable real-time location tracking. Its inclusion in SoC designs fosters the development of sophisticated IoT products capable of delivering real-time, accurate geolocation data, accelerating the integration of smart technologies across various sectors.
The LDPC Decoder caters to 5G Network Release (NR) standards, providing a reliable decoding process crucial for modern communication systems. Utilizing the Min-Sum decoding algorithm, it offers configurable bit widths and supports early termination through a concurrent parity check engine, enhancing decoding efficiency. In addition, the decoder’s architecture accommodates flexible iteration settings, optimal for applications reliant on re-transmission protocols such as HARQ. Embedded in its design is a focus on reducing power usage and maximizing throughput, suitable for various network scenarios and demanding 5G applications.
PhantomBlu represents Blu Wireless's state-of-the-art mmWave technology tailored for military and defense use. This advanced solution supports tactical communication between vehicles, whether on land, sea, or air, by leveraging a stealthy mesh network capable of running applications and IP networking over an anti-jam resistant infrastructure. The PhantomBlu network offers flexibility and scalability to meet various operational demands within defense environments, from securing critical infrastructure to enabling convoy communications and integrating airborne systems. Its ability to provide high bandwidth in real-time ensures communication is reliable and secure, even in complex and hostile environments. With features like 10x data rates compared to Wi-Fi and 5G, reduced size, weight, and power requirements, and future-proof scalability, PhantomBlu is built for seamless integration with existing military systems. The solution further offers long-range communication up to 4km, incorporating advanced features like antenna beamforming for improved signal processing, making it a robust component for military networks.
The PCS1100 is a versatile RF transceiver chip designed to facilitate Wi-Fi 6E networks, leveraging the IEEE 802.11ax specification. This sophisticated module operates within the RF domain, acting as the RF component of a Wi-Fi 6/6E access point or station, offering multi-band support including 6GHz Wi-Fi. It excels as a companion chip to a host controller, enabling seamless MAC and baseband digital operations for Wi-Fi 6/6E.\n\nNotable for its multi-user MIMO and dual-band concurrent capabilities, the PCS1100 efficiently handles multiple spatial streams, thereby optimizing network performance. It supports advanced modulation schemes up to 1024-QAM, promising robust connectivity even in congested environments. Its power-optimized design ensures efficient operation, minimizing the energy footprint while maximizing throughput.\n\nDeveloped with advanced RF engineering practices, the PCS1100 features an analog I/Q interface and components necessary for consistent calibration and signal path compensation. Its design guarantees adaptability and reliability across varying conditions, making it an ideal choice for high-density environments like smart cities, universities, and industrial applications.
The FCM2801-BD is a 28GHz CMOS Power Amplifier, specifically designed for applications in the 5G mmWave spectrum. It operates across a frequency range of 23 to 36 GHz and delivers a gain of 22 dB with a Psat of 19.55 dBm. Boasting a PAE of 53%, this amplifier suits high-frequency telecommunications, offering improved range and reduced energy consumption. The design minimizes thermal output, which further aids in reducing system maintenance costs.
Post-Quantum Cryptography IP offers a hardware-based solution integrated with software capabilities to ensure secure communications in a quantum computing era. Designed with quantum resistance in mind, it supports key exchange, encapsulation, and decapsulation functions using lattice-based algorithms. This IP is equipped with measures to protect against side-channel attacks, including simple power analysis and differential power analysis. Offering interfaces like AMBA, it ensures flexibility in integration within various systems, positioning it as a crucial component for future-proofing communication security against the impending challenges of quantum computation.
ARDSoC extends the capabilities of DPDK to ARM-based SoCs, enabling efficient packet processing that bypasses the traditional Linux network stack. This IP core saves valuable ARM processor cycles and integrates smoothly with distributed network applications, especially those relying on containers and embedded protocol bridges. The key benefit of ARDSoC is its ability to drastically reduce power consumption, latency, and the overall TCO when transitioning from x86 architectures. This is achieved by optimizing the ARM CCI-400 Cache performance and utilizing zero copy DPDK coherent memory structures. The IP supports popular ARM architectures like A53 and A72 and can achieve up to 64 Gbps throughput under nominal operating conditions. ARDSoC is particularly useful for cloud-edge devices requiring robust network processing capabilities. Its compatibility with existing DPDK programs ensures developers can easily migrate and integrate their applications with minimal modifications, supported by Atomic Rules' commitment to innovation and real-world application needs.
Engineered for modern wireless networking needs, the Wi-Fi 6 IP is fully compliant with the 802.11ax protocol, ensuring backward compatibility with previous iterations such as Wi-Fi 4 and 5. This IP delivers augmented bandwidth and improved network performance, making it the ideal choice for high-density environments demanding effective network communication. Tailored for seamless integration in smart devices, this IP underscores reliability with reduced latency and enhanced connection speeds.
The 39GHz 1W Power Amplifier is tailored for 5G mmWave applications, boasting significant power efficiency. Fabricated with 0.15um PHEMT technology, this amplifier operates between 38 to 42GHz, delivering 19dB of gain with a third-order intercept point (IP3) of 40dBm. With a power of 31dBm at P-1dB, it's housed in a surface-mount technology (SMT) package, ensuring optimal integration in high-frequency systems.
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