All IPs > Wireless Communication > 3GPP-5G
The evolution of mobile communication technology has reached a pivotal stage with the introduction of 3GPP-5G, a standard that promises to transform wireless communications. In the realm of semiconductor IP, 3GPP-5G solutions encompass a wide range of technologies that are integral to developing and deploying next-generation communication networks. These semiconductor IPs provide the foundational architecture required for high-speed data transfer, ultra-reliable low latency, and massive connectivity, supporting the diverse and demanding use cases of modern mobile and IoT applications.
3GPP-5G semiconductor IP solutions are crucial for manufacturers and developers looking to design cutting-edge communication systems. These IPs enable the seamless integration of 5G capabilities into a variety of devices, from smartphones and smart home appliances to industrial IoT sensors and autonomous vehicles. They are designed to handle complex signal processing, support multiple frequency bands, and deliver enhanced performance metrics such as increased bandwidth and improved energy efficiency. By leveraging these semiconductor IPs, companies can significantly reduce time-to-market and development costs while ensuring that the end devices meet stringent 5G standards.
Within this category, you'll find a broad array of semiconductor IP products tailored to meet the specific challenges and opportunities posed by 5G networks. These include baseband processors, RF transceivers, and advanced modulation solutions, all of which are engineered to support the high demands of 5G technology. Furthermore, these IPs often come with software support and development kits that facilitate faster adoption and implementation into existing systems.
As the world moves towards more interconnected and intelligent systems, 3GPP-5G semiconductor IPs provide the essential building blocks for future innovations. By enabling the next generation of wireless communication, these IPs not only enhance current technologies but also pave the way for new applications and services that were previously unimaginable. Whether you are developing solutions for consumer electronics, automotive, healthcare, or smart cities, the 3GPP-5G semiconductor IP category offers the tools and technologies to bring your vision to life.
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
Systems4Silicon's Digital PreDistortion (DPD) Solution is designed to significantly enhance the power efficiency of RF power amplifiers. This subsystem is complete and adaptive, providing a scalable solution that transcends the limitations typical of vendor-specific dependencies. On account of its universal compatibility, this IP core can be compiled for any ASIC or FPGA/SoC platform, serving as an all-encompassing solution suited for a diverse array of wireless communication systems such as 5G and multi-carrier setups. One of the standout features of the DPD technology is its capability to improve transmission bandwidth efficiently, offering scalability for bandwidths of up to 1 GHz or more. This positions the DPD solution as a forward-thinking technology, catering to modern demands for higher data rates and broader communication ranges. The adaptive nature of the solution ensures that it can modulate performance parameters in real-time, responding dynamically to varying operational conditions and system requirements, thereby maximizing amplifier efficiency across different setups. In operational terms, the DPD Solution is field-proven, reflecting its reliability and performance in real-world applications. It represents a versatile technology that integrates seamlessly with existing systems, delivering a robust enhancement to power amplifier efficiency while maintaining high compatibility with emerging communication standards. The flexibility of this technology makes it a vital asset in the infrastructure of contemporary wireless networks, ensuring smooth and efficient signal transmission.
The 802.11ah HaLow Transceiver is engineered to fulfill the demands of modern IoT applications, where low power consumption and extended range are critical. It aligns with the IEEE 802.11ah standard, commonly termed as Wi-Fi HaLow™, and offers exceptional flexibility for new generations of IoT and mobile devices.\n\nBoasting features like low noise direct conversion and integrated calibration for I/Q pathways, this transceiver supports multiple modulation bandwidths, including 1 MHz, 2 MHz, and up to 4 MHz. With its capabilities spanning significant frequency ranges, the design ensures stable connectivity with minimum latency and enhanced receiver sensitivity.\n\nOne of its strengths lies in extensibility, providing superb integration potential either as a part of a broader system-on-chip (SoC) or as a standalone communication module. Designed with minimal power draw, it also allows using external power amplifiers to enhance transmission power, aligning with diverse application needs such as asset tracking, building security, and broader sensor networks.
Polar coding, a relatively recent addition to the 5G NR suite of technologies, is embraced by AccelerComm through their unique design that facilitates higher degrees of parallel processing. This advancement ensures operational efficiency and minimizes resource usage, thereby improving system robustness and throughput in 5G NR control channels. By employing a patented architecture, Polar coding exhibits flexibility and scalability, key to supporting high-performance 5G requirements. The reduced burden on hardware resources enables it to deliver superior BLER performance, crucial for meeting the stringent demands of modern telecommunications standards. Delivering across a spectrum of platforms, whether hardware-based like ASIC and FPGA or software-driven, Polar coding maintains a high degree of integration ease. This allows rapid deployment and alignment with existing infrastructure, ensuring seamless communication and data integrity in a wide array of network scenarios.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
AccelerComm offers an innovative LDPC solution specifically for 5G NR systems, pushing the boundaries of performance with its advanced block-parallel and row-parallel architectures. This sophisticated solution enhances data channel performance by utilizing a combination of scalability, high throughput, and low latency to maintain optimal communication systems. The LDPC solution effectively addresses standard 5G data channels, achieving substantive gains in resource utilization efficiency. By improving the already stringent latency specifications to support numerology 4, the solution ensures comprehensive code and transport block processing capabilities. It also upholds IEEE standards, providing a compliant pathway for high reliability and operational efficiency. Designed for integration across multiple platforms, including ASIC, FPGA, and software form factors, LDPC’s flexibility allows for deployment in a range of network conditions. Its open standard software interfaces make it easily adaptable, presenting a robust and versatile framework for companies to enhance their 5G network communication protocols with minimal effort.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The mmWave PLL is meticulously designed to cater to applications that operate in the millimeter-wave frequency bands, delivering high frequency stability and low phase noise. This innovative product serves as a critical component in RF systems, particularly where high-frequency signals are required. Fantastically well-suited for cutting-edge wireless communication applications and advanced radar systems, the mmWave PLL's architecture supports frequencies up to 110 GHz. This provides a robust solution that enhances signal integrity and performance in complex communication systems. Versatile and adaptable, the mmWave PLL advances the capabilities of mmWave technology, making it indispensable for industries seeking to push the boundaries of data transmission and signal processing.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
eSi-Comms offers highly parametric communication solutions tailored for complex projects. It encompasses a range of communication protocols and standards, ensuring seamless integration and high performance. This solutions package is ideal for optimizations across telecommunications systems, supporting a variety of communication needs.
The pPLL08 Family represents Perceptia's suite of all-digital RF frequency synthesizer PLLs designed for high-frequency applications, such as 5G and WiFi. With frequencies reaching up to 8GHz and jitter below 300fs RMS, this PLL family is ideal for both RF LO clocks and the clocking of ADCs/DACs in rigorous RF environments. Featuring a compact architecture, these PLLs are built with a LC tank DCO to meet stringent performance specifications. Flexibility is a hallmark of this IP; it allows for seamless integration across various SoC designs, supported by robust performance across multiple foundry process nodes from 5nm to 40nm.
The RWM6050 Baseband Modem is engineered to facilitate high-data rate applications across wireless communication networks. Designed to serve as a versatile component within various telecommunication systems, it processes signals with precision to enhance data throughput across diverse transmission environments. At its core, the RWM6050 is optimized for operation in complex wireless networks where bandwidth efficiency and robust signal integrity are paramount. It seamlessly integrates into wireless communication frameworks, providing the needed flexibility and scalability to support next-generation network deployments. Through its advanced capabilities, this baseband modem establishes itself as a pivotal element in ensuring reliable, high-speed data transmission. Whether supporting conventional networks or cutting-edge mmWave technology applications, the RWM6050 maintains stellar performance, thereby enhancing the efficiency of communication infrastructures in both commercial and defence sectors.
LightningBlu is designed specifically to transform the connectivity landscape of high-speed rail by providing uninterrupted, on-the-move multi-gigabit connectivity. By bridging the gap between trackside infrastructure and the train, it offers onboard services such as internet access, entertainment, and passenger information. Operating within the mmWave range, LightningBlu ensures a seamless communication experience even at high speeds, significantly enhancing the onboard experience for passengers. Integrating robust mmWave technology, the solution supports high data throughput, ensuring passengers can enjoy swift internet access and other online services while traveling. This wireless solution eliminates the need for traditional wired networks, reducing complexities and enhancing operational flexibility. With a profound ability to support high-speed data-intensive applications, LightningBlu sets a new benchmark in transportation connectivity. This platform's design facilitates smooth operation at velocities exceeding 300 km/h; coupled with its ability to maintain service over several kilometers, it is a critical component in advancing modern rail systems. LightningBlu not only meets today’s connectivity demands but also future-proofs the necessities of tomorrow's rail network implementations.
The 802.11 LDPC is a high-throughput solution designed for efficient wireless communication. This product supports frame-to-frame, on-the-fly configurations, offering flexibility in decoding iterations to balance throughput and error correction. It is engineered to conform to necessary performance specifications, ensuring optimal bit-error-rate and packet-error-rate performance in wireless networks. Functionality-wise, the design excels in meeting demanding throughput requirements while maintaining superior error correction capabilities. By allowing flexible configuration of LDPC decoding iterations, the product empowers users to tailor performance based on specific needs. This flexibility is essential for networks requiring dynamic adaptation to changing conditions or varying environmental factors. Technically, the 802.11 LDPC is crafted to integrate seamlessly into existing communication infrastructures, providing robust support for maintaining high data rates even under challenging conditions. Its unique ability to balance performance and energy efficiency makes it a preferred choice for modern wireless applications, strengthening connectivity reliability across multiple devices and environments.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The PCS2100 is a cutting-edge modem chip, specifically designed to facilitate the deployment of Wi-Fi HaLow networks, an extension of the Wi-Fi standard that enhances IoT connectivity. Based on the IEEE 802.11ah norm, this chip caters primarily to IoT devices, functioning proficiently within a network spearheaded by the PCS2500 access point. Its strength lies in its ability to operate over sub-gigahertz frequencies, offering extended transmission range that reaches over one kilometer.\n\nIncorporating innovative network management functions tailored for IoT, the PCS2100 ensures a robust and scalable connection with low power consumption, essential for densely packed IoT scenarios. The chip supports modulation schemes that enhance its capacity to manage receiver sensitivity and correct phase noise, contributing to its efficient transmission and reception.\n\nFocused on extending battery life while ensuring consistent IoT connectivity, features such as resource allocation windowing and target wake time optimize the network's power usage. This makes the PCS2100 an ideal candidate for long-term operational devices like sensors, providing extended communication life cycles while maintaining high data throughput.
UWB Technology & IP features advanced ultra-wideband solutions designed for precision connectivity in short-range communications. Offering high data efficiency and robust interference resistance, UWB is ideal for applications such as indoor positioning and short-range radar. TES's UWB technology is designed to seamlessly integrate into various systems, enhancing connectivity and interaction in complex network environments.
AccelerComm's Software-Defined High PHY is a malleable solution, catered to the ARM processor framework, capable of fulfilling the diverse requirements of modern telecommunications infrastructures. This technology is renowned for its optimization capabilities, functioning either with or without hardware acceleration, contingent on the exigencies of the target application with regards to power and capacity. The implementation of Software-Defined High PHY signifies a leap in configuring PHY layers, facilitating adaptation to varying performance and efficiency mandates of different hardware platforms. The technology supports seamless transitions across platforms, making it applicable for a spectrum of use cases, harmonizing with both flexible software protocols and established hardware standards. By uniting traditional hardware PHY layers with modern software innovations, this solution propels network performance while reducing latency, enhancing data throughput, and minimizing overall system power consumption. This adaptability is vital for enterprises aiming to meet the dynamic demands for quality and reliability in wireless communication network setups.
The Complete 5G NR Physical Layer solution by AccelerComm is designed to provide exceptional performance for demanding applications in O-RAN and satellite networks. This all-encompassing solution integrates high-accuracy signal processing technology, ensuring optimal link performance and efficient power usage. The physical layer is inherently flexible, allowing performance optimizations tailored to meet specific requirements of specialized network applications. This solution navigates the complex real-world dynamics involved in high-performance network scenarios, including both terrestrial and space-based communications. By leveraging advanced algorithms and architectures, the 5G physical layer supports customizable configurations, leading to power and area efficiency improvements. Through interoperability with multiple hardware platforms, it maximizes the performance of 5G networks, enhancing the user experience by minimizing latency and maximizing throughput. Delivered as openly-licensable intellectual property, the 5G NR Physical Layer can function across a wide range of platforms, such as ARM software and FPGA, ensuring broad compatibility. This strategic approach facilitates quicker project advancements through seamless integration and testing processes on multiple development boards, thereby reducing project risks effectively.
The WiFi6, LTE, and 5G front-end module is a cutting-edge solution for next-generation wireless communications, designed to operate effectively across multiple frequency bands, including 2.4 GHz and 5-7 GHz. This module integrates components such as the LNA (Low Noise Amplifier), PA (Power Amplifier), and RF switch to provide seamless connectivity for modern wireless devices. This front-end module is engineered to support high-speed data transmission and low latency, vital for applications ranging from mobile devices to advanced cellular infrastructure. Its design also emphasizes energy efficiency and clear signal amplification, ensuring robust performance in densely populated radio environments. With compatibility for WiFi6, LTE, and 5G technologies, this module plays a significant role in enhancing mobile and fixed communications. The focus on multi-standard support ensures that devices remain future-proof and efficient, handling increased data demands and improving user experiences in both consumer and industrial applications.
ParkerVision's Energy Sampling Technology is a state-of-the-art solution in RF receiver design. It focuses on achieving high sensitivity and dynamic range by implementing energy sampling techniques. This technology is critical for modern wireless communication systems, allowing devices to maintain optimal signal reception while consuming less power. Its advanced sampling methods enable superior performance in diverse applications, making it a preferred choice for enabling efficient wireless connectivity. The energy sampling technology is rooted in ParkerVision's expertise in matched filter concepts. By applying these concepts, the technology enhances the modulation flexibility of RF systems, thereby expanding its utility across a wide range of wireless devices. This capability not only supports devices in maintaining consistent connectivity but also extends their battery life due to its low energy requirements. Overall, ParkerVision's energy sampling technology is a testament to their innovative approach in RF solutions. It stands as an integral part of their portfolio, addressing the industry's demand for high-performance and energy-efficient wireless technology solutions.
Crest Factor Reduction (CFR) Technology by Systems4Silicon is engineered to optimize the efficiency of power amplifiers by managing the transmit signal envelope with precision. This technology is standard-agnostic, giving it a unique flexibility that supports its deployment across a wide range of platforms without being restricted by particular vendor protocols. Such independence ensures its utility in both ASIC and FPGA/SoC contexts, thus widening its applicability in modern communication infrastructures. At its core, the FlexCFR technology allows for a controlled reduction in the peak-to-average power ratio of the transmitted signals, effectively enhancing the performance of radio power amplifiers. This improvement in performance translates to an increase in energy efficiency, crucial for sustaining the growing demands on wireless infrastructure brought about by next-generation wireless standards like 5G. By reducing the crest factor, this technology ensures amplifiers can operate at their optimal efficiency levels, safeguarding the consistency and quality of signal transmission. The integration of CFR Technology within systems contributes to an overall enhanced power amplifier efficiency, aligning with the needs of various communication standards without necessitating bespoke adaptations. The field-proven applicability of this IP core underscores its reliability and performance in enhancing amplifier efficiency, ensuring clearer, more robust radio transmissions. This adaptability is critical for clients seeking to streamline operations while ensuring a future-proof setup ready for evolving communication technologies.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
Tower Semiconductor's RF-SOI and RF-CMOS platforms are tailored for cutting-edge wireless communication systems. These technologies cater to the burgeoning need for high-speed and high-performance RF solutions essential for modern telecommunications and mobile platforms. RF-SOI technology offers exceptional isolation and integration capabilities, significantly boosting performance in RF front-end modules. It's particularly optimal for devices operating in multi-band and carrier aggregation situations, ensuring seamless connectivity and data integrity. On the other hand, the RF-CMOS platform leverages CMOS processes to achieve cost-effective solutions while maintaining high RF performance levels, ideal for mass-produced consumer electronics. The combination of SOI and CMOS processes leads to advanced flexibility and improved yield, supporting the stringent requirements of mobile workloads. These technologies empower the development of compact, power-efficient, and high-performance wireless communication devices, positioning them well ahead in the fast-evolving telecommunications landscape.
The FCM3801-BD is designed for those requiring 39GHz CMOS Power Amplification within the 5G mmWave range. It supports frequencies from 32 to 44 GHz, featuring a 19 dB gain and a Psat of 18.34 dBm. With a PAE of 45%, this amplifier is engineered for high-power applications where efficiency and thermal management are crucial. It's particularly suited for modern telecom environments requiring minimal energy use and weight savings.
The RFicient chip is crafted to transform the Internet of Things (IoT) by delivering unprecedented energy efficiency. It is engineered to power sustainable IoT applications, minimizing energy consumption to nearly negligible levels. Utilizing this technology, devices can operate over extended periods without the need for frequent battery replacements or extensive power sources. Equipped with advanced RF capabilities, this chip is tailored for long-range connectivity, enabling devices to communicate across vast distances seamlessly. It is suited for deployment in varied environments, ensuring robust performance even in shifting conditions. The innovation behind this chip lies in its integration of cutting-edge circuit design which maintains low power usage while maximizing performance. RFicient's potential extends far beyond simple connectivity. It supports IoT devices with minimal energy resources, proving critical in domains where maintenance accessibility is limited. Its adaptive technologies can foster new IoT applications, paving the way for a future where technology adapts intuitively to the needs of diverse sectors and environments.
The PCS1100 is a versatile RF transceiver chip designed to facilitate Wi-Fi 6E networks, leveraging the IEEE 802.11ax specification. This sophisticated module operates within the RF domain, acting as the RF component of a Wi-Fi 6/6E access point or station, offering multi-band support including 6GHz Wi-Fi. It excels as a companion chip to a host controller, enabling seamless MAC and baseband digital operations for Wi-Fi 6/6E.\n\nNotable for its multi-user MIMO and dual-band concurrent capabilities, the PCS1100 efficiently handles multiple spatial streams, thereby optimizing network performance. It supports advanced modulation schemes up to 1024-QAM, promising robust connectivity even in congested environments. Its power-optimized design ensures efficient operation, minimizing the energy footprint while maximizing throughput.\n\nDeveloped with advanced RF engineering practices, the PCS1100 features an analog I/Q interface and components necessary for consistent calibration and signal path compensation. Its design guarantees adaptability and reliability across varying conditions, making it an ideal choice for high-density environments like smart cities, universities, and industrial applications.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
The Complete RF Transceiver designed for frequencies 433, 868, and 915 MHz is compliant with IEEE 802.15.4-2015. This solution is versatile, suiting applications requiring robust RF communication over these specific frequency bands. The transceiver is engineered to facilitate data rates accommodating 1.2 kbps to 500 kbps, allowing excellent adaptability in various systems. Its support extends to GFSK, BPSK, and O-QPSK modulation techniques, enhancing compatibility across different implementations. A vital feature of this transceiver is its comprehensive design, integrating PLL and RF front-end components. This high level of integration simplifies system design by removing the need for external RF components. Its performance is further exemplified by a TX power range from -20 to +8 dBm, ensuring significant transmission capability while maintaining efficient power use. This makes it ideal for long-distance communication without the complexities often associated with higher frequency bands and complex protocols. Further enhancing its versatility, the transceiver IP includes built-in voltage regulators and a bandgap reference, optimizing integration into various system-on-chip (SoC) architectures. These features are crucial for companies seeking to create wireless systems with minimal external dependencies, ensuring efficient use of space and resources on silicon. This makes it a preferable choice for global deployment where robust RF performance is a priority.
The PUSCH Equalizer by AccelerComm aims to improve the spectral efficiency of systems operating with multiple antennas, focusing on eliminating noise and interference through sophisticated signal processing. It's an essential feature for uplink communications, making it a perfect fit for next-generation 5G networks where performance integrity is crucial. Built upon advanced equalization algorithms, this solution integrates harmoniously with existing PUSCH Decoder units, seamlessly supporting Universal Communication Identifier (UCI) over PUSCH with the addition of an Equalizer block. It excels in enhancing spectral efficiency in various deployment scenarios by seamlessly incorporating equalization, demodulation, LDPC, and polar decoding functions. The PUSCH Equalizer is known for providing significant cost-efficiency and power reduction per bit processed. It’s available for both FPGA and ASIC platforms, meeting varied application requirements for interoperability and minimizing time-to-market timelines—ideal for enterprises keen on reducing deployment and operational costs while maximizing network performance.
Cobalt is a cutting-edge GNSS receiver that is expertly designed to offer ultra-low-power functionality, specifically tailored to IoT Systems-on-Chip. It is engineered to extend the market potential of IoT devices by integrating essential GNSS capabilities into modem SoCs. This not only conserves energy but also ensures that devices maintain compact sizes, essential for applications sensitive to size constraints and energy efficiency. Cobalt features a software-defined receiver capable of supporting major constellations such as Galileo, GPS, and Beidou, ensuring a broad reach and reliable performance in varied environments. Its standalone and cloud-assisted positioning functions optimize power usage, allowing for enhanced sensitivity and finer accuracy even in challenging conditions. Developed in collaboration with CEVA DSP and backed by the European Space Program Agency, Cobalt incorporates advanced processing techniques that improve resistance to multi-path interference and enhance modulation rates. This ensures that IoT devices utilizing Cobalt are equipped with state-of-the-art geolocation services, vital for sectors like logistics, agriculture, and mobility solutions.
The FCM2801-BD is a 28GHz CMOS Power Amplifier, specifically designed for applications in the 5G mmWave spectrum. It operates across a frequency range of 23 to 36 GHz and delivers a gain of 22 dB with a Psat of 19.55 dBm. Boasting a PAE of 53%, this amplifier suits high-frequency telecommunications, offering improved range and reduced energy consumption. The design minimizes thermal output, which further aids in reducing system maintenance costs.
PhantomBlu is a milestone in tactical communications, providing high-performance, data-rich connectivity solutions tailored for defence environments. Delivering on-the-move gigabit connectivity capabilities, it is designed to support demanding applications in mission-critical scenarios. With independently configurable options as PCP (hub) or STA (client), this solution excels in providing high-speed tactical communications over extensive ranges, making it indispensable in strategic defence operations. The platform leverages Blu Wireless’s advanced mmWave technology to ensure low SWAP (size, weight, and power) features, crucial for mobile and portable military applications. This adaptability and lack of reliance on cabled networks ensure PhantomBlu is not only agile but also highly effective across diverse operational environments. Through meticulous design, PhantomBlu supports interoperability with existing and future military assets, thereby extending the life and usability of defence communications infrastructure. By enabling high-bandwidth networks and low-latency communications, it stands as a cornerstone for modern defence strategies, allowing rapid data exchange vital for decision-making in fast-evolving tactical circumstances.
The Convolutional Encoder and Viterbi Decoder IPs provide a comprehensive solution for forward error correction, essential in ensuring data integrity within communication systems. This IP core supports a wide array of polynomial configurations, adapting to specific project requirements, thus ensuring flexibility for various applications. Engineered for high-performance environments, this encoder and decoder combination is designed to integrate seamlessly within FPGA or processor-based systems. Its ability to process data efficiently with minimal error rates makes it indispensable for applications requiring high reliability and accuracy, such as mobile and satellite communications. The Viterbi Decoder facilitates the decoding of convolutional codes, allowing for error correction post data transmission, a critical function in maintaining data fidelity across noisy channels. By leveraging this IP core, engineers can achieve low bit error rates while optimizing their system's coding gain, therefore maximizing communication efficiency.
The NB-IoT (LTE Cat NB1) Transceiver is a versatile module built to adhere to the 3GPP Release 13 standard, with additional capability for Release 14 compliance. Its design offers high performance for both transmitter and receiver functions, meeting stringent 3GPP specifications with margin for enhanced reliability.\n\nOperating predominantly within cellular bands, the transceiver utilizes a low-power profile to ensure efficiency, offering analog interfaces for straightforward integration and testing. Its programmability via an SPI interface makes it suitable for a wide range of applications and testing environments.\n\nEngineered to interface effortlessly with baseband and MAC layers, this transceiver is an optimal solution for IoT implementations where long battery life and reliable connection quality are paramount. The NB-IoT module provides the necessary signal control for correcting DC offsets, ensuring consistent performance and facilitating integration across various IoT applications.
The PCS2500 is a sophisticated access point system-on-chip designed for Wi-Fi HaLow networks, enabling a robust IoT ecosystem in accordance with the IEEE 802.11ah standard. It serves as a central hub managing communication between multiple PCS2100 client devices, using sub-gigahertz frequencies to cover extensive areas up to one kilometer. As an IoT internet gateway, the PCS2500 excels in managing dense networks with efficient resource allocation.\n\nEnsuring reliable and extended connectivity for IoT devices, this access point features various innovations to manage power consumption effectively, such as resource allocation windows (RAW) and target wake time (TWT). These features allow for orderly network access and reduce device contention, optimizing throughput and conserving energy.\n\nHigh receiver sensitivity and optimized transmission features make the PCS2500 a cornerstone in IoT networking, especially in applications requiring wide coverage and long-term battery life for connected devices like sensors. Its integration capability allows seamless interaction with existing network infrastructures, facilitating easy implementation and management.
The LDPC Decoder for 5G NR by Mobiveil is crafted to ensure seamless decoding within modern cellular networks. Incorporating the Min-Sum decoding algorithm, it ensures optimal performance while reducing power consumption and silicon area usage. This decoder is equipped with programmable bit widths, allowing for tailored configurations to suit specific application requirements during the compile phase. The inclusion of an early iteration termination feature, driven by an integrated parity check engine, supports efficiency by enabling preemptive exits during iterative processes. By accommodating retries with hybrid automatic repeat requests (HARQ), the decoder maintains robustness across various transmission conditions. This adaptability makes it an invaluable component for 5G networks, where data integrity and fast processing are paramount.
Engineered for modern wireless networking needs, the Wi-Fi 6 IP is fully compliant with the 802.11ax protocol, ensuring backward compatibility with previous iterations such as Wi-Fi 4 and 5. This IP delivers augmented bandwidth and improved network performance, making it the ideal choice for high-density environments demanding effective network communication. Tailored for seamless integration in smart devices, this IP underscores reliability with reduced latency and enhanced connection speeds.
ARDSoC introduces Data Plane Development Kit (DPDK) capabilities to the ARM-based System on Chip (SoC) domain, bypassing the traditional Linux network stack to save valuable ARM processor cycles. Designed specifically for embedded MPSoC environments, ARDSoC streamlines the transition of existing DPDK programs with minimal adjustments, bringing powerful data manipulation capabilities to devices with ARM architecture. This solution is particularly beneficial in reducing the power, latency, and total cost of ownership for applications transitioning from x86 frameworks to ARM structures. ARDSoC provides a zero-copy memory structure enhancing cache performance, along with an optimized Poll Mode Driver (PMD) that ensures minimal latency by maintaining data proximity to processing nodes. Notably, it harmonizes with a range of applications, from embedded protocol bridges to cloud-edge networks that demand robust packet processing. Among its many features, ARDSoC enables seamless packet vector and container-aware processing, supporting various platforms like VPP and Kubernetes. Compatible with Xilinx platforms, ARDSoC facilitates swift integration and testing, allowing developers to leverage the inherent flexibility and performance advantages in diverse networking and cloud computing scenarios.
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems, so a powerful FEC code is needed. The New Radio (NR) FEC for the control channel is designed based on Polar codes, allowing close to the Shannon limit/Capacity operation. It features Polar code successive cancellation decoding, as needed for the 3GPP physical layer standard, with Parity Check bits that simplify the pruning of the search tree. The encoding of the NR Polar code is performed in GF(2), structured using static reliabilities from the ETSI standard. This IP Core supports a maximum code block length of 1024 bits and a minimum of 32 bits. It can be easily integrated with interleavers and Rate matching circuitry to support all rates required by 5G NR. Additional features include successive cancellation decoding with list decoding, soft decision decoding, high peak rates, low latency, and compliance with the 3GPP TS 38.212 V15.1.1 standard. The IP Core is suitable for applications such as 3GPP-LTE Rel. 15 control channels, 5G NR air interfaces, machine-to-machine communication, and high traffic IoT.
Crest Factor Reduction (CFR) is a fundamental technology in the design of Power Amplifiers, aimed at alleviating the stringent power supply design requirements. CFR reduces the peak power demand on the amplifiers by lowering the peaks in the signal without significantly compromising the signal quality. This process results in a more efficient operation of the amplifier, minimizing power dissipation and improving overall system performance. By smoothing out the peaks, Crest Factor Reduction enables higher average power output without tripping the amplifier into distortion zones, thereby optimizing the use of available power resources. This aspect of amplifier design is vital for maintaining system integrity and extending the operational life of electronic components in dynamic RF environments. CFR technology finds its vital application in telecommunications, where it helps in managing peak-to-average power ratios efficiently. By ensuring that power amplifiers operate within optimal parameters, CFR contributes to energy conservation and operational reliability, making it indispensable in modern telecommunications infrastructure.
Creonic's Turbo encoders and decoders are meticulously designed to support error correction in both satellite and terrestrial communication applications. The turbo coding process enhances data reliability and efficiency, making it indispensable in digital communication systems where bandwidth and power efficiency are paramount. These IP cores are aligned with leading standards such as DVB-RCS2 and LTE, ensuring they meet the rigorous demands of high-performance systems. The Turbo technology employed by Creonic optimizes for high throughput while maintaining low error rates, making these IP cores vital for communication networks where performance consistency is critical. Commercial and military users alike benefit from the robust error correction capabilities these encoders and decoders provide, as they improve signal reliability over varying transmission conditions. This consistent reliability translates to a reduction in retransmissions and improved overall communication efficiency. Moreover, the flexibility and configurability of Creonic's Turbo IP cores allow for tailored solutions across different platforms, including both FPGA and ASIC. This adaptability ensures that the cores can be embedded effectively across a variety of hardware architectures, thereby broadening the scope of applications they can support.
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