All IPs > Security IP > Platform Security
In today's digital world, the importance of platform security cannot be overstated. Platform security semiconductor IPs are essential for protecting electronic systems from an increasing array of threats. These IPs play a critical role in ensuring that systems remain secure by safeguarding data, communications, and applications from unauthorized access or malicious attacks.
Platform security IPs include a variety of solutions such as encryption engines, secure boot mechanisms, and trusted execution environments. These technologies work in harmony to validate the authenticity of hardware and software components, providing a comprehensive security framework for electronic devices. By integrating these security measures at a fundamental level, semiconductor IPs ensure that systems are resilient to tampering and meet stringent security standards.
The applications of platform security semiconductor IPs span across a multitude of industries. From consumer electronics like smartphones and smart home devices to critical infrastructure systems and automotive applications, robust security is imperative. These IPs are designed to address the security needs of both edge devices and cloud-based platforms, preserving the integrity and confidentiality of sensitive data as it is processed and transmitted.
In our Silicon Hub, you will find a diverse array of platform security semiconductor IPs tailored to meet varied security requirements. Whether you're looking to protect consumer devices or safeguard enterprise data centers, our cutting-edge IP solutions provide the reliability and flexibility needed to counteract evolving security threats. Explore our category to enhance your products with state-of-the-art security technologies.
The Akida Neural Processor IP by BrainChip is a versatile AI solution that melds neural processing capabilities with scalable digital architecture, delivering high performance with minimal power consumption. At its core, this processor is engineered using principles from neuromorphic computing to address the demands of AI workloads with precision and speed. By enabling efficient computations with sparse data, the Akida Neural Processor optimizes sparse data, weights, and activations, making it especially suitable for AI applications that demand real-time processing with low latency. It provides a flexible solution for implementing neural networks with varying complexities and is adaptable to a wide array of use cases from audio processing to visual recognition. The IP core’s configurable framework supports the execution of complex neural models on edge devices, effectively running sophisticated neural algorithms like Convolutional Neural Networks (CNNs) without the need for complementary computing resources. This standalone operation capability reduces dependency on external CPUs, driving down power consumption and liberating devices from constant network connections.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
KPIT Technologies offers comprehensive AUTOSAR solutions that are pivotal for the development of modern, adaptive automotive systems. Emphasizing middleware integration and E/E architecture transformation, their solutions simplify the complexities of implementing adaptive AUTOSAR platforms, enabling streamlined application development and expeditious vehicle deployment. With extensive experience in traditional and adaptive AUTOSAR ecosystems, KPIT assists OEMs in navigating the challenges associated with software-defined vehicles. Their expertise facilitates the separation of hardware and software components, which is crucial for the future of vehicle digital transformation. KPIT's middleware development capabilities enhance vehicle systems' robustness and scalability, allowing for seamless integration across various automotive applications and ensuring compliance with industry standards. By fostering strategic partnerships and investing in cutting-edge technology solutions, KPIT ensures that its clients can confidently transition to and maintain advanced AUTOSAR platforms. The company's commitment to innovation and excellence positions it as a trusted partner for automakers striving to stay ahead in the competitive automotive landscape by embracing the shift towards fully software-defined vehicles.
The Akida IP platform is a revolutionary neural processor inspired by the workings of the human brain to achieve unparalleled cognitive capabilities and energy efficiency. This self-contained neural processor utilizes a scalable architecture that can be configured from 1 to 128 nodes, each capable of supporting 128 MAC operations. It allows for the execution of complex neural network operations with minimal power and latency, making it ideal for edge AI applications in vision, audio, and sensor fusion. The Akida IP supports multiple data formats including 4-, 2-, and 1-bit weights and activations, enabling the seamless execution of various neural networks across multiple layers. Its convolutional and fully-connected neural processors can perform multi-layered executions independently of a host CPU, enhancing flexibility in diverse applications. Additionally, its event-based hardware acceleration significantly reduces computation and communication loads, preserving host CPU resources and optimizing overall system efficiency. Silicon-proven, the Akida platform provides a cost-effective and secure solution due to its on-chip learning capabilities, supporting one-shot and few-shot learning methods. By maintaining sensitive data on-chip, the system offers improved security and privacy. Its extensive configurability ensures adaptability for post-silicon applications, making Akida an intelligent and scalable choice for developers. It is especially suited for implementations that require real-time processing and sophisticated AI functionalities at the edge.
aiWare is engineered as a high-performance neural processing unit tailored for automotive AI applications, delivering exceptional power efficiency and computational capability across a broad spectrum of neural network tasks. Its design centers around achieving the utmost efficiency in AI inference, providing flexibility and scalability for various levels of autonomous driving, from basic L2 assistance systems to complex L4 self-driving operations. The aiWare architecture exemplifies leading-edge NPU efficiencies, reaching up to 98% across diverse neural network workloads like CNNs and RNNs, making it a premier choice for AI tasks in the automotive sector. It boasts an industry-leading 1024 TOPS capability, making it suitable for multi-sensor and multi-camera setups required by advanced autonomous vehicle systems. The NPU's hardware determinism aids in achieving high ISO 26262 ASIL B certification standards, ensuring it meets the rigorous safety specifications essential in automotive applications. Incorporating an easy-to-integrate RTL design and a comprehensive SDK, aiWare simplifies system integration and accelerates development timelines for automotive manufacturers. Its highly optimized dataflow and minimal external memory traffic significantly enhance system power economy, providing crucial benefits in reducing operational costs for deployed automotive AI solutions. Vibrant with efficiency, aiWare assures OEMs the capabilities needed to handle modern automotive workloads while maintaining minimal system constraints.
Polar ID is a groundbreaking biometric security solution designed for smartphones, providing a secure and convenient face unlock feature. Employing advanced meta-optic technology, Polar ID captures the polarization signature of a human face, offering an additional layer of security that easily identifies human tissue and foils sophisticated 3D mask attempts. This technology enables ultra-secure facial recognition in diverse environments, from daylight to complete darkness, without compromising on the user experience. Unlike traditional facial recognition systems, Polar ID operates using a simple, compact design that eliminates the need for multiple optical modules. Its unique capability to function in any lighting condition, including bright sunlight or total darkness, distinguishes it from conventional systems that struggle under such scenarios. Furthermore, the high resolution and precision of Polar ID ensure reliable performance even when users have their face partially obscured by sunglasses or masks. With its cost-effectiveness and small form factor, Polar ID is set to disrupt the mobile device market by making secure biometric authentication accessible to a broader range of smartphones, not just high-end models. By simplifying the integration of facial recognition technology, Polar ID empowers mobile devices to replace less secure, inconvenient fingerprint sensors, thus broadening the reach and applicability of facial biometrics in consumer electronics.
PUFrt stands as a flagship hardware root of trust solution, incorporating PUF technology to create a unique and unclonable UID directly on the chip. This ensures robust security from the ground up, offering features such as TRNG, secure OTP, and an attack-resistant shell. The architecture of PUFrt provides a resilient foundation for semiconductor devices, helping to mitigate reverse engineering and counterfeiting risks. It integrates seamlessly with various systems, offering a trusted base for lightweight hardware security keys and full-function security coprocessors.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
Securyzr iSSP is an advanced security lifecycle management solution, designed to offer seamless integration of security features throughout the device lifecycle. It provides a comprehensive platform for managing security tasks such as provisioning, firmware updates, security monitoring, and device identity management. The iSSP is built to facilitate zero-touch security lifecycle services, ensuring robust protection against potential cyber threats from chip to cloud. It stands out with its ability to handle post-quantum cryptography (PQC), making it future-ready and capable of addressing upcoming security challenges in an evolving digital landscape.
eSi-Crypto provides advanced features in encryption and authentication, offering an impressive suite of solutions including True Random Number Generators (TRNGs), cryptographic processing, and Public Key Acceleration. Engineered to optimize resource usage without compromising throughput, it is designed to secure devices effectively in various critical applications.
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
The Securyzr Key Management System offers a robust solution integrated into Secure-IC's security ecosystem to manage cryptographic keys effectively and securely. This system ensures that key generation, distribution, and storage processes are carried out in a highly secure manner, facilitating strong encryption and digital signature functions. Its integration into a wide range of devices guarantees secure communication and data handling across various applications, making it a critical component in safeguarding sensitive data.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
The RISC-V CPU IP NS Class by Nuclei is specifically aimed at sectors requiring enhanced security and financial technology solutions. Built upon a versatile architecture, it is pivotal for applications in IoT security and payment systems. This processor IP leverages the RISC-V standard to offer customizable configurations, optimized through its Verilog-based development, to enhance readability and effectiveness in debugging, contributing to superior PPA performance. Nuclei’s NS Class equips developers with flexible tools to adapt the processor to varied system requirements, making use of extensive RISC-V extensions and the opportunity for user-defined instructions. The IP’s security features are robust, featuring TEE support and a physical security package, ensuring complete security for sensitive data. Additionally, it complies with functional safety standards such as ASIL-B and ASIL-D, which are crucial in environments requiring stringent safety compliance. In essence, the NS Class stands out for its ability to secure and optimize financial transactions and data protection in IoT applications. Its flexibility in configuration and comprehensive security measures make it a reliable choice for demanding and sensitive technology applications.
TerraPoiNT from NextNav represents a groundbreaking advance in Position, Navigation, and Timing (PNT) systems by providing a resilient alternative to GPS. This system is particularly designed to function in environments where GPS is traditionally weak, such as indoors or urban areas. It delivers secure, fully encrypted signals resistant to spoofing and jamming. By relying on a network of terrestrial transmitters rather than satellite data alone, TerraPoiNT offers significantly stronger signal strength, providing a critical PNT solution capable of ensuring uninterrupted operational capability. NextNav’s TerraPoiNT system is built on an extensive network of low-cost broadcast beacons and integrates seamlessly with existing GPS/GNSS technologies for improved navigation accuracy. The system utilizes a frequency-flexible waveform and operates independently from communication networks, guaranteeing its independence and resilience. Moreover, the solution incorporates components like Timing as a Service (TaaS), vital for maintaining synchronized systems across industries requiring precise timing. The network is engineered to support various industry standards and has demonstrated superior performance metrics according to evaluations by the Department of Transportation. TerraPoiNT also includes cybersecurity measures to detect and mitigate GPS interference, making it a vital component for infrastructure protection. Its utility is further amplified by partnerships with major integrated circuit manufacturers, enhancing the applicability of NextNav’s technological innovations across industries like telecommunications and critical infrastructure.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
NeoPUF is a pioneering hardware security solution aimed at enhancing the protection of semiconductor devices. Leveraging physical unclonable function (PUF) technology, NeoPUF generates unique identifiers for each chip, providing an essential root of trust for secure applications. This capability is crucial in environments where robust data security is paramount, such as IoT, AI, and automotive sectors. Unlike traditional security measures that rely on stored keys, NeoPUF derives keys directly from the inherent physical characteristics of the silicon, making it resistant to cloning and reverse engineering. This approach ensures that each device can authenticate itself and safeguard sensitive information without exposing it to potential threats. Such a methodology significantly strengthens the overall security infrastructure of modern digital systems. NeoPUF not only facilitates secure communication but also aids in protecting intellectual property against piracy and counterfeiting. It is a versatile technology that integrates smoothly into existing systems and requires no additional hardware, minimizing costs while maximizing security. As security becomes an increasingly critical aspect of semiconductor design, NeoPUF stands out as a forward-thinking solution ready to meet the challenges of emerging technologies.
PUFhsm is an advanced embedded hardware security module designed for automotive and complex applications. It acts as an embedded security enclave, isolating key functions from the main system to ensure secure operations. With integrated cryptographic engines and dedicated CPUs, PUFhsm supports secure boot, updates, and key management within a compliant framework. It enhances designs by bolstering security while optimizing efficiency and reducing time-to-market.
The QDID PUF is an innovative hardware experience designed to generate a unique cryptographic identity through quantum tunneling current variations. Utilizing standard CMOS processes, it taps into randomness deriving from oxide thickness variations and defect distribution in gate oxide, creating a robust hardware root-of-trust. This enables the establishment of secure architectures by providing on-the-fly identity generation that does not rely on memory storage, making it resistant to side-channel and machine learning attacks. The QDID PUF is especially noteworthy for its high entropy seed generation, supporting customizable security strengths up to 256 bits, and is designed with built-in resistance against secret leakage through advanced countermeasures. The technology is thoroughly tested under diverse environmental conditions, consistently maintaining reliability and longevity, and has achieved extensive verification across major fabs including TSMC, GF, and UMC across various process nodes in Bulk CMOS, FDSOI, and FinFET technologies. It enables key generation and device authentication, serving as a cornerstone for secure provisioning and post-quantum cryptography, thus supporting various applications in device identification, supply chain security, and more. Successfully verified under NIST standards, QDID PUF ensures excellent performance across voltage, temperature, and ageing tests, offering a robust solution for future-proof IoT device integration.
Suite-Q SW is a versatile cryptographic software library offered by PQ Secure, tailored to optimize code size, stack usage, and performance for diverse device specifications. Available in both high-speed assembly and portable C code, it suits a variety of embedded processors ranging from 8-bit to 64-bit platforms. This software solution ensures that memory-constrained devices can still maintain robust security features without sacrificing critical system resources. Compatible with general-purpose and specialized CPUs, Suite-Q SW supports hardware offload, enhancing processing efficiency across different applications. Key functionalities include support for various symmetric and asymmetric cryptographic standards, aligning with global security protocols. Suite-Q SW offers customization options to balance speed and memory use, meeting specific performance criteria while providing thorough validation tests and performance metrics for seamless integration into existing systems.
ZIA SV represents a state-of-the-art stereo vision IP core geared towards precise distance measurement through stereo imaging, critical for applications involving autonomous navigation and distance sensing. By harnessing images from dual cameras, ZIA SV utilizes semi-global matching (SGM) algorithms to accurately estimate disparities and distances. The core is optimized through various pre- and post-processing techniques to enhance performance and precision. These processes include alignment, stereo rectification, sub-pixel interpolation, and disparity image denoising, ensuring unparalleled accuracy in distance estimation. Equipped with a scalable architecture, DMP’s ZIA SV supports integration with AMBA AXI4 interface, ensuring compatibility with numerous processor architectures. The versatility and precision of this IP make it suitable for use in robots and drones requiring advanced stereo vision capabilities.
The Platform-Level Interrupt Controller (PLIC) is a versatile and fully parameterized controller designed to manage interrupt signals in RISC-V platforms. It is compliant with the RISC-V standards, offering full customization to match various system needs, making it a critical component in managing complex interrupt schemes across different CPU environments. The PLIC ensures efficient handling of interrupts, optimizing both performance and resource utilization. With its flexible architecture, the PLIC can be tailored to fit a wide range of applications, enhancing its utility in diverse embedded systems. It supports multiple levels of interrupts, prioritization, and custom configurations, ensuring it can integrate seamlessly with other system components. The inclusion of this controller in a system design gives developers the tools needed to effectively manage interrupt processing, thus maintaining high system throughput and responsiveness.
Designed as a public key algorithm coprocessor, the FortiPKA-RISC-V stands out for its ability to streamline operations typically bogged down by Montgomery domain transformations. This component is tailored for high performance in embedded systems, ensuring enhanced data security through its advanced modular multiplication and robust protection against SCA and FIA. Particularly suited for secure System on Chip (SoC) integration, FortiPKA-RISC-V offers significant performance improvements without increasing area constraints.
NeoFuse represents an advancement in anti-fuse OTP technology, offering robust data protection for semiconductor devices. Its unique design ensures that once programmed, the data in NeoFuse cannot be altered, making it ideal for applications requiring permanent data storage, such as security keys and hardware identifiers. The technology behind NeoFuse focuses on providing high reliability and data integrity. By utilizing innovative materials and processes, NeoFuse guarantees stable performance across extended periods, even under fluctuating environmental conditions. This ensures that the data remains secure and accessible throughout the device's lifecycle. NeoFuse seamlessly integrates into various technology nodes and is compatible with numerous fabrication processes. This flexibility allows it to serve a broad range of applications, from automotive systems that demand high-security measures to consumer electronics requiring efficient space utilization. With its focus on preventing unauthorized data manipulation, NeoFuse is a pivotal component for protecting sensitive information in today’s digital age.
The RISC-V CPU IP NA Class from Nuclei is purpose-built for the automotive industry, focusing on ISO26262 FuSa standards to ensure functional safety. This processor IP is designed with automotive-specific features and flexibility, employing a 64-bit architecture to handle complex computations necessary in advanced driver assistance systems (ADAS) and other automotive applications. Developed using Verilog, the NA Class prioritizes readability, which aids in debugging and optimizing performance, power efficiency, and area measurements. With substantial configurability, the NA Class allows for integration in a wide range of systems by leveraging RISC-V extensions and user-defined instruction capabilities. Its comprehensive security suite, including TEE support and physical security packages, ensures the integrity and protection of automotive systems from cyber-threats. Furthermore, the NA Class is aligned with ASIL-B and ASIL-D safety protocols, providing the necessary assurance for automotive safety and reliability standards. In conclusion, Nuclei's NA Class is set to meet the high demands of automotive applications requiring safety and security. It offers robust features that address the specific needs of the automotive scene, showcasing Nuclei’s dedication to innovation and safety in the automotive sector.
Suite-Q HW is a comprehensive system-on-chip (SoC) design by PQ Secure that integrates all necessary cryptographic components for secure protocols. Targeted at both high-end servers and low-end embedded systems, Suite-Q HW offers versatile hardware accelerators capable of conducting symmetric and asymmetric cryptographic operations efficiently. Key features of this hardware include a NIST 800-90-compliant true random number generator (TRNG), support for a variety of elliptic curve cryptographies, and capabilities for post-quantum cryptography operations such as isogeny-based and lattice-based cryptographies. It also supports traditional algorithms like AES and SHA, ensuring compatibility with established security protocols. Suite-Q HW is engineered to offload heavy cryptographic computations, reducing system demands while providing substantial power savings over software implementations. This makes it ideal for applications requiring high security and efficiency, such as in IoT devices where power consumption is a critical concern. Enhanced by optional DPA countermeasures, it provides robust security in a compact and efficient package.
The Integrated Secure Element (iSE) is a cornerstone in Secure-IC’s security offerings, providing a root of trust embedded within the main System-on-Chip (SoC). It delivers multiple essential services to the host system, including secure boot, key isolation, and anti-tamper protection. Tailored to ensure maintenance of system integrity and confidentiality, the iSE acts as a resilient line of defense against sophisticated attacks, maintaining the secure execution of applications and safeguarding the integrity of sensitive data.
The SHA-3 Crypto Engine is a robust hardware accelerator specifically designed for cryptographic hashing functions. It presents a balance of high throughput and area efficiency and aligns with the FIPS 202 standards set by NIST. This engine supports all SHA-3 hash functions, including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512, as well as SHAKE-128 and SHAKE-256. Built to mitigate security vulnerabilities, it provides comprehensive defense against time-based side-channel attacks, ensuring data integrity. Operating within a single clock domain, the SHA-3 Crypto Engine is adequately verified, boasting automatic byte padding and effortless integration into existing systems. Its versatility spans numerous applications ranging from Message Authentication Codes (MACs) to protocol engines like IPsec and TLS/SSL, alongside secure boot engines and encrypted data storage solutions. Through integrating this engine, clients can guarantee the integrity and security of financial transactions, e-commerce platforms, and even blockchain applications. Delivered in System Verilog RTL with supportive testbenches and integration examples, the SHA-3 Crypto Engine offers straightforward deployment while maintaining compliance with industry standards. Its resource utilization spans a variety of FPGA families such as AMD Spartan, Kintex-7, and AMD Zynq MPSoC, presenting adaptability and efficiency across diverse platforms.
The DSHA2-512 core specializes in the SHA2-512 hashing algorithm, providing a highly efficient means to process hashing functions in data-intensive environments. It is designed to comply with FIPS PUB 180-4 standards, ensuring that it meets established guidelines for secure hashing operations necessary in a variety of industry settings. With interfaces that include APB, AHB, and AXI, the DSHA2-512 exhibits broad compatibility with existing digital infrastructures, enabling it to be deployed across a wide array of technology solutions. This core is ideal for sectors where ensuring data integrity and authenticity is critical, such as finance, governmental, and secure communications sectors. Its enhanced technical capabilities mean that the DSHA2-512 core supports extensive data processing requirements while maintaining the security integrity of hashes, making it an essential component for applications that demand reliable hash computation and data security.
The Physically Unclonable Function (PUF) provides a hardware-based security feature that is essential in uniquely identifying devices. Enhancing security by generating a unique digital fingerprint for each device, the PUF ensures that these fingerprints are virtually impossible to replicate or clone. This functionality is pivotal in protecting sensitive information, particularly in applications where tamper-resistant identification is required. By leveraging intrinsic silicon variations, the PUF offers a high level of security while remaining efficient and low-power, becoming a critical component in the next-generation security solutions for IoT and other connected devices.
Comcores' MACsec solution addresses the needs for secure communication on Ethernet links by implementing the IEEE 802.1AE standard for MAC Security. It provides comprehensive protection against eavesdropping and manipulation, making it suitable for applications demanding high security over public and private networks. Built to support various data rates, the MACsec IP core integrates robust cryptographic suites like AES-GCM to encrypt and authenticate network traffic. Its deployment ensures data confidentiality and integrity, fostering a secure environment for transmitting sensitive information such as in military communication systems and data centers.
The DSHA2-256 core is a dedicated solution for hashing functions, specifically designed to excel in processing the SHA2-256 algorithm. Compliant with the FIPS PUB 180-4 standards, this universal core accelerates the hash operation, providing efficient and secure data processing options for diverse digital systems. Its architecture supports both APB, AHB, and AXI bus interfaces, allowing for easy integration into numerous applications that require robust hashing mechanisms. The core enhances processing capabilities, facilitating the rapid execution of secure hash functions that protect data integrity and authenticity. This IP core is invaluable in fields where data security and integrity are critical, such as banking, digital communication, and any networked environment where information verification is necessary. By providing dedicated hardware for hashing tasks, it ensures high levels of data protection and performance, making it an ideal choice for developers looking to implement reliable security solutions.
The Security Protocol Accelerator from PQ Secure is engineered to enhance the efficiency of cryptographic protocols by offloading computationally intensive processes onto a dedicated hardware unit. This approach not only speeds up operations but also reduces the load on primary processors, enhancing overall system performance. Supporting a broad range of cryptographic protocols, this accelerator is designed to integrate seamlessly with existing infrastructure, ensuring backward compatibility and operational efficiency. Its robust architecture allows it to support various established and emerging cryptographic standards, making it adaptable to both current and future security needs. Additionally, the Security Protocol Accelerator features built-in protections against advanced security threats, such as side-channel attacks, ensuring that data remains protected against evolving tactics used by attackers. The accelerator is a valuable addition to systems needing enhanced security measures alongside optimal performance.
The Keccak Hash Engine is renowned for its adaptability and capability, primarily recognized as a cryptographic hash function. Its core structure is based on a unique sponge construction featuring the Keccak-f cryptographic permutation, allowing for extensive customization in output length and security strength. This flexibility has secured its adoption in mobile telephony standards like 3GPP TS 35.231 and NIST standards, namely FIPS 202 and SP 800-185. Capable of executing hash functions and providing support for authentication, encryption, and pseudo-random number generation, the Keccak Hash Engine is a versatile asset in various cryptographic applications. Its design rests on simplicity and ease of integration, coupled with a single clock domain to ensure seamless deployment and operation across platforms. Due to its extensively verified code, the Keccak Hash Engine is dependable for applications demanding high security levels, like blockchain, random number generation, and authentication protocols. Available in System Verilog RTL, it is suitable for diverse industrial applications that demand robust cryptographic functions adaptable to evolving security needs.
The Cryptographic COEsec is integral to substation automation systems, offering advanced cryptographic solutions to secure communications and data integrity within electric utility networks. This core is designed to protect critical infrastructure components from unauthorized access and cyber threats, ensuring the secure operation of power grid systems. With increasingly stringent regulations governing data security, the COEsec core provides comprehensive cryptographic functions including encryption, decryption, and authentication tailored for the unique needs of substation environments. By integrating this core, utility companies can safeguard their network communications against tampering and interception, thereby maintaining the integrity and confidentiality of energy distribution processes. The COEsec core supports seamless integration into existing infrastructures, allowing for enhanced security without compromising on system performance. Its robust design ensures compatibility with industry standards, providing peace of mind to operators looking to secure their digital ecosystems from emerging cyber threats. This core is essential for future-proofing substation automation systems against the evolving landscape of cybersecurity challenges.
The iShield Key by Swissbit is a versatile security solution that integrates both digital and physical access controls, all in one device. It enables efficient authentication across a variety of IT systems, buildings, and secure printing facilities. Designed for ease of use, it acts as a universal security key that supports USB and NFC interfaces, enhancing its compatibility with various platforms. It’s built to provide robust protection for online accounts by securely navigating websites, applications, and corporate networks. Its hybrid functionality allows seamless integration into existing workflows, thus providing a comprehensive approach to security. With its compact form, the iShield Key remains a popular choice for secure access management in diverse environments.
This IP core offers advanced technology to resist side-channel attacks, crucial for maintaining the integrity and confidentiality of sensitive data. It is specifically engineered to withstand efforts to extract cryptographic keys via analysis of physical emanations from hardware devices. The side-channel attack resistance feature of this product ensures that it can be deployed in environments where data protection is paramount, such as in financial systems and secure communications.
Aimed at mitigating the risk of fault injection attacks, this IP employs sophisticated strategies to maintain security integrity under extreme conditions. It uses error-detection and correction techniques to prevent unauthorized manipulations that could otherwise lead to unauthorized access. The IP is designed to be robust against fault conditions induced by attackers using methods like voltage manipulation and clock glitching. Its deployment is vital in secure environments where data integrity is non-negotiable.
The DSHA2-384 core is optimized for executing the SHA2-384 hash function, ensuring secure and efficient handling of hashing operations within digital systems. It fully complies with FIPS PUB 180-4 standards, ensuring adherence to widely recognized security protocols and making it ideal for industries that demand high standards of data protection. This IP core supports a variety of bus interfaces including APB, AHB, and AXI, providing compatibility with a broad range of system architectures. Its advanced security features enhance hashing processes, enabling rapid and secure management of data in applications that range from financial transactions to complex data security implementations. For security-focused applications, the DSHA2-384 core offers unmatched reliability and performance. It suits environments where data integrity is paramount, supporting industries that need robust digital security measures. The core facilitates secure communications and encrypted storage, making it a vital tool for safeguarding sensitive information in a digital-first world.
FortiMac offers a secure implementation of HMAC SHA2, aimed at providing strong resistance to side-channel and fault injection attacks. Utilizing the Threshold Implementation paradigm ensures its ability to protect critical applications, both in software and hardware deployments. FortiMac's market distinction lies in its unique capability of employing only a minimal number of standard digital gates, while concurrently offering robust security for SCA and FIA threats.
The CCSDS LDPC (8160, 7136) IP is a meticulously crafted Low-Density Parity-Check encoder and decoder tailored for space communication standards. The Consultative Committee for Space Data Systems (CCSDS) has specified these LDPC codes to enhance data integrity and reliability for space missions where error-free transmission is crucial. This IP core offers significant improvements in error correction performance, making it ideal for deep space and near-Earth missions requiring high data throughput and reliability. The use of LDPC coding provides a significant advantage over traditional error correction methods, enabling efficient data recovery even under challenging conditions. Designed for FPGA implementation, the IP can be seamlessly integrated into space communication systems, offering reliable performance and ensuring compliance with CCSDS standards. Its efficient use of resources makes it a preferred choice for space agencies looking to maximize mission success.
The KiviPQC-KEM is an advanced cryptographic solution developed for the post-quantum era, designed to support all ML-KEM variants standardized under NIST's FIPS 203. This IP core performs key operations necessary for key generation, encapsulation, and decapsulation, ensuring robust defenses against quantum computer attacks. The engine is a central asset in post-quantum cryptography, facilitating secure secret key establishment over public channels. Targeted for integration within ASIC and FPGA systems, the KiviPQC-KEM distinguishes itself with its minimalistic logic utilization and efficient resource management. It incorporates hardware acceleration to bolster performance during computationally intense tasks, bridging the gap between security needs and computational capabilities. KiviPQC-KEM is encapsulated as a standalone unit, allowing easy integration without extensive resources. Applications for this core cover a broad spectrum of secure communications, from quantum-resistant networks to electronic transactions. It also features seamless compatibility with network security protocols like MACsec, IPsec, and transport protocols such as TLS and SSL. The KiviPQC-KEM is delivered with comprehensive supporting documentation and source codes, ensuring that it meets the needs of developers seeking robust, quantum-safe solutions.
The Reed-Solomon Codec by IPrium is a powerful tool in the arsenal of digital communication systems, providing exceptional error detection and correction capabilities. Renowned for its effectiveness in correcting multiple symbol errors, this codec is instrumental in ensuring data integrity across a broad range of applications. Utilized extensively in data storage solutions and communication protocols, Reed-Solomon codes are critical for environments where data accuracy is paramount. They are particularly valuable in systems like digital television, CD/DVD storage, and satellite communication, where they effectively manage and correct erroneous data transmissions. This codec is designed for seamless integration into advanced digital systems, supporting flexible configuration options to cater to specific user needs. By leveraging FPGA technology, it offers impressive performance characteristics, ensuring reliable data transmission and storage, even in challenging conditions.
Fault Injection Detection IP from Crypto Quantique provides a defense mechanism against physical attacks on silicon through hardware-level fault detection. By monitoring anomalies in clock, power, and thermal parameters, this IP enables secure embedded systems to proactively respond to potential glitches, enhancing overall security. Its modular design allows easy integration with existing crypto IPs and secure FSMs, providing additional layers of protection for sensitive embedded devices. Critical for automotive, medical, and industrial applications, the IP helps in meeting security standards like ISO/SAE 21434 and IEC 62443. This IP provides flexible configuration of sensitivity levels and pulse durations to tailor defenses to specific threat models, ensuring minimal impact on performance while maintaining a high level of security.
QRoot Lite is designed for resource-constrained MCUs and IoT devices, offering a lightweight, configurable root-of-trust. Built on TCG MARS specification, it simplifies integration and reduces cost, ensuring secure boot, attestation, and key protection. The IP minimizes silicon and power requirements, making it ideal for low-power device applications. Its flexible architecture allows seamless inclusion into SoC designs, offering not only secure boot and firmware validation but also tamper protection and unauthorized access prevention during device operation. QRoot Lite provides secure attestation using Trusted Computing Group standards, making it an excellent choice for meeting compliance and security standards in smart sensors, medical devices, and gateway products. It supports integration with standard industry interfaces and is optimized for low silicon footprint, reinforcing its versatility in diverse IoT environments.
Crypto Quantique's Cryptographic Cores are scalable cryptographic accelerators offering comprehensive algorithm coverage including AES, SHA, ECC, Ascon, and emerging post-quantum cryptography standards like Kyber and Dilithium. These cores are engineered for high-performance deployments in secure SoC designs, optimized for low-area and low-latency operation. Designed to resist side-channel and fault injection attacks, these cores provide a secure foundation for enforcement of secure boot, identity verification, and encryption protocols across various device implementations. This ensures reliable cryptographic operations in industry sectors like IoT, automotive, and medical devices. The cores offer configurable integration options, accommodating a variety of interface standards such as APB and AXI, which ease incorporation into existing development workflows. Focused on achieving compliance, these cores come with processes streamlined for regulatory certification, making them a pragmatic choice for forward-thinking system designs.
The Agile Secure Element is a configurable security enclave designed for integrating robust, flexible security features directly into SoC designs. It includes an embedded microprocessor and various cryptographic engines, supporting tasks like secure boot and trusted execution, making it an ideal tool for creating trusted zones in multi-core or subsystem-based SoC designs. With support for high-speed cryptographic operations and customizable architecture, the Agile Secure Element is prepared for regulatory compliance, ensuring capabilities align with standards like CRA and ISO. Its modular, certifiable design allows efficient security integration without the need for extensive modifications to existing systems. The IP features a rich set of cryptographic primitives and integration flexibility, accommodating standard interfaces like APB and AXI, which facilitates its adoption within various system architectures. The support for post-quantum cryptographic (PQC) implementations further enhances its readiness for future security requirements, ensuring next-generation SoC robustness, while maintaining efficient power and area ratios.
The True Random Number Generator (TRNG) IP is essential for generating high-quality entropy sources needed for secure cryptographic operations. NIST- and BSI-compliant, this product ensures secure key generation and other critical encryption operations, forming a foundational element for secure SoC and embedded systems. TRNG provides high throughput of up to 100 Mbit/s, supported by in-built health checks to maintain entropy quality over time and under various operating conditions. The TRNG offers digital and analog implementations, providing flexibility depending on performance requirements and integration specifics. Errored entropy output detection and conditioning ensure continuous operational integrity, making it ideal for secure boot and identity provision applications. With robust integration support, the TRNG IP fits seamlessly into diverse electronic environments, cementing its role in maintaining scalable and reliable cryptographic operations.
Post-Quantum Cryptography (PQC) by Secure-IC focuses on developing and implementing cryptographic techniques that are resistant to potential threats posed by quantum computing. As quantum computing capabilities advance, traditional cryptographic methods could become obsolete; therefore, Secure-IC's PQC solutions aim to offer a robust defense by employing algorithms that quantum computers cannot easily break. This solution is pivotal for enterprises looking to future-proof their cybersecurity frameworks, ensuring that even with the advent of powerful quantum processors, sensitive information remains secure.
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