All IPs > Security IP > Platform Security
In today's digital world, the importance of platform security cannot be overstated. Platform security semiconductor IPs are essential for protecting electronic systems from an increasing array of threats. These IPs play a critical role in ensuring that systems remain secure by safeguarding data, communications, and applications from unauthorized access or malicious attacks.
Platform security IPs include a variety of solutions such as encryption engines, secure boot mechanisms, and trusted execution environments. These technologies work in harmony to validate the authenticity of hardware and software components, providing a comprehensive security framework for electronic devices. By integrating these security measures at a fundamental level, semiconductor IPs ensure that systems are resilient to tampering and meet stringent security standards.
The applications of platform security semiconductor IPs span across a multitude of industries. From consumer electronics like smartphones and smart home devices to critical infrastructure systems and automotive applications, robust security is imperative. These IPs are designed to address the security needs of both edge devices and cloud-based platforms, preserving the integrity and confidentiality of sensitive data as it is processed and transmitted.
In our Silicon Hub, you will find a diverse array of platform security semiconductor IPs tailored to meet varied security requirements. Whether you're looking to protect consumer devices or safeguard enterprise data centers, our cutting-edge IP solutions provide the reliability and flexibility needed to counteract evolving security threats. Explore our category to enhance your products with state-of-the-art security technologies.
Akida Neural Processor IP by BrainChip serves as a pivotal technology asset for enhancing edge AI capabilities. This IP core is specifically designed to process neural network tasks with a focus on extreme efficiency and power management, making it an ideal choice for battery-powered and small-footprint devices. By utilizing neuromorphic principles, the Akida Neural Processor ensures that only the most relevant computations are prioritized, which translates to substantial energy savings while maintaining high processing speeds. This IP's compatibility with diverse data types and its ability to form multi-layer neural networks make it versatile for a wide range of industries including automotive, consumer electronics, and healthcare. Furthermore, its capability for on-device learning, without network dependency, contributes to improved device autonomy and security, making the Akida Neural Processor an integral component for next-gen intelligent systems. Companies adopting this IP can expect enhanced AI functionality with reduced development overheads, enabling quicker time-to-market for innovative AI solutions.
Akida IP represents BrainChip's groundbreaking approach to neuromorphic AI processing. Inspired by the efficiencies of cognitive processing found in the human brain, Akida IP delivers real-time AI processing capabilities directly at the edge. Unlike traditional data-intensive architectures, it operates with significantly reduced power consumption. Akida IP's design supports multiple data formats and integrates seamlessly with other hardware platforms, making it flexible for a wide range of AI applications. Uniquely, it employs sparsity, focusing computation only on pertinent data, thereby minimizing unnecessary processing and conserving power. The ability to operate independently of cloud-driven data processes not only conserves energy but enhances data privacy and security by ensuring that sensitive data remains on the device. Additionally, Akida IP’s temporal event-based neural networks excel in tracking event patterns over time, providing invaluable benefits in sectors like autonomous vehicles where rapid decision-making is critical. Akida IP's remarkable integration capacity and its scalability from small, embedded systems to larger computing infrastructures make it a versatile choice for developers aiming to incorporate smart AI capabilities into various devices.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The aiWare hardware neural processing unit (NPU) stands out as a state-of-the-art solution for automotive AI applications, bringing unmatched efficiency and performance. Designed specifically for inference tasks associated with automated driving systems, aiWare supports a wide array of AI workloads including CNNs, LSTMs, and RNNs, ensuring optimal operation across numerous applications.\n\naiWare is engineered to achieve industry-leading efficiency rates, boasting up to 98% efficiency on automotive neural networks. It operates across various performance requirements, from cost-sensitive L2 regulatory applications to advanced multi-sensor L3+ systems. The hardware platform is production-proven, already implemented in several products like Nextchip's APACHE series and enjoys strong industry partnerships.\n\nA key feature of aiWare is its scalability, capable of delivering up to 1024 TOPS with its multi-core architecture, and maintaining high efficiency in diverse AI tasks. The design allows for straightforward integration, facilitating early-stage performance evaluations and certifications with its deterministic operations and minimal host CPU intervention.\n\nA dedicated SDK, aiWare Studio, furthers the potential of the NPU by providing a suite of tools focused on neural network optimization, supporting developers in tuning their AI models with fine precision. Optimized for automotive-grade applications, aiWare's technology ensures seamless integration into systems requiring AEC-Q100 Grade 2 compliance, significantly enhancing the capabilities of automated driving applications from L2 through L4.
The Polar ID system by Metalenz revolutionizes biometric security through its unique use of meta-optic technology. It captures the polarization signature of a human face, delivering a new level of security that can detect sophisticated 3D masks. Unlike traditional structured light technologies, which rely on complex dot-pattern projectors, Polar ID simplifies the module through a single, low-profile polarization camera that operates in near-infrared, ensuring functionality across varied lighting conditions and environments. Polar ID offers ultra-secure facial authentication capable of operating in both daylight and darkness, accommodating obstacles such as sunglasses and masks. This capability makes it particularly effective for smartphones and other consumer electronics, providing a more reliable and secure alternative to existing fingerprint and visual recognition technologies. By integrating smoothly into the most challenging smartphone designs, Polar ID minimizes the typical hardware footprint, making advanced biometric security accessible at a lower cost. This one-of-a-kind technology not only enhances digital security but also provides seamless user experiences by negating the need for multiple optical components. Its high resolution and accuracy ensure that performance is not compromised, safeguarding user authentication in real-time, even in adverse conditions. By advancing face unlock solutions, Polar ID stands as a future-ready answer to the rising demand for unobtrusive digital security in mainstream devices.
PUFrt stands as a flagship hardware root of trust solution, incorporating PUF technology to create a unique and unclonable UID directly on the chip. This ensures robust security from the ground up, offering features such as TRNG, secure OTP, and an attack-resistant shell. The architecture of PUFrt provides a resilient foundation for semiconductor devices, helping to mitigate reverse engineering and counterfeiting risks. It integrates seamlessly with various systems, offering a trusted base for lightweight hardware security keys and full-function security coprocessors.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The eSi-Crypto suite provides a comprehensive range of encryption and authentication functionalities catered for integration in both ASIC and FPGA targets. Designed with efficiency in mind, it offers low resource usage coupled with high throughput. This suite incorporates a high-grade True Random Number Generator (TRNG) compliant with NIST 800-22 standards. Available with standalone or AMBA APB/AHB/AXI bus interfaces, it supports a wide range of cryptographic algorithms such as CRYSTALS Kyber, Dilithium, ECDSA, RSA, AES, and SHA, providing robust security solutions adaptable to varying application needs.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
The RISC-V CPU IP NS Class is specifically engineered for security-focused applications, including fintech mobile payments and IoT security. This architecture supports a variety of security protocols, making it ideal for systems that require robust data protection and secure transaction handling. It features a background in efficiently managing sensitive information, supporting comprehensive information security solutions with strong cryptographic capabilities. This IP is built with RISC-V's flexible extensions, ensuring files and communication streams maintain confidentiality and integrity in diverse operational scenarios. Robust by design, the NS Class caters to sectors such as IoT, where data protection is paramount, making it a trusted choice for developers seeking to enforce stringent security measures into their solutions. With options for extending functionality and increasing resilience through user-defined instructions, the NS Class remains adaptable for future security requirements.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
Suite-Q SW stands as a versatile cryptographic software library offered by PQ Secure that is meticulously engineered to optimize code size, stack usage, and performance across various processing environments. This library is built to be portable, with implementations available in C and assembly languages, catering to a wide array of processor architectures including 8-, 16-, 32-, and 64-bit systems. The software library is designed to seamlessly integrate into diverse development environments, providing developers with modular plug-in modules that facilitate easy hardware offload. Suite-Q SW supports a comprehensive spectrum of cryptographic operations, including both symmetric encryption such as AES and advanced post-quantum schemes, ensuring robust data protection. As part of its feature set, Suite-Q SW offers multiple configurations, allowing developers to balance memory utilization and processing speed according to their specific application needs. This flexibility makes the library suitable for both general-purpose applications and highly specialized embedded systems, ensuring it meets the stringent requirements of modern security demands.
The QDID PUF uses quantum tunneling via variations in the oxide layer of a CMOS process, creating a unique identity for devices. It eliminates the complexities and costs of traditional secure provisioning by generating high entropy keys on-demand from intrinsic quantum phenomena. This hardware-anchored identity solution excels in resisting side-channel attacks and offers compliance with standards like PSA Level 2 and CC EAL4+. Extensive environmental testing ensures durability, making it ideal for applications including secure key generation and device authentication.
Focused on automotive applications and certified for ISO 26262 Functional Safety, the RISC-V CPU IP NA Class is a specialized offering for high-stakes environments such as vehicular systems. Its design is tailored to meet the rigorous safety standards required in the automotive industry, supporting ASIL-B and ASIL-D safety levels. The NA Class IP combines robust functionality with advanced safety measures, providing a reliable solution for implementing safety-critical tasks in next-generation automotive designs. With scalability at its core, it supports advanced RISC-V extensions and user-defined instruction sets, ensuring the adaptability of the IP to meet evolving industry standards and custom specifications. Through its comprehensive support of safety and performance features, the NA Class stands as a reliable building block for developers focusing on creating secure, high-performance automotive systems. Its cutting-edge design ensures it can handle the sophisticated demands of modern vehicles, from engine management to advanced driver-assistance systems (ADAS).
NeoFuse is a highly reliable anti-fuse One-Time Programmable (OTP) memory solution developed by eMemory. This technology is designed to offer robust protection and security for semiconductor applications, particularly in environments where permanent data storage and retrieval are crucial. NeoFuse's architecture ensures data integrity and reliability by resisting tampering and unauthorized access, primarily through its irreversible programming characteristics. The OTP memory can be utilized in various applications, including code storage, trimming, and parameter setting, serving industries such as mobile computing, automotive, and security systems. It is particularly beneficial for applications requiring low power consumption and high data endurance, providing a cost-effective and efficient solution for modern electronic devices. NeoFuse is also compatible with advanced semiconductor processes, exemplifying its flexibility and adaptability to different design and manufacturing needs. This capability allows designers to incorporate NeoFuse into diverse products without significant adjustments, ensuring seamless integration into existing and new systems alike, promoting expansive innovation in design and functionality.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
Suite-Q HW is a comprehensive system-on-chip (SoC) design that encapsulates all necessary standardized cryptographic protocols required for secure communication. PQ Secure has engineered this hardware solution to cater to both high-end servers and low-end embedded systems, providing a flexible platform that adapts to various operational requirements. This product achieves performance efficiency by offloading symmetric and asymmetric cryptographic operations to specialized hardware accelerators, effectively reducing the computational burden on the central processor. Suite-Q HW supports a range of cryptographic functions, from Advanced Encryption Standard (AES) implementations to complex public-key cryptographic standards such as ECDSA and lattice-based cryptography. A prominent feature of Suite-Q HW is its capability to incorporate optional differential power analysis (DPA) countermeasures, which secure cryptographic operations against side-channel attacks. Furthermore, the design of Suite-Q HW facilitates ease of integration with various SoC and FPGA architectures, making it a highly adaptable solution for developers seeking to enhance their security infrastructure without substantial redesign efforts.
NeoPUF is a cutting-edge hardware solution that revolutionizes semiconductor security through its advanced random number generation capabilities. It offers up to 100 times faster performance compared to traditional methods, positioning it as an essential component for the next generation of secure chips. The technology is rooted in the concept of Physical Unclonable Functions (PUFs), which inherently provide unique identifiers to each chip, ensuring unforgeable security features. NeoPUF offers a robust foundation for securing semiconductors throughout their lifecycle, addressing vulnerabilities in data at rest, in transit, and during processing. Its design leverages both analog and digital components to achieve unmatched security and reliability, creating a formidable 'drop-in' security module solution. With applications spanning a variety of industries, including automotive, IoT, and mobile computing, NeoPUF enables these sectors to enhance device integrity, combat counterfeiting, and secure sensitive information. The technology's integration into semiconductor design eliminates the need for costly and complex key management processes, thus streamlining the production and operation phases. Additionally, NeoPUF's adaptability to future computing demands, such as those posed by quantum advances, further cements its place as a versatile and forward-thinking security solution.
PUFhsm is an advanced embedded hardware security module designed for automotive and complex applications. It acts as an embedded security enclave, isolating key functions from the main system to ensure secure operations. With integrated cryptographic engines and dedicated CPUs, PUFhsm supports secure boot, updates, and key management within a compliant framework. It enhances designs by bolstering security while optimizing efficiency and reducing time-to-market.
The FortiPKA-RISC-V is a unique public key accelerator that incorporates modular multiplication resistant to both side-channel and fault injection threats. It serves as an efficient coprocessor for RISC-V architectures, enabling secure and quick cryptographic operations while offering a streamlined performance across low-power device applications.
ZIA Stereo Vision is designed to offer superior depth perception and object detection by employing advanced stereo vision algorithms. This system enhances the capabilities of autonomous vehicles and drones, providing precise imaging for real-time decision-making applications. Built with a focus on accuracy and computational efficiency, it supports a range of stereoscopic camera systems, enabling better navigation and environmental interaction.
Post-Quantum Cryptography IP offers a hardware-based solution integrated with software capabilities to ensure secure communications in a quantum computing era. Designed with quantum resistance in mind, it supports key exchange, encapsulation, and decapsulation functions using lattice-based algorithms. This IP is equipped with measures to protect against side-channel attacks, including simple power analysis and differential power analysis. Offering interfaces like AMBA, it ensures flexibility in integration within various systems, positioning it as a crucial component for future-proofing communication security against the impending challenges of quantum computation.
The DSHA2-512 core specializes in the SHA2-512 hashing algorithm, providing a highly efficient means to process hashing functions in data-intensive environments. It is designed to comply with FIPS PUB 180-4 standards, ensuring that it meets established guidelines for secure hashing operations necessary in a variety of industry settings. With interfaces that include APB, AHB, and AXI, the DSHA2-512 exhibits broad compatibility with existing digital infrastructures, enabling it to be deployed across a wide array of technology solutions. This core is ideal for sectors where ensuring data integrity and authenticity is critical, such as finance, governmental, and secure communications sectors. Its enhanced technical capabilities mean that the DSHA2-512 core supports extensive data processing requirements while maintaining the security integrity of hashes, making it an essential component for applications that demand reliable hash computation and data security.
The SHA-3 Crypto Engine offers a robust hardware acceleration solution for cryptographic hashing functions. Its design prioritizes high throughput and efficient resource utilization, complying with NIST’s FIPS 202 standards. The core supports various SHA-3 hash functions including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512, alongside Extendable Output Functions (XOF) like SHAKE-128 and SHAKE-256. This comprehensive support makes it a versatile tool for ensuring data integrity and authentication in a multitude of applications. A key feature of the SHA-3 Crypto Engine is its protection against timing-based side channel attacks, offering a secure cryptographic environment. Fully synchronous in design, it operates within a single clock domain, ensuring stability and reliability across different platforms. Its applications span various domains such as secure boot engines, IPsec and TLS/SSL protocol engines, and even blockchain technologies. The core has been extensively verified and includes features such as automatic byte padding, making it an adaptable solution across a wide range of applications. It’s designed to be implemented on both FPGAs and ASICs, ensuring flexibility and adaptability in various deployment scenarios.
The Video Anonymization solution by Gyrus AI is designed to meet regulatory compliance mandates like GDPR by ensuring the privacy of individuals captured in videos. By using advanced AI techniques, it automatically detects and blurs faces, license plates, and other sensitive information in video footage. This tool not only complies with global data privacy laws but also maintains video quality, allowing businesses to handle, process, and share video content securely and ethically. One of the standout features of this solution is its ability to replace real faces with AI-generated synthetic characters. This means that identity protection is assured without losing critical non-identifying attributes, making it exceptionally suitable for industries such as automotive, healthcare, and media. The system's automated nature means that it can handle large datasets efficiently, up to 10 times more than conventional methods, and at a significantly reduced cost, often lowering expenses by up to 70%. The solution integrates seamlessly into existing workflows, thanks to its high degree of customization and compliance with various industry standards. Whether used in real-time or batch processing, its superior anonymization capabilities outperform traditional methods, enhancing privacy levels while facilitating post-processing analytics like emotion tracking and gaze detection. Gyrus AI’s tool empowers organizations to meet privacy standards effectively, thereby facilitating secure media sharing and analysis.
The Column A/D Converter serves as a pivotal component in CMOS image sensors, converting analog signals from pixels into a precise digital format for subsequent processing. Embedded with advanced signal processing techniques, this IP ensures minimal error margins and optimizes the performance of imaging systems by effectively handling noise and signal variance. Engineered to support high-speed and high-accuracy image conversions, this A/D converter is structured to accommodate single-slope and multi-slope methodologies to maximize data fidelity and resolution. Its flexibility allows it to adapt to varied operational contexts, ranging from consumer electronics to specialized industry applications like barcode scanning and biometric authentication. With a focus on minimizing power consumption while ensuring efficient signal conversion, this converter meets the stringent requirements for portable and battery-operated devices. Combining compact design with sophisticated algorithmic processing, the Column A/D Converter is integral to enhancing overall image quality and system efficiency, making it indispensable for modern imaging solutions prepared to meet tomorrow’s technological demands.
Comcores' MACsec solution addresses the needs for secure communication on Ethernet links by implementing the IEEE 802.1AE standard for MAC Security. It provides comprehensive protection against eavesdropping and manipulation, making it suitable for applications demanding high security over public and private networks. Built to support various data rates, the MACsec IP core integrates robust cryptographic suites like AES-GCM to encrypt and authenticate network traffic. Its deployment ensures data confidentiality and integrity, fostering a secure environment for transmitting sensitive information such as in military communication systems and data centers.
The Security Protocol Accelerator from PQ Secure Technologies enhances the computational efficiency of cryptographic operations by accelerating the execution of security protocols on hardware platforms. This innovative solution is meticulously designed to optimize the processing of cryptographic algorithms, thereby reducing the computational load on host processors. By integrating the Security Protocol Accelerator, systems benefit from a significant boost in performance, particularly when handling large volumes of cryptographic data. This makes it an excellent fit for applications that demand real-time processing capabilities, such as network security appliances and high-performance servers. The accelerator provides streamlined execution pathways for both symmetric and asymmetric encryption operations, ensuring rapid and secure data exchanges. Another key feature of this product is its flexibility to integrate with existing systems, making it a versatile solution across a wide range of industries and applications. By offloading demanding cryptographic tasks, it not only enhances the throughput of digital systems but also improves the overall security posture by implementing hardware-based security measures. This approach ensures that sensitive operations are conducted swiftly and securely, safeguarding against potential cyber threats.
The DSHA2-256 core is a dedicated solution for hashing functions, specifically designed to excel in processing the SHA2-256 algorithm. Compliant with the FIPS PUB 180-4 standards, this universal core accelerates the hash operation, providing efficient and secure data processing options for diverse digital systems. Its architecture supports both APB, AHB, and AXI bus interfaces, allowing for easy integration into numerous applications that require robust hashing mechanisms. The core enhances processing capabilities, facilitating the rapid execution of secure hash functions that protect data integrity and authenticity. This IP core is invaluable in fields where data security and integrity are critical, such as banking, digital communication, and any networked environment where information verification is necessary. By providing dedicated hardware for hashing tasks, it ensures high levels of data protection and performance, making it an ideal choice for developers looking to implement reliable security solutions.
The Cryptographic COEsec core is pivotal for substation automation systems requiring robust security measures. This core integrates advanced cryptographic techniques to safeguard communications and data integrity within critical infrastructure networks. Ensuring secure and trusted data exchanges makes it indispensable for environments where maintaining confidentiality and integrity is non-negotiable, such as power and utility sectors.
The Keccak Hash Engine is a versatile IP core known for its role in guaranteeing data security through a variety of cryptographic operations. This core is not just limited to hashing functions but extends its capabilities to include authentication, encryption, and pseudo-random number generation. Fundamental to its design is the use of the sponge construction and the innovative Keccak-f cryptographic permutation. This IP core stands out for its flexibility, allowing for customization in hash output lengths and security levels. Standardized under widely recognized protocols like NIST's FIPS 202, the Keccak Hash Engine has undergone thorough scrutiny ensuring its robustness. The design is optimized for seamless integration into existing systems, operating efficiently within a single clock domain. The Keccak Hash Engine’s applications extend across various sectors, providing essential security functions for systems like blockchain, PRNG, and more. Its configurability means it can adapt to numerous scenarios, maintaining high security standards as required by different applications.
This IP core offers comprehensive countermeasures against fault injection attacks, utilizing both algorithmic and circuit-level techniques. It enhances the robustness of systems where reliability is paramount, particularly in applications requiring high levels of security under adverse conditions.
This IP core is designed to mitigate the risks associated with side-channel attacks, offering circuit-level enhancements to prevent data leakage from power and electromagnetic emissions. It integrates seamlessly with existing architectures, providing an additional layer of security without compromising processing power or speed.
The DSHA2-384 core is optimized for executing the SHA2-384 hash function, ensuring secure and efficient handling of hashing operations within digital systems. It fully complies with FIPS PUB 180-4 standards, ensuring adherence to widely recognized security protocols and making it ideal for industries that demand high standards of data protection. This IP core supports a variety of bus interfaces including APB, AHB, and AXI, providing compatibility with a broad range of system architectures. Its advanced security features enhance hashing processes, enabling rapid and secure management of data in applications that range from financial transactions to complex data security implementations. For security-focused applications, the DSHA2-384 core offers unmatched reliability and performance. It suits environments where data integrity is paramount, supporting industries that need robust digital security measures. The core facilitates secure communications and encrypted storage, making it a vital tool for safeguarding sensitive information in a digital-first world.
Rambus' Root of Trust is a foundational technology for securing system on chip (SoC) hardware and safeguarding data at rest. This solution caters to government and automotive sectors, featuring programmable secure co-processors and highly compact designs with options for Quantum Safe Cryptography. Available with certifications for FIPS 140 CMVP and ISO 26262, it is vital for applications requiring stringent security measures.
The FortiMac library provides advanced protection for HMAC SHA2 implementations, ensuring resilience against differential power analysis (DPA) and fault injection. It is designed for situations requiring high-security cryptographic computations without sacrificing efficiency, particularly in environments where power and area are constrained.
The Reed-Solomon Codec by IPrium is a powerful tool in the arsenal of digital communication systems, providing exceptional error detection and correction capabilities. Renowned for its effectiveness in correcting multiple symbol errors, this codec is instrumental in ensuring data integrity across a broad range of applications. Utilized extensively in data storage solutions and communication protocols, Reed-Solomon codes are critical for environments where data accuracy is paramount. They are particularly valuable in systems like digital television, CD/DVD storage, and satellite communication, where they effectively manage and correct erroneous data transmissions. This codec is designed for seamless integration into advanced digital systems, supporting flexible configuration options to cater to specific user needs. By leveraging FPGA technology, it offers impressive performance characteristics, ensuring reliable data transmission and storage, even in challenging conditions.
The Fault Injection Detection IP enhances security by providing hardware-level defenses against glitch-based physical attacks. It includes modular detectors for clock, power, and thermal anomalies, ensuring protection of cryptographic implementations from real-world intrusion strategies. The IP is crucial for applications in automotive, medical, and high-assurance industrial sectors, as it allows detection and response to various physical threat vectors without affecting performance.
The CCSDS LDPC (8160, 7136) IP is a meticulously crafted Low-Density Parity-Check encoder and decoder tailored for space communication standards. The Consultative Committee for Space Data Systems (CCSDS) has specified these LDPC codes to enhance data integrity and reliability for space missions where error-free transmission is crucial. This IP core offers significant improvements in error correction performance, making it ideal for deep space and near-Earth missions requiring high data throughput and reliability. The use of LDPC coding provides a significant advantage over traditional error correction methods, enabling efficient data recovery even under challenging conditions. Designed for FPGA implementation, the IP can be seamlessly integrated into space communication systems, offering reliable performance and ensuring compliance with CCSDS standards. Its efficient use of resources makes it a preferred choice for space agencies looking to maximize mission success.
The KiviPQC-KEM is a post-quantum cryptographic IP core designed for the future of secure communications. It implements the ML-KEM Key Encapsulation Mechanism, which is a robust algorithm resistant to quantum computing attacks. This IP core is capable of executing key generation, encapsulation, and decapsulation operations as per the NIST FIPS 203 standard. Highly efficient in performance, the KiviPQC-KEM operates with minimal logic utilization making it cost-effective for clients. It offers high-level security by providing hardware acceleration for computationally demanding tasks, minimizing vulnerabilities and ensuring maximum protection in communications. Ideal for applications that prioritize quantum-resistance, the KiviPQC-KEM is suitable for securing network infrastructures, transport protocols like TLS and SSL, and electronic transactions. The architecture facilitates easy integration into a wide range of platforms, supporting both FPGA and ASIC implementations.
The Agile Secure Element IP is a customizable security enclave, integrating secure boot, key storage, and trusted execution into SoCs. It features crypto-accelerated engines for secure operations and a secure microprocessor, which can include a RISC-V core for isolation of critical processes. Designed to meet regulatory standards, it offers flexibility in integrating secure elements without custom development, facilitating rapid design of secure devices across various industries such as automotive and medical.
QRoot Lite is a flexible and lightweight root-of-trust designed for microcontrollers and IoT devices, especially those constrained by power and space. Following the TCG MARS specification, it introduces essential security features such as secure boot, attestation, and key protection. This IP minimizes costs and simplifies integration, aiding teams aiming for regulatory compliance and robustness in products that include smart sensors and medical devices. Its architecture is secured against counterfeiting and tampering, offering future-proof security with cryptographic agility.
The Platform-Level Interrupt Controller (PLIC) from Roa Logic is a fully compliant and flexible solution designed in accordance with the RISC-V specifications. This interrupt controller is crucial for managing multiple interrupt sources in a computing system, providing reliable and efficient handling of interrupt requests. Its parameterized design enables easy configuration to meet specific project requirements, thus offering an adaptable solution for varied embedded applications.
These Cryptographic Cores are scalable, high-performance solutions providing implementations of symmetric, asymmetric, and post-quantum algorithms ideal for secure SoC designs. The cores are engineered to meet the demands of various markets including automotive and medical, featuring low-area, high-throughput, and built-in side-channel resistance. They support a range of cryptographic standards like AES, SHA, and ECC, and are future-proof with support for post-quantum algorithms such as Kyber and Dilithium.
This True Random Number Generator (TRNG) IP ensures high-quality entropy for secure key generation and cryptographic operations. Compliant with NIST and BSI standards, the TRNG offers both digital and analog implementations, which facilitate robust key management in secure boot and identity provisioning. Its secure entropy generation meets rigorous statistical health tests and can reach sampling rates up to 100 Mbit/s, providing a trustworthy foundation for cryptographic processes in a variety of applications.
The Digital PUF provides a compact and logic-based physically unclonable function (PUF) ideal for generating secure identities and keys within SoCs. This IP generates unclonable 128 or 256-bit seeds, offering a root of trust for secure boot, key generation, and device authentication while maintaining a minimal silicon footprint. It integrates seamlessly using APB or AXI interfaces and ensures high entropy through built-in standards-validated randomness tests. This makes the Digital PUF robust against tampering and optimal for low-footprint designs.
The TLS1.3 Processor Core offers exceptional security features, chiefly focusing on enhancing encrypted communication. Utilizing elliptic curve cryptography bases such as ECDSA, it supports high-level security credentials and facilitates fast processing speeds. The core stands out with its ability to maintain high throughput while minimizing latency, making it ideal for applications requiring secure, high-speed data exchanges. Perfectly suited for industrial IoT and aviation systems, the TLS1.3 core ensures robust protection against potential cybersecurity threats.
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