All IPs > Security IP > Cryptography Cores
In today's interconnected world, the importance of secure communication and data protection cannot be overstated. Cryptography cores are a crucial subset of semiconductor IPs designed to provide foundational security solutions across a variety of electronic systems. At their core, these IPs implement complex algorithms that ensure the confidentiality, integrity, and authenticity of data being processed and exchanged.
The cryptography cores available in this category offer a diverse range of features tailored to different security needs. From symmetric-key algorithms like AES to asymmetric-key systems such as RSA and ECC, these cores ensure that systems can securely encrypt and decrypt information, protecting it from unauthorized access and tampering. By embedding these cryptographic functions directly into hardware, it becomes possible to achieve faster processing speeds and higher levels of security compared to software implementations.
These semiconductor IPs are widely used in applications where data security is paramount. This includes, but is not limited to, industries such as finance, telecommunications, and healthcare. Devices utilizing cryptography cores can range from secure payment systems, ensuring safe financial transactions, to mobile devices for secure communications, to medical devices that safeguard sensitive health information. Additionally, with the rise of the Internet of Things (IoT), cryptography cores are increasingly crucial in providing secure connections for a myriad of smart devices.
By integrating cryptography cores into your designs, you not only improve security but also future-proof your products against many potential vulnerabilities. As security threats continue to evolve, having robust cryptography solutions is essential for maintaining trust and reliability in your products and services. Whether you're developing a new application or enhancing an existing one, our category of cryptography cores offers the semiconductor IP solutions you need to meet today's stringent security demands.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
The Polar ID Biometric Security System by Metalenz revolutionizes smartphone biometric security with its advanced imaging capabilities that capture the full polarization state of light. This system detects unique facial polarization signatures, enabling high-precision face authentication that even sophisticated 3D masks cannot deceive. Unlike traditional systems requiring multiple optical modules, Polar ID achieves secure recognition with a single image, ideal for secure digital payments and more. Operating efficiently across various lighting conditions, from bright daylight to complete darkness, Polar ID ensures robust security without compromising user convenience. By leveraging meta-optic technology, it offers a compact, cost-effective alternative to structured light solutions, suitable for widespread deployment across millions of mobile devices.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
The Dynamic Neural Accelerator II (DNA-II) is a highly efficient and versatile IP specifically engineered for optimizing AI workloads at the edge. Its unique architecture allows runtime reconfiguration of interconnects among computing units, which facilitates improved parallel processing and efficiency. DNA-II supports a broad array of networks, including convolutional and transformer networks, making it an ideal choice for numerous edge applications. Its design emphasizes low power consumption while maintaining high computational performance. By utilizing a dynamic data path architecture, DNA-II sets a new benchmark for IP cores aimed at enhancing AI processing capabilities.
aiWare represents aiMotive's advanced hardware intellectual property core for automotive neural network acceleration, pushing boundaries in efficiency and scalability. This neural processing unit (NPU) is tailored to meet the rigorous demands of automotive AI inference, providing robust support for various AI workloads, including CNNs, LSTMs, and RNNs. By achieving up to 256 Effective TOPS and remarkable scalability, aiWare caters to a wide array of applications, from edge processors in sensors to centralized high-performance modules.\n\nThe design of aiWare is particularly focused on enhancing efficiency in neural network operations, achieving up to 98% efficiency across diverse automotive applications. It features an innovative dataflow architecture, ensuring minimal external memory bandwidth usage while maximizing in-chip data processing. This reduces power consumption and enhances performance, making it highly adaptable for deployment in resource-critical environments.\n\nAdditionally, aiWare is embedded with comprehensive tools like the aiWare Studio SDK, which streamlines the neural network optimization and iteration process without requiring extensive NPU code adjustments. This ensures that aiWare can deliver optimal performance while minimizing development timelines by allowing for early performance estimations even before target hardware testing. Its integration into ASIL-B or higher certified solutions underscores aiWare's capability to power the most demanding safety applications in the automotive domain.
The Alcora V-by-One HS Daughter Card is tailored for high-speed digital interfacing, specifically aligning with FPGA development boards via FMC connectors. The card features 8 RX and 8 TX lanes, with the option to combine two FMC cards for a total of 16 lanes. This configuration supports video resolutions up to 4K at 120Hz or 8K at 30Hz, demonstrating its capability to handle large volumes of data efficiently. Designed to meet the demanding requirements of high-resolution and high-frame-rate applications, the Alcora card integrates dual clock generators to optimize signal clarity by synthesizing the transceiver reference clock and minimizing jitter. This characteristic is crucial in maintaining data integrity and ensuring smooth video performance, making the Alcora an optimal choice for flat panel display integration. Featuring flexible connectivity options, the Alcora card is available in both 51-pin and 41-pin header variants. This design ensures that it can provide a comprehensive interface to meet various technical challenges, advancing the capabilities of high-speed digital communications within FPGA systems.
PUFrt is a sophisticated Hardware Root of Trust (HRoT) solution that focuses on generating and storing root keys that never leave the chip, ensuring a secure environment for sensitive operations. This IP incorporates a 1024-bit Physical Unclonable Function (PUF) along with a true random number generator (TRNG) compliant with NIST standards. PUFrt's architecture is fortified with secure storage capabilities that protect key information from potential physical attacks, providing a robust security layer against future threats in the IoT landscape. Its design allows seamless integration across different systems and design architectures, making it versatile for applications ranging from lightweight hardware security keys to full-fledged Security Coprocessors. With built-in anti-tamper features and customization options, PUFrt is a prime choice for those looking to secure their semiconductor supply chain against threats like counterfeiting and reverse engineering. Certified by Riscure, PUFrt sets a high benchmark for reliable security practices in semiconductor design. Its comprehensive security framework makes it indispensable for modern chip designs that necessitate high levels of trust and integrity.
SphinX encryption technology delivers high-performance, low-latency AES-XTS encryption and decryption capabilities, specifically designed to meet the stringent security demands of modern data environments. It supports independent, non-blocking encryption and decryption channels, ensuring that data can be securely processed with minimal delay. This powerful encryption solution is ideal for data centers and enterprises subjected to significant data security and integrity requirements. By ensuring that data is protected from unauthorized access while maintaining operational efficiency, SphinX provides a robust foundation for secure data management. The capabilities of SphinX align with industry standards, making it suitable for a variety of applications that demand high levels of data encryption. Its integration aids businesses in protecting sensitive information without compromising on speed or computing power, facilitating secure yet agile data processing.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
The Intelligence X280 is engineered to provide extensive capabilities for artificial intelligence and machine learning applications, emphasizing a software-first design approach. This high-performance processor supports vector and matrix computations, making it adept at handling the demanding workloads typical in AI-driven environments. With an extensive ALU and integrated VFPU capabilities, the X280 delivers superior data processing power. Capable of supporting complex AI tasks, the X280 processor leverages SiFive's advanced vector architecture to allow for high-speed data manipulation and precision. The core supports extensive vector lengths and offers compatibility with various machine learning frameworks, facilitating seamless deployment in both embedded and edge AI applications. The Intelligence family, represented by the X280, offers solutions that are not only scalable but are customizable to particular workload specifications. With high-bandwidth interfaces for connecting custom engines, this processor is built to evolve alongside AI's progressive requirements, ensuring relevance in rapidly changing technology landscapes.
Helion Technology's AES-XTS solution offers state-of-the-art encryption for data-at-rest in storage systems, adept at mitigating threats such as copy-paste and dictionary attacks. AES-XTS operates by encrypting disk sector data with blocks of 16-bytes under a secret AES key, incorporating a modifier value corresponding to each block's logical disk location. This method ensures that identical plaintext sectors stored at different positions yield different encrypted outputs. Designed to handle high performance requirements, Helion's AES-XTS cores enable custom levels of throughput scaling from 1Gbps up to over 64Gbps, suitable for diverse scenarios like servers and high-speed SSDs. The product range includes single, twin, quad, and giga variants, aligning closely with specific performance and logic resource parameters, optimizing both hardware usage and security efficacy. This flexibility and adherence to the IEEE 1619 standard make Helion's AES-XTS cores valuable for any application demanding secure disk-level encryption. Available for either ASIC or FPGA platforms, these cores are constructed to leverage the unique capabilities of each technology, achieving the best possible performance across different use cases.
Secure OTP is a cutting-edge non-volatile memory solution designed to safeguard key, data, and secret storage with enhanced protection against hardware attacks. It features a combination of physical macros and digital RTL, offering robust anti-tamper and integrated protection mechanisms. This solution is specifically architected for integration in CMOS technologies and is compatible across numerous IC and ASIC applications. By incorporating a 1024-bit PUF for scrambling and I/O shuffling, Secure OTP significantly elevates stored data security, effectively making it tamperproof. As digital security challenges mount, Secure OTP provides a modernized answer, ensuring the safekeeping of critical information across its lifecycle. Its adoption addresses prevalent security gaps in legacy e-fuse solutions and is instrumental in extending robust defense systems within SoC environments, acting as a cornerstone for comprehensive hardware security strategies.
The eSi-Crypto solution provides an advanced encryption and authentication framework, ensuring robust security for digital data. Its sophisticated algorithms cover a wide array of cryptographic needs, from basic encryption to complex data protection mechanisms. This solution is designed to offer high performance with low resource consumption, making it ideal for various embedded systems where security and efficiency are paramount. EnSilica has integrated various cryptographic components, including True Random Number Generators (TRNGs), to support extensive security protocols. These components are critical in applications such as secure communications, financial transactions, and personal data protection, where unauthorized access prevention is crucial. The streamlined architecture of eSi-Crypto ensures it can be efficiently implemented across diverse system architectures, offering scalable security solutions for emerging digital threats. Its flexibility allows customization and integration with other IPs, providing a seamless security shield for both legacy and new systems.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Securyzr iSSP is an advanced integrated Security Service Platform that manages the security lifecycle of connected devices from chip to cloud. It provides a seamless solution for provisioning, firmware updates, security monitoring, and device identity management. This platform ensures reliability with zero-touch security services and is built to adapt to various lifecycle stages of embedded systems.
The 802.11 LDPC core by Wasiela is engineered for high throughput applications in wireless communication systems. It excels in providing frame-to-frame on-the-fly configuration, allowing developers to balance throughput and error correction performance according to specific needs. This LDPC solution is compliant with relevant throughput and performance specifications, ensuring reliable bit-error-rate and packet-error-rate outcomes that meet industry standards. The core's adaptability in decoding iterations is key to maintaining high efficiency without compromising on quality.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
The AES Core from Green IP Core provides robust encryption capabilities crucial for maintaining data security across a variety of platforms. It employs advanced encryption standards to safeguard sensitive information, thereby serving as a foundation for secure communication and data storage solutions. This IP is versatile enough to be implemented in both consumer electronics and large-scale enterprise systems where data protection is paramount. Designed with efficiency in mind, this core optimizes hardware resource usage, delivering high-speed encryption while minimizing impact on performance. Its architecture is specifically tailored to offer seamless integration into existing systems, requiring minimal reconfiguration of current operations. This adaptability makes it an ideal choice for companies looking to bolster their security measures without significant infrastructure changes. The AES Core stands out due to its fault-tolerant design, ensuring that it remains operable even under conditions that may induce errors in traditional systems. This reliability factor is key for industries where data integrity and security are of utmost importance, including finance, telecommunications, and government sectors.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The Securyzr Key Management System is pivotal in safeguarding cryptographic keys within various systems. By facilitating key lifecycle management, this system ensures that keys remain secure from creation through destruction. It offers an intuitive interface for administrators to oversee and manage keys across their network, providing peace of mind with enhanced access controls and auditing capabilities.
The RISC-V CPU IP NS Class is crafted explicitly for applications requiring heightened security and robustness, such as fintech payment systems and IoT security solutions. This processor class is equipped to support secure operations, incorporating features essential for protecting data and ensuring secure communications within devices. This processor integrates security protocols aligned with the RISC-V open standard, offering developers the ability to embed reliable security measures directly at the hardware level. Its architecture provides the foundation for developing systems where data integrity and secure processing are non-negotiable, ensuring that sensitive applications run safely and efficiently. The RISC-V CPU IP NS Class is supported by a strong ecosystem offering tools and resources to facilitate the secure application development process. With its ability to integrate seamlessly with other embedded systems, the NS Class empowers designers to create solutions that prioritize and enhance security in modern digital environments, where threats are constantly evolving.
Helion Technology delivers efficient hashing solutions through their SHA family of products, including SHA-1 and the more secure SHA-2 family, as well as MD5 for legacy purposes. These hashing cores are implemented to transform arbitrary-length files or messages into unique, fixed-length digests, which act as veritable signatures of the original data. These secure hash algorithms (SHAs) are integral to digital signatures and message authentication applications, underpinning protocols like IPsec and TLS/SSL by ensuring integrity and authenticity. With configurations optimized for high-speed and low-area applications, Helion's hashing solutions prove effective in systems needing cryptographic checks. The cores are partitioned into the FAST and TINY controls, each catering to different throughput and resource trade-offs. FAST delivers performance up to 4Gbps, focusing on speed, while TINY configurations are geared towards minimal resource utilization, providing an ideal solution for energy-efficient, low-data rate needs in both FPGA and ASIC technologies.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The FPGA Pre-Trade Risk Check by Algo-Logic Systems enhances financial security by performing comprehensive risk assessments before executing trades. This preemptive analysis is integrated directly into the FPGA infrastructure, facilitating extremely fast identification and analysis of potential risks. Market participants can immediately identify erroneous trades or breaches of risk parameters, ensuring compliance with established guidelines. With the capability to process data at exceptional speeds, this solution ensures that each trade adheres to the pre-defined risk criteria before it's executed in the market. This feature is particularly beneficial for financial institutions and trading firms where rapid and accurate risk assessment is crucial. By preventing unauthorized or high-risk trades from proceeding, the technology helps firms maintain their market integrity and avoid costly errors. Moreover, the integration of risk management processes within the FPGA framework provides an added layer of security, which is vital for maintaining trust and reliability in financial operations. The FPGA Pre-Trade Risk Check solution thus streamlines the intersection of speed, accuracy, and security in the financial trading sector.
The Individual IP Core Modules offered by ResQuant are designed to support a wide array of post-quantum cryptography needs, featuring compatibility with all recognized NIST PQC standards. These include pioneering algorithms such as Dilithium, Kyber, XMSS, and SPHINCS+, guaranteeing breadth in cryptographic applications. These modules offer comprehensive cryptographic functions like advanced encryption standards using AES, hashing with SHA2 and SHA3 families, and generation of true random numbers, posing as a versatile security solution adaptable to a variety of environments. Scheduled for future updates with additional protocols like the FRODO Key Encapsulation Mechanism, these IP cores promise continuous alignment with evolving cryptographic needs. Their structure accommodates substantial flexibility in terms of performance tuning and system integration, enabling easy deployment in diverse application scenarios, from IoT devices to large-scale data centers, making them a staple for entities preparing for quantum computing advancements. These modules ensure security frontiers remain resilient against future computational intricacies.
The AIoT Platform from SEMIFIVE is crafted to create specialized IoT and edge processing devices with efficiency and cutting-edge technology. Leveraging silicon-proven design components on Samsung's 14nm process, it streamlines the development of high-performance, power-efficient applications. This platform is equipped with dual SiFive U54 RISC-V CPUs, LPDDR4 memory, and comprehensive interfaces like MIPI-CSI and USB3.0. Targeted at consumer electronics such as wearables and smart home devices, this platform supports a wide array of IoT applications, including industrial IoT and smart security systems. Its architectural flexibility allows customization of system specifications, enabling designers to address the unique requirements of diverse IoT deployments. The AIoT platform supports applications with rigorous demands for power efficiency and cost-effectiveness, ensuring swift time-to-market and reduced development cycles. With a collaborative ecosystem of package design, board evaluation, and software, it paves the way for innovative IoT solutions that seamlessly integrate advanced technologies into everyday devices.
ResQuant's Cyclone V FPGA with an integrated Post-Quantum Cryptography (PQC) processor is designed to provide a quantum-safe backbone for secure systems. Equipped with a complete set of NIST PQC cryptography suite, this FPGA offers straightforward integration with existing hardware and software architectures, particularly beneficial for validating quantum-secure applications. This FPGA solution provides a practical platform for testing and deploying post-quantum algorithms, making it a preferred choice for organizations looking to explore these next-gen security protocols. The integration of a PQC processor ensures that systems built on this FPGA can withstand potential quantum computing threats, securing data transmission and storage for future technologies. It's suitable for applications needing robust proof-of-concept validation of quantum-safe innovations, supporting an array of configurations for industry-specific applications. Given its comprehensive cryptography suite and integration capabilities, ResQuant's Cyclone V FPGA stands as a vital tool for security innovators paving the way to a quantum-resistant future.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
The PUFcc is an advanced Crypto Coprocessor that amalgamates high-level cryptographic capabilities with a robust Hardware Root of Trust foundation. This IP module is thoroughly equipped with a full suite of cryptographic algorithms certified by NIST CAVP and compliant with OSCCA standards, tailored to fulfill complex and diverse IoT security needs. The coprocessor enhances security measures across multiple layers by integrating seamless key management and secure boot functionalities within its core operations, thus expanding security boundaries to external flash and other system components. Designed for ease of integration, PUFcc simplifies the process with built-in interfaces for swift memory access and data processing, bolstering system architecture with programmable flexibility to adopt evolving security protocols.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
The MACSEC Core provides an essential building block for implementing Ethernet data security, supporting protocols crucial for protecting data at the MAC layer in network infrastructure. It ensures confidentiality and integrity of the communications, making it invaluable for environments where data transmission security is paramount. A vital tool for network security, the MACSEC Core integrates seamlessly into various network processors, offering robust security for both small-scale and extensive network architectures. It stands out for its efficiency in encrypting and authenticating Ethernet packets, ensuring data remains protected from eavesdropping and unauthorized access. Designed for versatile network applications, the MACSEC Core can easily adapt to existing network configurations, enabling quick deployment and teeming with existing systems, thereby enhancing overall network security without extensive reconfigurations.
The G13/G13X series is tailored for 512B correction blocks, particularly used in NAND setups with 2KB to 4KB page sizes. While both variants are crafted to manage the demands of SLC NAND transitions to finer geometries, the G13X allows for correction of a higher number of errors. Designed to fit seamlessly into existing controller architectures, it enables extensions of current hardware and software capabilities without extensive new investments. It offers area optimization through parameter adjustments and supports a range of channel configurations for broad applicability.
The Turbo Encoder and Decoder cores by Creonic are engineered to deliver high efficiency in error correction, catering to standards like DVB-RCS2 and 4G LTE. These cores are vital in systems where low latency and high throughput are crucial, such as mobile communications and satellite transponders. Turbo coding technology is renowned for its capacity to approach the Shannon limit, offering near-optimal performance. Creonic's Turbo solutions are meticulously designed to support a wide gamut of applications from space communications to terrestrial wireless networks. Their enhanced algorithms allow for simplified integration and operational efficiency, drastically reducing the error rate in data transmission. The cores are particularly beneficial in environments that encounter significant noise and interference. By using these Turbo Cores, businesses can optimize their communication systems, thereby minimizing the engineering challenges related to complex transmission environments. These products are a testament to Creonic’s expertise in providing robust, versatile solutions that can be tailored to meet very specific customer needs.
The Cryptographic Core offers a comprehensive suite of classical cryptographic solutions. This product leverages well-established algorithms like AES for symmetric encryption and ECC for asymmetric encryption. Its design caters to both high and low-end applications, ensuring compatibility across various devices. This core is crucial for maintaining confidentiality and integrity in systems where traditional cryptography still reigns supreme. With the increasing vulnerability posed by advancing technology, including potential quantum threats, this Cryptographic Core provides secure encryption and decryption processes. Utilizing advanced algorithms such as RSA and variants of elliptic curve cryptography (ECC), it supports the secure exchange of information. Despite looming quantum computing challenges, many elements of classical cryptography remain effective and secure. The Cryptographic Core stands as a reliable option while industries transition towards more robust quantum-safe systems. It offers flexibility and adaptability, accommodating specific security needs through customization and configuration for various performance levels.
Helion Technology offers industry-standard AES solutions effective for high data security applications across various industries. Their AES cores, used globally in commercial developments, can perform encryption and decryption using 128-bit, 192-bit, or 256-bit keys, depending on the intended security level. These cores cater to needs ranging from ultra-low area usage and data rates to top-tier multi-gigabit applications. Helion’s AES cores are distinguished by their ability to deliver performance close to that of ASICs when programmed into FPGAs like those from Xilinx, Altera, Microsemi, and Lattice. Clients have access to a series of AES engine families that cover an array of requirements from ultra-low size to very high-speed executions. The cores are designed to seamlessly integrate into any design, emphasizing user-friendliness and flexibility. They cater to multiple modes, such as CBC, CFB, CTR, and others, with validated solutions for applications needing hardware acceleration of the basic AES algorithm. This portfolio further extends to specialized configurations for advanced applications like AES-CCM, AES-GCM, and those needing key wrapping or supporting communication protocols like IPsec and SSL.
NeoPUF by eMemory Technology is a pioneering hardware security solution utilizing Physical Unclonable Function (PUF) technology. Designed to provide robust protection against unauthorized access and duplication, NeoPUF offers a unique security feature by exploiting the natural variability in silicon characteristics. This randomness is used to generate device-specific keys that are virtually impossible to replicate, ensuring a high level of security for sensitive data and cryptographic processes. NeoPUF's architecture supports a variety of security applications, including secure key storage and identity authentication. Its scalability and flexibility allow it to be integrated across different process nodes, making it an essential security element in IoT devices, automotive security systems, and other critical sectors requiring stringent cybersecurity measures.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
AES-GCM is an innovative authenticated encryption technique, employing universal hashing in a binary Galois field to secure data with concurrent privacy and authentication. Known for enabling very high data rates thanks to pipeline and parallel processing efficiencies, AES-GCM is used in a variety of networking and storage applications. This method is recognized by several standards, including MACsec and ANSI Fibre Channel protocols, offering unmatched data protection across high-speed environments. Helion's AES-GCM offerings span throughput requirements from modest 50Mbps to beyond 40Gbps, accommodating diverse performance and area constraints without sacrificing efficiency. These cores are meticulously optimized for major target technologies like Altera, Microsemi, and Xilinx FPGAs, as well as ASIC implementations, ensuring compatibility and high performance across platforms. Each AES-GCM version is tweaked for particular throughput needs while maintaining a compact logic footprint, reflecting Helion's engineering precision and quality. Whether for low or ultra-high bandwidth demands, Helion's solutions present robust encryption capabilities, underscored by ease of integration and operation benefits.
The IPSEC Core by Algotronix is designed to secure IP communications by providing robust encryption and authentication mechanisms. Essential for ensuring data confidentiality and integrity over IP networks, this core is suitable for embedding into network devices and systems aimed at safeguarding data against potential interception or tampering. Catering to a broad range of IP-based communication systems, the IPSEC Core offers flexibility and reliability, making it a preferred choice for developers focusing on secure data exchange methods. The ease of integration allows for its deployment in both new and existing network architectures, underpinning secure transmissions across increasingly complex digital environments. Its wide acceptance and deployment in secure communications underscore the IPSEC Core's effectiveness in delivering critical security features, thus supporting enterprises in protecting sensitive data across diverse network topologies.
The QDID PUF provides a unique identity based directly on quantum effects observed in standard CMOS processes. These identities are inherently secure due to the randomness that originates from variations in device oxide thickness and defect distribution. By leveraging such inherent unpredictability, QDID PUFs form a robust basis for hardware root-of-trust. This IP simplifies secure provisioning by avoiding traditional factory-based key injections, thereby reducing reliance on external secure manufacturing processes. QDID PUFs also ensure that identities are not stored in memory, instead being generated dynamically. This characteristic defends against side-channel attacks exploiting memory vulnerabilities. Additionally, the high entropy of the quantum effects they harness offers robust resistance to machine learning-based entropy source attacks, generating customizable security seeds up to 256 bits. Boosting its security, the QDID PUF integrates strategic countermeasures against side-channel attacks and has been certified to comply with stringent standards like PSA Level 2 and CC EAL4+. It supports wide-ranging environmental conditions and boasts extensive process node compatibility with major fabrication technologies. Typically used for key generation and device authentication, it represents the vanguard of cryptographic consistency for post-quantum applications.
The Customizable Cryptography Accelerator by ResQuant is designed to cater to diverse client needs, offering a broad range of configurable options. It integrates seamlessly with the complete set of NIST post-quantum cryptography standards, including algorithms like Dilithium, Kyber, and XMSS. This flexibility extends further by allowing customers to incorporate their own algorithms. This cryptography accelerator is straightforward to tailor in terms of performance and size, helping cater to varied application requirements. Its design incorporates defenses against various side-channel attacks, although some features like resistance to Differential Power Analysis (DPA), timing attacks, and Simple Power Analysis (SCA) are in development. The adaptability of the accelerator is enhanced with AXI 4 compatibility, ensuring it can be easily integrated into complex system-on-chip designs. Customers can expect a future-proof, versatile cryptographic solution that addresses both existing and emerging cybersecurity challenges. This product represents a significant advancement for organizations transitioning to quantum-safe security solutions.
Digital Systems and Security Solutions offer cutting-edge digital IP solutions that encompass security features vital for modern applications. These systems are designed to enhance encryption and data protection capabilities, ensuring a high level of security for sensitive information. By integrating advanced digital logic and security protocols, they are adept at handling complex computational processes while maintaining optimum performance. These solutions are integral for applications requiring stringent security standards, facilitating safe and efficient data handling and processing, thereby aligning with the industry's best practices for digital reliability and safety.
FortiPKA-RISC-V is a high-speed public key accelerator that enhances the efficiency of cryptographic tasks by offloading complex operations from the main CPU. It is particularly effective for tasks involving large integer arithmetic typical in asymmetric cryptography. The design eliminates the need for data transformations linked to Montgomery domain conversion, boosting performance significantly. The RISC-V core allows flexible integration using interfaces such as AMBA AXI4, APB, and others. It supports a wide range of cryptographic algorithms including RSA, ECDSA, and SM2, maintaining resilience against side-channel attacks through robust technological methodologies. This solution proves ideal for embedded systems in IoT, automotive, and payment systems, offering high configurability to align with specific performance and area requirements.
This IP focuses on advancing encryption methods to counteract threats posed by quantum computing. By using algorithms robust enough to withstand the computational power of quantum machines, the Post-Quantum Cryptography IP ensures the continued confidentiality of sensitive data long into the future. Collaboration with industry and academia allows Secure-IC to be at the cutting edge of this technological evolution.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
The QUIC Protocol Core from Design Gateway introduces a high-security data communication solution using the latest QUIC protocol with TLS 1.3 support. Implemented entirely in hardware, this core eliminates the reliance on CPU processing for complex encryption and data communication tasks. It enables faster client-server negotiations and reduces connection time, making it suitable for real-time applications that require secure, low-latency connections. Industries focused on speed and security, such as financial services and content delivery networks, will find this IP core exceptionally beneficial for enhancing data throughput and security.
Green IP Core's Fault Resistant AES Core elevates data encryption by combining robust cryptographic standards with enhanced fault tolerance. This technology is engineered to offer both security and reliability, addressing vulnerabilities that can arise from potential soft errors in cryptographic operations. This core is ideal for deployment in environments where faults can interfere with traditional AES implementations, such as in extreme environmental conditions or where high electromagnetic interference is present. It leverages intelligent error management, which preemptively identifies and corrects any anomalies, ensuring that encryption processes remain intact and reliable. Fault resistance in this core does not compromise its speed or efficiency. It continues to provide high-throughput encryption capabilities while ensuring that all security procedures are maintained under varying operational stresses. This makes it a valuable asset for sectors that require uncompromised data security, particularly where regulatory compliance is a factor, such as in healthcare, defense, and financial services.
Ocean Logic's AES Encryption Core represents a robust and reliable solution for securing data across numerous platforms. Renowned for its certification and extensive validation in silicon on both FPGA and ASIC, this IP core has established credibility and trust among a diversified customer base. The AES core has seen nearly 60 successful implementations, underlining its reliability in providing robust data security. This encryption core complies with stringent security standards, ensuring data integrity and confidentiality. It is subject to Australia's Export Control regulations, qualifying it for international deployment across numerous key markets worldwide. Such widespread recognition indicates its versatility and adaptability to meet various encryption needs. For businesses and organizations prioritizing data security, Ocean Logic's AES Encryption Core offers a proven, high-performance solution. Its design facilitates seamless integration into existing systems, providing a comprehensive encryption capability while maintaining operational efficiency. The IP core stands as an ideal choice for companies looking to fortify their security measures with a trusted, efficient, and scalable encryption architecture.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!