All IPs > Processor > Processor Cores
Processor cores are fundamental components in central processing units (CPUs) and systems-on-chip (SoCs) for a myriad of digital devices ranging from personal computers and smartphones to more specialized equipment like embedded systems. Within the category of Processor Cores, you'll find a diverse selection of semiconductor IPs tailored to meet the varying demands of speed, power efficiency, and processing capability required by today's technology-driven world.
Our Processor Cores category provides an extensive library of semiconductor IPs, enabling designers to integrate powerful, efficient, and scalable cores into their projects. These IPs are essential for firms aiming to innovate and achieve a competitive edge within the fast-evolving tech landscape. Whether you're developing high-performance computing solutions or aiming for energy-efficient mobile gadgets, our processor core IP offerings are designed to support a wide range of architectures, from single-core microcontrollers to multi-core, multi-threaded processors.
One of the primary uses of processor core IPs is to define the architecture and functions of a core within a chip. These IPs provide the blueprint for building custom processors that can handle specific applications efficiently. They cover a broad spectrum of processing needs, including general-purpose processing, digital signal processing, and application-specific processing tasks. This flexibility allows developers to choose IPs that align perfectly with their product specifications, ensuring optimal performance and power usage.
In our Processor Cores category, you'll discover IPs suited for creating processors that power everything from wearables and IoT devices to servers and network infrastructure hardware. By leveraging these semiconductor IPs, businesses can significantly reduce time-to-market, lower development costs, and ensure that their products remain at the forefront of technology innovation. Each IP in this category is crafted to meet industry standards, providing robust solutions that integrate seamlessly into various technological environments.
The Metis AIPU PCIe AI Accelerator Card is engineered for developers demanding superior AI performance. With its quad-core Metis AIPU, this card delivers up to 214 TOPS, tackling challenging vision applications with unmatched efficiency. The PCIe card is designed with user-friendly integration in mind, featuring the Voyager SDK software stack that accelerates application deployment. Offering impressive processing speeds, the card supports up to 3,200 FPS for ResNet-50 models, providing a competitive edge for demanding AI tasks. Its design ensures it meets the needs of a wide array of AI applications, allowing for scalability and adaptability in various use cases.
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
The Yitian 710 Processor represents T-Head Semiconductor's debut in Arm server chip development. It integrates cutting-edge architecture to deliver exceptional computing performance and efficiency. Designed for high-demand environments, this processor uses advanced Armv9 instruction set architecture, allowing for increased compatibility and robust performance metrics. With a design that maximizes throughput while minimizing power consumption, Yitian 710 is well-suited for cloud services and data-driven applications. The processor is engineered with a 2.5D packaging design, which enables enhanced performance through a dual-die structure. Its architecture includes 128 high-performance Armv9 CPU cores, each featuring a substantial cache and memory management capabilities, fostering smooth and efficient processing of large data volumes. This setup ensures high-speed data access and transfer, making it ideal for modern computational demands. The Yitian 710 Processor's I/O subsystem supports PCIe 5.0, providing substantial bandwidth to accommodate heavy data loads and improve interface interaction. This expansion capability makes the T-Head Yitian 710 Processor a versatile and scalable solution, designed to address the requirements of AI, big data analytics, and enterprise-level computing. Its power efficiency and support for high-frequency operations guarantee optimal performance in energy-conscious and high-load environments.
The Veyron V2 CPU represents Ventana's second-generation RISC-V high-performance processor, designed for cloud, data center, edge, and automotive applications. This processor offers outstanding compute capabilities with its server-class architecture, optimized for handling complex, virtualized, and cloud-native workloads efficiently. The Veyron V2 is available as both IP for custom SoCs and as a complete silicon platform, ensuring flexibility for integration into various technological infrastructures. Emphasizing a modern architectural design, it includes full compliance with RISC-V RVA23 specifications, showcasing features like high Instruction Per Clock (IPC) and power-efficient architectures. Comprising of multiple core clusters, this CPU is capable of delivering superior AI and machine learning performance, significantly boosting throughput and energy efficiency. The Veyron V2's advanced fabric interconnects and extensive cache architecture provide the necessary infrastructure for high-performance applications, ensuring broad market adoption and versatile deployment options.
The Quadric Chimera General Purpose Neural Processing Unit (GPNPU) delivers unparalleled performance for AI workloads, characterized by its ability to handle diverse and complex tasks without requiring separate processors for different operations. Designed to unify AI inference and traditional computing processes, the GPNPU supports matrix, vector, and scalar tasks within a single, cohesive execution pipeline. This design not only simplifies the integration of AI capabilities into system-on-chip (SoC) architectures but also significantly boosts developer productivity by allowing them to focus on optimizing rather than partitioning code. The Chimera GPNPU is highly scalable, supporting a wide range of operations across all market segments, including automotive applications with its ASIL-ready versions. With a performance range from 1 to 864 TOPS, it excels in running the latest AI models, such as vision transformers and large language models, alongside classic network backbones. This flexibility ensures that devices powered by Chimera GPNPU can adapt to advancing AI trends, making them suitable for applications that require both immediate performance and long-term capability. A key feature of the Chimera GPNPU is its fully programmable nature, making it a future-proof solution for deploying cutting-edge AI models. Unlike traditional NPUs that rely on hardwired operations, the Chimera GPNPU uses a software-driven approach with its source RTL form, making it a versatile option for inference in mobile, automotive, and edge computing applications. This programmability allows for easy updating and adaptation to new AI model operators, maximizing the lifespan and relevance of chips that utilize this technology.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
The xcore.ai platform by XMOS is a versatile, high-performance microcontroller designed for the integration of AI, DSP, and real-time I/O processing. Focusing on bringing intelligence to the edge, this platform facilitates the construction of entire DSP systems using software without the need for multiple discrete chips. Its architecture is optimized for low-latency operation, making it suitable for diverse applications from consumer electronics to industrial automation. This platform offers a robust set of features conducive to sophisticated computational tasks, including support for AI workloads and enhanced control logic. The xcore.ai platform streamlines development processes by providing a cohesive environment that blends DSP capabilities with AI processing, enabling developers to realize complex applications with greater efficiency. By doing so, it reduces the complexity typically associated with chip integration in advanced systems. Designed for flexibility, xcore.ai supports a wide array of applications across various markets. Its ability to handle audio, voice, and general-purpose processing makes it an essential building block for smart consumer devices, industrial control systems, and AI-powered solutions. Coupled with comprehensive software support and development tools, the xcore.ai ensures a seamless integration path for developers aiming to push the boundaries of AI-enabled technologies.
The Metis AIPU M.2 Accelerator Module is designed for devices that require high-performance AI inference in a compact form factor. Powered by a quad-core Metis AI Processing Unit (AIPU), this module optimizes power consumption and integration, making it ideal for AI-driven applications. With a dedicated memory of 1 GB DRAM, it enhances the capabilities of vision processing systems, providing significant boosts in performance for devices with Next Generation Form Factor (NGFF) M.2 sockets. Ideal for use in computer vision systems and more, it offers hassle-free integration and evaluation with Axelera's Voyager SDK. This accelerator module is tailored for any application seeking to harness the power of AI processing efficiently. The Metis AIPU M.2 Module streamlines the deployment of AI applications, ensuring high performance with reduced power consumption.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The RV12 RISC-V Processor is a highly customizable single-issue, single-core CPU adhering to the RV32I and RV64I standards of the RISC-V architecture. It is designed specifically for use in embedded applications, offering flexibility and scalability for various hardware environments. The processor supports an open-source instruction set, making it well-suited for a wide range of computational needs while remaining efficient and compact. This processor core is optimized to provide a balanced blend of performance and power consumption, which is critical for embedded systems. Its design supports integration into a variety of designs, from simple standalone systems to complex, multi-component systems. With extensive documentation and a complete testbench provided, the RV12 processor ensures that developers can deploy it with minimal integration challenges, leveraging its configurable parameters to meet specific project requirements.
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
Designed for minimal power consumption, the Tianqiao-70 is a 64-bit RISC-V CPU core that harmonizes efficiency with energy savings. Targeting primarily the commercial space, this CPU core supports applications that demand lower power usage without compromising performance outputs. It stands out in the fields of mobile and desktop processing, AI learning, and other demanding applications that require consistent yet power-efficient computing. Architected to provide maximum throughput with minimum power draw, it is essential for energy-critical systems. The Tianqiao-70 showcases StarFive's commitment to optimizing for efficiency, enabling mobile, desktop, and AI platforms to leverage low power requirements effectively. This makes it a compelling choice for developers aiming to integrate eco-friendly solutions in their products.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
Micro Magic's Ultra-Low-Power 64-Bit RISC-V Core is engineered for superior energy efficiency, consuming a mere 10mW while operating at a clock speed of 1GHz. This processor core is designed to excel under low voltage conditions, delivering high performance without compromising on power conservation. It is ideal for applications requiring prolonged battery life or those operating in energy-sensitive environments. This processor integrates Micro Magic's advanced design methodologies, allowing for operation at frequencies up to 5GHz when necessary. The RISC-V Core capabilities are enhanced by solid construction, ensuring reliability and robust performance across various use-cases, making it an adaptable solution for modern electronic designs. With its cutting-edge design, this RISC-V core supports rapid deployment in numerous applications, especially in areas demanding high computational power alongside reduced energy usage. Micro Magic's advanced techniques ensure that this core is not only fast but also supports scalable integration into various systems with ease.
The SiFive Intelligence X280 is a high-performance CPU core tailored for advanced AI and ML workloads, featuring sophisticated vector and matrix compute capabilities. It offers developers a vast toolkit for crafting efficient AI solutions that can be deployed at the edge, thanks to a focus on providing both high performance and scalability. The X280’s architecture allows for the integration of custom accelerator engines, making it highly adaptable to shifting demands in AI technology. Boasting advanced vector compute engines, the X280 is designed to handle large datasets efficiently, ideal for inference tasks and model training. This processor stands out with its high bandwidth interconnects, facilitating seamless data flow and control across custom computing engines integrated using RISC-V custom instructions. Its capabilities mark it as a versatile choice for complex machine learning applications spanning various industry segments. The SiFive Intelligence X280 supports a broad range of tools and frameworks designed to simplify deployment and integration. By using a RISC-V architecture, it promotes open innovation and reduces dependency on traditional proprietary models. This freedom translates into increased optimization opportunities, enabling rapid iteration and development cycles critical for maintaining a competitive edge in AI technology.
The RISC-V Core-hub Generators from InCore are tailored for developers who need advanced control over their core architectures. This innovative tool enables users to configure core-hubs precisely at the instruction set and microarchitecture levels, allowing for optimized design and functionality. The platform supports diverse industry applications by facilitating the seamless creation of scalable and customizable RISC-V cores. With the RISC-V Core-hub Generators, InCore empowers users to craft their own processor solutions from the ground up. This flexibility is pivotal for businesses looking to capitalize on the burgeoning RISC-V ecosystem, providing a pathway to innovation with reduced risk and cost. Incorporating feedback from leading industry partners, these generators are designed to lower verification costs while accelerating time-to-market for new designs. Users benefit from InCore's robust support infrastructure and a commitment to simplifying complex chip design processes. This product is particularly beneficial for organizations aiming to integrate RISC-V technology efficiently into their existing systems, ensuring compatibility and enhancing functionality through intelligent automation and state-of-the-art tools.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
The Azurite Core-hub by InCore Semiconductors is a sophisticated solution designed to offer scalable RISC-V SoCs with high-speed secure interconnect capabilities. This processor is tailored for performance-demanding applications, ensuring that systems maintain robust security while executing tasks at high speeds. Azurite leverages advanced interconnect technologies to enhance the communication between components within a SoC, making it ideal for industries that require rapid data transfer and high processing capabilities. The core is engineered to be scalable, supporting a wide range of applications from edge AI to functional safety systems, adapting seamlessly to various industry needs. Engineered with a focus on security, the Azurite Core-hub incorporates features that protect data integrity and system operation in a dynamic technological landscape. This makes it a reliable choice for companies seeking to integrate advanced RISC-V architectures into their security-focused applications, offering not just innovation but also peace of mind with its secure design.
The eSi-1600 is a 16-bit CPU core designed for cost-sensitive and power-efficient applications. It accords performance levels similar to that of 32-bit CPUs while maintaining a system cost comparable to 8-bit processors. This IP is particularly well-suited for control applications needing limited memory resources, demonstrating excellent compatibility with mature mixed-signal technologies.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The eSi-1650 is a compact, low-power 16-bit CPU core integrating an instruction cache, making it an ideal choice for mature process nodes reliant on OTP or Flash program memory. By omitting large on-chip RAMs, the IP core optimizes power and area efficiency and permits the CPU to capitalize on its maximum operational frequency beyond OTP/Flash constraints.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The RISC-V Core IP developed by AheadComputing Inc. stands out in the field of 64-bit application processors. Designed to deliver exceptional per-core performance, this processor is engineered with the highest standards to maximize the Instructions Per Cycle (IPC) efficiency. AheadComputing's RISC-V Core IP is continuously refined to address the growing demands of high-performance computing applications. The innovative architecture of this core allows for seamless execution of complex algorithms while achieving superior speed and efficiency. This design is crucial for applications that require fast data processing and real-time computational capabilities. By integrating advanced power management techniques, the RISC-V Core IP ensures energy efficiency without sacrificing performance, making it suitable for a wide range of electronic devices. Anticipating future computing needs, AheadComputing's RISC-V Core IP incorporates state-of-the-art features that support scalability and adaptability. These features ensure that the IP remains relevant as technology evolves, providing a solid foundation for developing next-generation computing solutions. Overall, it embodies AheadComputing’s commitment to innovation and performance excellence.
RAIV represents Siliconarts' General Purpose-GPU (GPGPU) offering, engineered to accelerate data processing across diverse industries. This versatile GPU IP is essential in sectors engaged in high-performance computing tasks, such as autonomous driving, IoT, and sophisticated data centers. With RAIV, Siliconarts taps into the potential of the fourth industrial revolution, enabling rapid computation and seamless data management. The RAIV architecture is poised to deliver unmatched efficiency in high-demand scenarios, supporting massive parallel processing and intricate calculations. It provides an adaptable framework that caters to the needs of modern computing, ensuring balanced workloads and optimized performance. Whether used for VR/AR applications or supporting the back-end infrastructure of data-intensive operations, RAIV is designed to meet and exceed industry expectations. RAIV’s flexible design can be tailored to enhance a broad spectrum of applications, promising accelerated innovation in sectors dependent on AI and machine learning. This GPGPU IP not only underscores Siliconarts' commitment to technological advancement but also highlights its capability to craft solutions that drive forward computational boundaries.
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
The N Class RISC-V CPU IP from Nuclei is tailored for applications where space efficiency and power conservation are paramount. It features a 32-bit architecture and is highly suited for microcontroller applications within the AIoT realm. The N Class processors are crafted to provide robust processing capabilities while maintaining a minimal footprint, making them ideal candidates for devices that require efficient power management and secure operations. By adhering to the open RISC-V standard, Nuclei ensures that these processors can be seamlessly integrated into various solutions, offering customizable options to fit specific system requirements.
The SCR3 Microcontroller Core is an efficient solution built for microcontroller-based applications, offering a fine balance between performance and resource utilization. Designed with a 5-stage in-order pipeline, it enhances instruction throughput without compromising on power efficiency. This core accommodates both 32-bit and 64-bit configurations, making it versatile for a variety of embedded applications. It also incorporates privilege modes and an MPU, enhancing control and security measures in embedded systems. The inclusion of L1 and L2 caches further optimizes data processing and retrieval, catering to high-speed requirements. SCR3 is relevant to diverse market segments such as industrial, automotive, and IoT, where the need for reliable and efficient processing units is paramount. Its configurability and adaptability make it a preferred choice for developers aiming to integrate high-performance microcontroller cores with robust architectural features that ensure seamless application execution.
As an advanced solution, the SCR9 Processor Core is built to deliver top-of-the-line performance for enterprise and high-performance computing applications. Featuring a 12-stage dual-issue out-of-order pipeline, it caters to complex processing tasks with exceptional speed and accuracy. Supporting hypervisor capabilities and a virtual processing unit, the SCR9 core is designed for scalability, handling up to 16 cores. Its coherent cache system ensures swift and consistent data flow, enhancing overall system reliability and throughput. Targeted at applications across AI, data centers, and mobile devices, this core embodies flexibility and power. The combination of virtualization, comprehensive caching, and high computational performance makes SCR9 an optimal choice for environments where maintaining high efficiency and power balance is essential.
Crafted for high-performance demands, the SCR6 Microcontroller Core is targeted at applications that require superior computational power. It features a 12-stage dual-issue out-of-order pipeline that effectively boosts instruction processing and optimizes execution efficiency. The SCR6 core supports 64-bit architectures and is equipped with a high-performance floating-point unit (FPU), catering to applications in sectors like industrial automation, IoT, and telecom. Its advanced architectural design ensures swift data handling and seamless integration, making it suitable for complex embedded applications. This core is also marked by its energy-efficient attributes while ensuring robust performance, adhering to the need for low-power consumption in various embedded systems. With its flexible design, the SCR6 offers developers ample opportunity for customization and optimization, aligning well with specific project requirements.
The Codasip RISC-V BK Core Series is designed to offer flexible and high-performance core options catering to a wide range of applications, from low-power tasks to intricate computational needs. This series achieves optimal balance in power consumption and processing speed, making it suitable for applications demanding energy efficiency without compromising performance. These cores are fully RISC-V compliant, allowing for easy customizations to suit specific needs by modifying the processor's architecture or instruction set through Codasip Studio. The BK Core Series provides a streamlining process for developing precise computing solutions, ideal for IoT edge devices and sensor controllers where both small area and low power are critical. Moreover, the BK Core Series supports architectural exploration, enabling users to optimize the core design specifically tailored to their applications. This capability ensures that each core delivers the expected power, efficiency, and performance metrics required by modern technological solutions.
EverOn is an ultra-low voltage SRAM developed by sureCore to cater to modern applications requiring extensive dynamic and static power savings. Built on the 40ULP BULK CMOS process, EverOn achieves up to 80% reductions in dynamic power utilization while cutting static power draw by 75%, making it highly efficient for IoT and wearable technology. Operational from 0.6V to 1.21V, EverOn supports a cycle time as short as 20MHz at its lowest voltage, scaling impressively to over 300MHz at its highest. This voltage scaling unlocks robust performance capabilities in energy-constrained environments, aligning with the trend towards increasingly sophisticated, low-power always-on devices. EverOn incorporates advanced techniques such as subdividing memory into banks for flexible power management and synchronized single-port operation, which enhances versatility. Its high-density bit cells facilitate reduced area footprints while the patented SMART-Assist technology ensures robust operation even at the retention voltage, supporting extended battery life applications in emerging markets.
The SCR1 Microcontroller Core by Syntacore is crafted for deeply embedded applications, providing a robust open-source solution. This core is engineered with a 4-stage in-order pipeline, ensuring efficient instruction processing and minimal latency. Its compact design makes it ideal for applications requiring high performance in space-constrained environments. SCR1 is a 32-bit microcontroller core that aligns with the requirements of embedded systems for industries like industrial automation, IoT, and automotive sectors. Its architecture ensures low power consumption while maintaining reliable operation. This core is particularly suitable for control systems and sensor fusion applications, where space and energy efficiency are critical. The simplicity of the SCR1 Core facilitates easy integration into larger complex systems, making it a versatile building block for embedded hardware solutions. With its focus on open-source compatibility, it supports a myriad of custom modifications, allowing engineers to tailor its functionality to suit specific project needs.
The Y180 is a streamlined microprocessor featuring around 8K gates, specifically designed as a clone of the Zilog Z180 CPU. Tailored for applications requiring compact size and efficient performance, this CPU-only design is a suitable replacement for legacy systems needing updates with reliable components. As a lightweight processor, the Y180 supports fundamental computational tasks while maintaining compatibility with existing infrastructure designed for Z180 systems. Its straightforward design facilitates easy integration, making it desirable for projects necessitating simplicity and lower power usage. Given its specialized purpose, the Y180 serves niche markets where updating older technology cost-effectively without compromising performance is a priority. It leverages Systemyde's depth of microprocessor design expertise to deliver practicality and adaptability.
The NaviSoC is a versatile system-on-chip that revolutionizes GNSS applications by combining a high-performance receiver with an application processor. Designed for precision-demanding tasks, NaviSoC provides centimeter-level accuracy, making it ideal for applications such as autonomous drones and smart agriculture. It boasts a high update rate and low power consumption, crucial for real-time tracking and energy-efficient operations. This system-on-chip is enhanced with a RISC-V MCU, expanding its capabilities for various applications in asset tracking and industrial navigation. Its flexibility is evident in its support for all-constellation, all-band GNSS signals, providing global coverage and reliability. With fast time-to-first-fix capabilities and integration features such as dead reckoning and RTK, NaviSoC can handle challenging environments, ensuring consistent performance. NaviSoC's architecture integrates numerous peripherals and interfaces, optimized for seamless connectivity and extended functionality. Whether for UAV operations or time synchronization, the NaviSoC is equipped to address the most demanding requirements of today's connected world. Its adaptability is epitomized by its support for embedded flash and a dedicated software development kit (SDK), allowing for customization and rapid deployment in bespoke applications. This GNSS solution is also supported by a suite of development tools and evaluation boards, ensuring that developers can efficiently bring applications from concept to reality. As a flagship product of ChipCraft, NaviSoC underlines the company's commitment to delivering state-of-the-art semiconductor solutions.
The SCR7 Application Core by Syntacore is tailored for high-performance applications, featuring a 12-stage dual-issue out-of-order pipeline which ensures lag-free processing and enhanced computational efficiency. With a 64-bit architecture, it supports up to eight cores, making it suitable for demanding environments like artificial intelligence, machine learning, and enterprise computing. The core is Linux-capable, with cache coherence capabilities ensuring seamless memory access across multi-core systems. This application core is ideal for data-intensive tasks, equipped to handle large volumes of data with precision and speed. SCR7's support for a wide range of operating systems and environments makes it highly versatile, allowing deployment across various market segments requiring cutting-edge processing and application capabilities.
The Veyron V1 is a high-performance RISC-V CPU designed to meet the rigorous demands of modern data centers and compute-intensive applications. This processor is tailored for cloud environments requiring extensive compute capabilities, offering substantial power efficiency while optimizing processing workloads. It provides comprehensive architectural support for virtualization and efficient task management with its robust feature set. Incorporating advanced RISC-V standards, the Veyron V1 ensures compatibility and scalability across a wide range of industries, from enterprise servers to high-performance embedded systems. Its architecture is engineered to offer seamless integration, providing an excellent foundation for robust, scalable computing designs. Equipped with state-of-the-art processing cores and enhanced vector acceleration, the Veyron V1 delivers unmatched throughput and performance management, making it suitable for use in diverse computing environments.
The Nuclei N300 Series Processor Core is a commercial RISC-V Processor Core Series designed by Nuclei System Technology for microcontroller, IoT, or other low-power applications. The N300 Series offers advanced features such as dual-issue capability, configurable instruction sets including ISA extensions, low-power management modes, and comprehensive debug support. It also includes support for ECC, TEE, and scalable local memory interfaces. Enhanced features like ETRACE and customizable instructions via the NICE interface further extend its capabilities.
The Maverick-2 Intelligent Compute Accelerator (ICA) by Next Silicon represents a transformative leap in high-performance compute architecture. It seamlessly integrates into HPC systems with a pioneering software-defined approach that dynamically optimizes hardware configurations based on real-time application demands. This enables high efficiency and unparalleled performance across diverse workloads including HPC, AI, and other data-intensive applications. Maverick-2 harnesses a 5nm process technology, utilizing HBM3E memory for enhanced data throughput and efficient energy usage.\n\nBuilt with developers in mind, Maverick-2 supports an array of programming languages such as C/C++, FORTRAN, and OpenMP without the necessity for proprietary stacks. This flexibility not only mitigates porting challenges but significantly reduces development time and costs. A distinguishing feature of Maverick-2 is its real-time telemetry capabilities that provide valuable insights into performance metrics, allowing for refined optimizations during execution.\n\nThe architecture supports versatile interfaces such as PCIe Gen 5 and offers configurations that accommodate complex workloads using either single or dual-die setups. Its intelligent algorithms autonomously identify computational bottlenecks to enhance throughput and scalability, thus future-proofing investments as computing demands evolve. Maverick-2's utility spans various sectors including life sciences, energy, and fintech, underlining its adaptability and high-performance capabilities.
AON1100 marks a significant leap in edge AI processing for voice and sensor operations. Meticulously engineered for energy efficiency, this chip operates on less than 260µW while achieving over 90% accuracy even in low signal-to-noise environments. It is perfect for always-on gadgets demanding constant reliability and precision, especially under challenging conditions.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
The SiFive Performance series represents a leap forward in computing efficiency, featuring RISC-V processors designed for peak performance and high throughput across various applications. These 64-bit out-of-order cores come equipped with up to 256-bit vectors, optimizing them for data center workloads, web services, multimedia processing, and consumer electronics like smart devices. The Performance series balances cutting-edge energy efficiency with robust core capabilities, making it suited for AI workloads while minimizing power and spatial requirements. The SiFive Performance family’s design includes flexible core configurations that empower users to mix and match performance levels according to their specific needs. This approach results in streamlined and powerful processors suitable for a broad spectrum of applications, ranging from mobile devices to complex data center infrastructure. SiFive’s utilization of vector engines enhances AI applications, offering significant computational capability without imposing additional hardware demands. With the ability to expand up to 256 cores and integrate vector computing capabilities, SiFive's Performance series provides a high degree of scalability. Users benefit from enhanced performance density, allowing for the development of next-generation applications that require high levels of processing power within limited physical constraints. This range is an excellent choice for developers looking for efficient, scalable solutions tailored to diverse operational requirements.
The NS Class is Nuclei's crucial offering for applications prioritizing security and fintech solutions. This RISC-V CPU IP securely manages IoT environments with its highly customizable and secure architecture. Equipped to support advanced security protocols and functional safety features, the NS Class is particularly suited for payment systems and other fintech applications, ensuring robust protection and reliable operations. Its design follows the RISC-V standards and is accompanied by customizable configuration options tailored to meet specific security requirements.
Specially engineered for the automotive industry, the NA Class IP by Nuclei complies with the stringent ISO26262 functional safety standards. This processor is crafted to handle complex automotive applications, offering flexibility and rigorous safety protocols necessary for mission-critical transportation technologies. Incorporating a range of functional safety features, the NA Class IP is equipped to ensure not only performance but also reliability and safety in high-stakes vehicular environments.
Tachyum's Prodigy Universal Processor marks a significant milestone as it combines the functionalities of Central Processing Units (CPUs), General-Purpose Graphics Processing Units (GPGPUs), and Tensor Processing Units (TPUs) into a single cohesive architecture. This groundbreaking design is tailored to meet the escalating demands of artificial intelligence, high-performance computing, and hyperscale data centers by offering unparalleled performance, energy efficiency, and high utilization rates. The Prodigy processor not only tackles common data center challenges like elevated power consumption and stagnating processor performance but also offers a robust solution to enhance server utilization and reduce the carbon footprint of massive computational installations. Notably, it thrives on a simplified programming model grounded in coherent multiprocessor architecture, thereby enabling seamless execution of an array of AI disciplines like Explainable AI, Bio AI, and deep machine learning within a single hardware platform.
Y51 microprocessor embeds the 8051 Instruction Set Architecture within a 2-clock machine cycle, streamlining processing for devices adhering to this widely recognized standard. By adopting this efficient architecture, the Y51 ensures compatibility with legacy systems while optimizing performance outcomes. Focused on simplicity and efficiency, the Y51 is ideal for applications within embedded systems where adherence to the 8051 architecture is required. It provides easy system integration due to its standard compliance and operational fluency, becoming a repeat choice for developers maintaining or upgrading applications utilizing older technology. System architects benefit from the Y51’s reliability and processing strength, underscoring Systemyde’s commitment to delivering microprocessors that meet the traditional demands without sacrificing integration ease or flexibility.
Syntacore's SCR4 Microcontroller Core is designed for applications that demand efficient microcontroller solutions with sophisticated features. It incorporates a 5-stage in-order pipeline and includes privilege modes, making it suitable for embedded systems requiring secure and efficient processing. The SCR4 core achieves remarkable performance through features like floating-point unit (FPU) and memory protection unit (MPU), which enhance its capability in handling complex computational tasks. This core also integrates L1 and L2 caches, thereby expediting data access and improving system throughput. Ideal for markets like industrial control systems, automotive electronics, and IoT, the SCR4 core's configurable nature allows for targeted optimizations and design flexibility. Its energy-efficient design ensures compatibility with battery-powered devices and applications where power conservation is essential.
The NX Class RISC-V CPU IP by Nuclei is characterized by its 64-bit architecture, making it a robust choice for storage, AR/VR, and AI applications. This processing unit is designed to accommodate high data throughput and demanding computational tasks. By leveraging advanced capabilities, such as virtual memory and enhanced processing power, the NX Class facilitates cutting-edge technological applications and is adaptable for integration into a vast array of high-performance systems.
The SCR5 Application Core represents a powerful solution for versatile computing demands, offering substantial capabilities for Linux-based applications. It is equipped with a 9-stage in-order pipeline and supports up to four cores, facilitating smooth multitasking and efficient processing. This 64-bit application core is designed with an MMU and integrated L1 and L2 caches, promoting robust memory management and quick data access. Its coherent cache infrastructure further enhances system performance by maintaining data consistency across multi-core configurations. SCR5 is ideally suited for a wide range of markets, including but not limited to artificial intelligence, data analytics, and HPC environments. Its efficient infrastructure supports applications with high data processing and performance requirements, making it a viable option for server-class deployment where reliability and speed are crucial.
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