All IPs > Processor > Processor Cores
Processor cores are fundamental components in central processing units (CPUs) and systems-on-chip (SoCs) for a myriad of digital devices ranging from personal computers and smartphones to more specialized equipment like embedded systems. Within the category of Processor Cores, you'll find a diverse selection of semiconductor IPs tailored to meet the varying demands of speed, power efficiency, and processing capability required by today's technology-driven world.
Our Processor Cores category provides an extensive library of semiconductor IPs, enabling designers to integrate powerful, efficient, and scalable cores into their projects. These IPs are essential for firms aiming to innovate and achieve a competitive edge within the fast-evolving tech landscape. Whether you're developing high-performance computing solutions or aiming for energy-efficient mobile gadgets, our processor core IP offerings are designed to support a wide range of architectures, from single-core microcontrollers to multi-core, multi-threaded processors.
One of the primary uses of processor core IPs is to define the architecture and functions of a core within a chip. These IPs provide the blueprint for building custom processors that can handle specific applications efficiently. They cover a broad spectrum of processing needs, including general-purpose processing, digital signal processing, and application-specific processing tasks. This flexibility allows developers to choose IPs that align perfectly with their product specifications, ensuring optimal performance and power usage.
In our Processor Cores category, you'll discover IPs suited for creating processors that power everything from wearables and IoT devices to servers and network infrastructure hardware. By leveraging these semiconductor IPs, businesses can significantly reduce time-to-market, lower development costs, and ensure that their products remain at the forefront of technology innovation. Each IP in this category is crafted to meet industry standards, providing robust solutions that integrate seamlessly into various technological environments.
Axelera AI's Metis AIPU PCIe AI Accelerator Card is designed to tackle demanding vision applications with its powerful processing capabilities. The card embeds a single Metis AIPU which can deliver up to 214 TOPS, providing the necessary throughput for concurrent processing of high-definition video streams and complex AI inference tasks. This PCIe card is supported by the Voyager SDK, which enhances the user experience by allowing easy integration into existing systems for efficient deployment of AI inference networks. It suits developers and integrators looking for an upgrade to existing infrastructure without extensive modifications, optimizing performance and accelerating AI model deployment. The card’s design prioritizes performance and efficiency, making it suitable for diverse applications across industries like security, transportation, and smart city environments. Its capacity to deliver high frames per second on popular AI models ensures it meets modern digital processing demands with reliability and precision.
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
The Metis AIPU M.2 Accelerator Module from Axelera AI is engineered for applications requiring edge AI computing power in a compact form factor. Leveraging the quad-core Metis AIPU, this module provides efficient AI processing capabilities tailored for real-time analysis and data-intensive tasks in areas like computer vision. Designed to fit into standard NGFF (Next Generation Form Factor) M.2 sockets, it supports a wide range of AI models with dedicated 1GB DRAM memory for optimized performance. This module is especially suitable for systems needing enhanced image and video processing capabilities while maintaining minimal power consumption. The Metis AIPU M.2 Accelerator Module enhances computing architectures by enabling seamless integration of AI for a multitude of industrial and commercial applications. Its efficient design makes it ideal for environments where space is limited, but computational demand is high, ensuring that solutions are both powerful and cost-effective.
The Yitian 710 Processor is T-Head's flagship ARM-based server chip that represents the pinnacle of their technological expertise. Designed with a pioneering architecture, it is crafted for high efficiency and superior performance metrics. This processor is built using a 2.5D packaging method, integrating two dies and boasting a substantial 60 billion transistors. The core of the Yitian 710 consists of 128 high-performance Armv9 CPU cores, each accompanied by advanced memory configurations that streamline instruction and data caching processes. Each CPU integrates 64KB of L1 instruction cache, 64KB of L1 data cache, and 1MB of L2 cache, supplemented by a robust 128MB system-level cache on the chip. To support expansive data operations, the processor is equipped with an 8-channel DDR5 memory system, enabling peak memory bandwidth of up to 281GB/s. Its I/O subsystem is formidable, featuring 96 PCIe 5.0 channels capable of achieving dual-direction bandwidth up to 768GB/s. With its multi-layered design, the Yitian 710 Processor is positioned as a leading solution for cloud services, data analytics, and AI operations.
Veyron V2 represents the next generation of Ventana's high-performance RISC-V CPU. It significantly enhances compute capabilities over its predecessor, designed specifically for data center, automotive, and edge deployment scenarios. This CPU maintains compatibility with the RVA23 RISC-V specification, making it a powerful alternative to the latest ARM and x86 counterparts within similar domains. Focusing on seamless integration, the Veyron V2 offers clean, portable RTL implementations with a standardized interface, optimizing its use for custom SoCs with high-core counts. With a robust 512-bit vector unit, it efficiently supports workloads requiring both INT8 and BF16 precision, making it highly suitable for AI and ML applications. The Veyron V2 is adept in handling cloud-native and virtualized workloads due to its full architectural virtualization support. The architectural advancements offer significant performance-per-watt improvements, and advanced cache and virtualization features ensure a secure and reliable computing environment. The Veyron V2 is available as both a standalone IP and a complete hardware platform, facilitating diverse integration pathways for customers aiming to harness Ventana’s innovative RISC-V solutions.
Designed for ultra-low power consumption, the Tianqiao-70 delivers commercial-grade processing in a 64-bit RISC-V architecture. It's particularly geared towards mobile computing, desktop applications, and environments requiring efficient performance within a constrained power budget. The Tianqiao-70 leverages advanced RISC-V features to ensure it meets modern demands for low power yet high-performance computing, especially in mobile and intelligent systems. With scalability designed within its core, this CPU can adapt to a range of applications, from mobile devices to edge AI processing. StarFive emphasizes on power efficiency without compromising on performance, making the Tianqiao-70 a strategic choice for developers focusing on sustainable and intelligent technologies. This CPU core not only extends battery life but also enhances the capability of devices to handle sophisticated tasks with minimal energy use.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
The RV12 RISC-V Processor from Roa Logic is a highly versatile CPU designed for embedded applications. It complies with the RV32I and RV64I specifications of the RISC-V instruction set, supporting single-core configurations. The RV12 processor is renowned for its configurability, allowing it to be tailored to specific application requirements. It implements a Harvard architecture, which enables concurrent access to both instruction and data memory, optimizing performance and efficiency. Roa Logic's RV12 processor is part of their broader portfolio of 32/64-bit CPU solutions that leverage the open-source RISC-V instruction set. This architecture is favored for its simplicity and scalability, making it ideal for various embedded systems. The processor is equipped with an optimizing feature set that enhances its processing capabilities, ensuring it meets the rigorous demands of modern applications. Incorporating the RV12 processor into projects is streamlined thanks to its comprehensive support documentation and available test benches. These resources facilitate smooth integration into larger systems, providing developers with a reliable foundation for building advanced embedded systems. Its design is a testament to Roa Logic's commitment to delivering high-performance, adaptable IP solutions to the semiconductor industry.
The Chimera GPNPU from Quadric stands as a versatile processing unit designed to accelerate machine learning models across a wide range of applications. Uniquely integrating the strengths of neural processing units and digital signal processors, the Chimera GPNPU simplifies heterogeneous workloads by running traditional C++ code and complex AI networks such as large language models and vision transformers in a unified processor architecture. This scalability, tailored from 1 to 864 TOPs, allows it to meet the diverse requirements of markets, including automotive and network edge computing.\n\nA key feature of the Chimera GPNPU is its ability to handle matrix and vector operations alongside scalar control code within a single pipeline. Its fully software-driven nature enables developers to fine-tune model performance over the processor's lifecycle, adapting to evolving AI techniques without needing hardware updates. The system's design minimizes off-chip memory access, thereby enhancing efficiency through its L2 memory management and compiler-driven optimizations.\n\nMoreover, the Chimera GPNPU provides an extensive instruction set, finely tuned for AI inference tasks with intelligent memory management, reducing power consumption and maximizing processing efficiency. Its ability to maintain high performance with deterministic execution across various processes underlines its standing as a leading choice for AI-focused chip design.
The SCR9 Processor Core represents the height of processor sophistication with a 12-stage dual-issue out-of-order pipeline complemented by a vector processing unit (VPU). This 64-bit, 16-core configuration supports hypervisor capabilities, making it a powerhouse for enterprise and high-performance applications. Designed to meet the rigorous demands of AI, ML, and computational-heavy environments, the SCR9 core delivers exceptional data throughput and processing power. Its comprehensive architecture includes robust memory and cache management, ensuring efficiency and speed in processing. This application-class core is supported by an extensive ecosystem of development tools and platforms, ensuring that developers can exploit its full potential for innovative solutions. With its focus on high efficiency and advanced capabilities, the SCR9 core is a definitive choice in fields demanding top-tier processing power.
The eSi-1600 is a 16-bit CPU core designed for cost-sensitive and power-efficient applications. It accords performance levels similar to that of 32-bit CPUs while maintaining a system cost comparable to 8-bit processors. This IP is particularly well-suited for control applications needing limited memory resources, demonstrating excellent compatibility with mature mixed-signal technologies.
The xcore.ai platform is designed to power the intelligent Internet of Things (IoT) by combining flexibility and performance efficiency. With its distinctive multi-threaded micro-architecture, it allows for low-latency and predictable performance, crucial for IoT applications. Each xcore.ai device is equipped with 16 logical cores distributed over two tiles, each with integrated 512kB SRAM and a vector unit capable of handling both integer and floating-point operations. Communication between processors is facilitated by a robust interprocessor communication infrastructure, enabling scalability for systems requiring multiple xcore.ai SoCs. This platform supports a multitude of applications by integrating DSP, AI, and I/O processing within a cohesive development environment. For audio and voice processing needs, it offers adaptable, software-defined I/O that aligns with specific application requirements, ensuring efficient and targeted performance. The xcore.ai is also equipped for ai and machine learning tasks with a 256-bit VPU that supports various operations including 32-bit, 16-bit, and 8-bit vector operations, offering peak AI performance. The inclusion of a comprehensive development kit allows developers to explore its capabilities through ready-made solutions or custom-built applications.
The Y180 is a CPU-focused IP core that efficiently replicates the functionality of the Zilog Z180 CPU, comprising around 8k gates. This implementation showcases Systemyde’s commitment to detail, ensuring a consistent and reliable performance within a minimized footprint. With a core dedicated to sustaining traditional CPU operations, the Y180 is notably small yet potent, suiting designs requiring streamlined CPU cores. It remains resilient in environments that demand traditional computing interfaces, providing a dependable platform for basic process tasks. Its silicon-proven design attests to its dependability and functionality across various implementations. As a go-to standard, the Y180 supports standard CPU applications seamlessly, acting as an accessible solution for Zilog’s architectural compatibility.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
As a pinnacle of high-performance Linux-capable processor cores, the SCR7 Application Core incorporates a 12-stage dual-issue out-of-order pipeline for enhanced execution efficiency. This core is engineered for applications that require robust data handling and processing, with support for cache coherency and virtual memory management. The SCR7 core caters to advanced markets such as AI, ML, and data centers, benefiting from its scalability in 64-bit 8-core configurations. This formidable architecture is designed to handle complex computational loads, especially where rapid real-time data processing is vital. With a complete software development toolkit, this core empowers developers to integrate and optimize seamlessly into their systems, facilitating innovation and delivering top-tier performance in demanding application landscapes.
The RISC-V Core-hub Generators from InCore are tailored for developers who need advanced control over their core architectures. This innovative tool enables users to configure core-hubs precisely at the instruction set and microarchitecture levels, allowing for optimized design and functionality. The platform supports diverse industry applications by facilitating the seamless creation of scalable and customizable RISC-V cores. With the RISC-V Core-hub Generators, InCore empowers users to craft their own processor solutions from the ground up. This flexibility is pivotal for businesses looking to capitalize on the burgeoning RISC-V ecosystem, providing a pathway to innovation with reduced risk and cost. Incorporating feedback from leading industry partners, these generators are designed to lower verification costs while accelerating time-to-market for new designs. Users benefit from InCore's robust support infrastructure and a commitment to simplifying complex chip design processes. This product is particularly beneficial for organizations aiming to integrate RISC-V technology efficiently into their existing systems, ensuring compatibility and enhancing functionality through intelligent automation and state-of-the-art tools.
The SiFive Essential line features a versatile range of embedded CPU cores that serve a wide variety of markets, from consumer electronics to industrial computing. With an emphasis on configurability, these cores can be tailored to meet specific operational requirements, providing a foundation for custom applications tailored to precise needs. Offering a scaffold for both 32-bit MCUs and 64-bit CPUs, the Essential series supports various pipeline configurations to maximize throughput and optimize power usage. Its design inherently enables scalable performance, making it suitable for applications requiring performance optimization and advanced customization. These cores uphold SiFive’s tradition of high-quality innovation, delivering a robust, silicon-proven solution with billions of units already shipped globally. Ideal for diverse application scenarios, the Essential series provides a reliable, cost-effective foundation for a multitude of embedded processing projects.
This core is a remarkably energy-efficient processor designed by Micro Magic, Inc., offering a powerful solution for modern computing needs. Operating at 1GHz and consuming a mere 10mW of power, it leverages low voltage operation to achieve high-speed performance ideal for embedded and portable applications. The RISC-V core integrates design techniques that allow it to function efficiently across a range of voltages while maintaining superior performance levels often demanded by today's technology. This blend of power efficiency and performance makes it a prime candidate for application in cutting-edge consumer electronics and IoT devices where battery life and processing speed are critical. This core's architecture suits a wide variety of implementations, providing flexibility to developers aiming to create custom solutions tailored to specific market requirements. By enabling engineers to reduce power consumption without compromising on speed, the 64-bit RISC-V core demonstrates Micro Magic's commitment to pushing the boundaries of semiconductor technology.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The Titanium Ti375 FPGA presents an advanced solution ideal for developers seeking high-density, low-power configurations. Within its design is Efinix's Quantum compute fabric, which offers superior computational efficiency bundled with a robust I/O interface. Highlighting its versatility, the Ti375 incorporates a hardened RISC-V block, facilitating complex data processing tasks without confining power usage. Additionally, features such as a SerDes transceiver and LPDDR4 DRAM controller mark it as a powerful asset in high-demand environments, ensuring smooth and reliable data transactions. Further empowering its capability is an integrated MIPI D-PHY, making it particularly well-suited for modern applications demanding high-speed data exchange and connectivity.
The SCR1 Microcontroller Core is a compact, open-source processor designed for deeply embedded applications. It features a 4-stage in-order pipeline, making it highly efficient and suitable for scenarios demanding minimal area footprint and energy consumption. Ideal for IoT devices and sensor-centric systems, it balances performance with power efficiency in a 32-bit architecture. This core is optimized for real-time operating systems and integrates seamlessly into complex digital systems. With its small gate count and energy-conscious design, the SCR1 core excels in environments where low power and high reliability are paramount. Its configurability allows for tailored implementations that can meet diverse application requirements. Designed in SystemVerilog, it is supported by a comprehensive development toolkit and FPGA-based SDK, ensuring developers have all the necessary tools for efficient deployment and testing.
The RISC-V CPU IP N Class from Nuclei is engineered to cover a broad range of applications in the 32-bit architecture spectrum. This IP is designed with an emphasis on microcontroller functionalities, making it ideal for AIoT solutions. Tailored for flexibility, it supports numerous customization options, including integrated security features and functional safety assurance, which underscore its adaptability in diverse IoT deployments. Notably, the N Class configuration supports a wide array of tools and resources within the RISC-V ecosystem to streamline the development process and enhance performance optimization. At its core, the N Class IP is built to comply with the RISC-V open standard, ensuring compatibility and ease of integration with existing systems. Its robust configurability allows developers to select specific features pertinent to their application requirements, thereby optimizing resource allocation and efficiency. Featuring a three-stage pipeline architecture, the N Class delivers single and dual issue capabilities, which are crucial for achieving a balance between processing power and energy efficiency. Furthermore, the N Class IP stands out for its exceptional scalability. It accommodates user-defined instruction extensions, as well as the RISC-V B/K/P/V extensions, which together facilitate the execution of sophisticated tasks and enhance the overall versatility of the processor. This configurability and support for comprehensive information security solutions make it a vital component in securing IoT applications.
The SiFive Intelligence X280 delivers best-in-class vector processing capabilities powered by the RISC-V architecture, specifically targeting AI and ML applications. This core is designed to cater to advanced AI workloads, equipped with extensive compute capabilities that include wide vector processing units and scalable matrix computation. With its distinctive software-centric design, the X280 facilitates easy integration and offers adaptability to complex AI and ML processes. Its architecture is built to handle modern computational demands with high efficiency, thanks to its robust bandwidth and scalable execution units that accommodate evolving machine learning algorithms. Ideal for edge applications, the X280 supports sophisticated AI operations, resulting in fast and energy-efficient processing. The design flexibility ensures that the core can be optimized for a wide range of applications, promising unmatched performance scalability and intelligence in edge computing environments.
Topaz FPGAs are engineered to be a go-to solution for industries requiring a swift scale-up to volume production without compromising on performance or efficiency. Centered around an efficient architectural framework, these FPGAs deliver the power and functionality needed to address mainstream applications. They are renowned for their innovative fabric, which optimizes both die area and performance metrics. As such, Topaz FPGAs are indispensable for projects ranging from consumer electronics to automotive solutions, ensuring adaptability and scalability along evolving technological paths. Furthermore, with their seamless system integration capability, these FPGAs significantly shorten the development cycle, facilitating a faster go-to-market strategy while maintaining the high standards Efinix is known for.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Veyron V1 is a high-performance RISC-V CPU aimed at data centers and similar applications that require robust computing power. It integrates with various chiplet and IP cores, making it a versatile choice for companies looking to create customized solutions. The Veyron V1 is designed to offer competitive performance against x86 and ARM counterparts, providing a seamless transition between different node process technologies. This CPU benefits from Ventana's innovation in RISC-V technology, where efforts are placed on providing an extensible architecture that facilitates domain-specific acceleration. With capabilities stretching from hyperscale computing to edge applications, the Veyron V1 supports extensive instruction sets for high-throughput operations. It also boasts leading-edge chiplet interfaces, opening up numerous opportunities for rapid productization and cost-effective deployment. Ventana's emphasis on open standards ensures that the Veyron V1 remains an adaptable choice for businesses aiming at bespoke solutions. Its compatibility with system IP and its provision in multiple platform formats—including chiplets—enable businesses to leverage the latest technological advancements in RISC-V. Additionally, the ecosystem surrounding the Veyron series ensures support for both modern software frameworks and cross-platform integration.
The SiFive Performance series is designed to deliver the highest levels of computing power while maintaining energy efficiency. These cores are optimized for a variety of demanding applications, offering a balance of high throughput, scalability, and customization. Tailored for industries that require maximum performance, the series boasts both scalar and vector processing capabilities, equipped with advanced features like out-of-order execution and optional vector compute engines for enhanced versatility. The design of the SiFive Performance series allows for flexible deployment across diverse applications, from high-performance computing environments to embedded systems. The major emphasis on customization enables users to optimize their solutions for specific needs, ensuring that performance metrics are closely aligned with operational demands. These cores provide support for the latest RISC-V profiles, offering improved computation power, energy efficiency, and integration flexibility. The result is a highly capable core IP solution that is ready to power next-generation technology in sectors like data centers, AI, and beyond.
The Azurite Core-hub by InCore Semiconductors is a sophisticated solution designed to offer scalable RISC-V SoCs with high-speed secure interconnect capabilities. This processor is tailored for performance-demanding applications, ensuring that systems maintain robust security while executing tasks at high speeds. Azurite leverages advanced interconnect technologies to enhance the communication between components within a SoC, making it ideal for industries that require rapid data transfer and high processing capabilities. The core is engineered to be scalable, supporting a wide range of applications from edge AI to functional safety systems, adapting seamlessly to various industry needs. Engineered with a focus on security, the Azurite Core-hub incorporates features that protect data integrity and system operation in a dynamic technological landscape. This makes it a reliable choice for companies seeking to integrate advanced RISC-V architectures into their security-focused applications, offering not just innovation but also peace of mind with its secure design.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The SCR3 Microcontroller Core offers a medium-performance solution for embedded applications, featuring a 5-stage in-order pipeline. It supports both 32-bit and 64-bit configurations, providing a versatile platform for various use cases in industrial and automotive systems. Equipped with privilege modes and a memory protection unit (MPU), the SCR3 core emphasizes security and stability, ensuring robust performance in safety-critical environments. Additionally, its L1 and L2 cache support enhances processing speed and data efficiency. Tailored for real-time tasks, this core integrates capabilities that support complex control systems and network devices. Its architecture and toolchain are specifically designed to enable developers to quickly innovate and meet stringent application demands.
The Codasip RISC-V BK Core Series represents a family of processor cores that bring advanced customization to the forefront of embedded designs. These cores are optimized for power and performance, striking a fine balance that suits an array of applications, from sensor controllers in IoT devices to sophisticated automotive systems. Their modular design allows developers to tailor instructions and performance levels directly to their needs, providing a flexible platform that enhances both existing and new applications. Featuring high degrees of configurability, the BK Core Series facilitates designers in achieving superior performance and efficiency. By supporting a broad spectrum of operating requirements, including low-power and high-performance scenarios, these cores stand out in the processor IP marketplace. The series is verified through industry-leading practices, ensuring robust and reliable operation in various application environments. Codasip has made it straightforward to use and adapt the BK Core Series, with an emphasis on simplicity and productivity in customizing processor architecture. This ease of use allows for swift validation and deployment, enabling quicker time to market and reducing costs associated with custom hardware design.
The RAIV General Purpose GPU (GPGPU) epitomizes versatility and cutting-edge technology in the realm of data processing and graphics acceleration. It serves as a crucial technology enabler for various prominent sectors that are central to the fourth industrial revolution, such as autonomous driving, IoT, virtual reality/augmented reality (VR/AR), and sophisticated data centers. By leveraging the RAIV GPGPU, industries are able to process vast amounts of data more efficiently, which is paramount for their growth and competitive edge. Characterized by its advanced architectural design, the RAIV GPU excels in managing substantial computational loads, which is essential for AI-driven processes and complex data analytics. Its adaptability makes it suitable for a wide array of applications, from enhancing automotive AI systems to empowering VR environments with seamless real-time interaction. Through optimized data handling and acceleration, the RAIV GPGPU assists in realizing smoother and more responsive application workflows. The strategic design of the RAIV GPGPU focuses on enabling integrative solutions that enhance performance without compromising on power efficiency. Its functionality is built to meet the high demands of today’s tech ecosystems, fostering advancements in computational efficiency and intelligent processing capabilities. As such, the RAIV stands out not only as a tool for improved graphical experiences but also as a significant component in driving innovation within tech-centric industries worldwide. Its pioneering architecture thus supports a multitude of applications, ensuring it remains a versatile and indispensable asset in diverse technological landscapes.
The SCR6 Microcontroller Core stands out with its 12-stage dual-issue out-of-order pipeline, strategically designed for high-performance microcontroller applications. This 64-bit core supports a high-performance floating-point unit, which is key for computations in complex embedded systems and applications demanding precision. Optimized for real-time operating systems, the SCR6 offers advanced processing capabilities required by new-age industrial, IoT, and automotive applications. Its out-of-order execution pipeline ensures maximum efficiency, reducing latency while maintaining low power consumption. The development ecosystem supporting SCR6 includes a comprehensive toolkit and documentation, facilitating rapid design and deployment efforts, empowering developers to meet and exceed performance demands effectively.
The eSi-1650 is a compact, low-power 16-bit CPU core integrating an instruction cache, making it an ideal choice for mature process nodes reliant on OTP or Flash program memory. By omitting large on-chip RAMs, the IP core optimizes power and area efficiency and permits the CPU to capitalize on its maximum operational frequency beyond OTP/Flash constraints.
AheadComputing's RISC-V Core IP delivers unmatched performance designed for intensive computing applications. This core utilizes a powerful 64-bit architecture, embodying the latest advancements in RISC-V processing technology to ensure exceptional operational efficiency. The core's design facilitates a significant boost in per-core performance, which is ideal for applications that require high computational power and reliability. With an inherent ability to support a variety of computing environments, this RISC-V Core IP is perfect for developers looking to enhance application processors' processing power across diverse industries. Crafted with scalability in mind, it offers developers the flexibility needed to adapt to evolving technological demands. By leveraging advanced RISC-V capabilities, this core ensures a future-proof solution that seamlessly fits into existing and emerging product lines.
The "Origin E1" is engineered for AI applications demanding minimal power and space, commonly deployed in home appliances, smartphones, and security devices. Tailored for efficiency, the E1 provides a compact AI processing unit optimized to handle always-on tasks with a low power footprint. Its architecture focuses on achieving less than 1 TOPS performance, making it well-suited for applications where conserving power and memory is paramount. By utilizing Expedera's packet-based schema, the E1 achieves parallel processing across layers, enhancing speed and reducing energy and space requirements, crucial for maintaining the performance of everyday smart devices. In terms of utility, the E1 is exemplified in always-listening technologies, allowing for seamless user experiences by keeping the power necessary for continuous AI analysis to a minimum, ensuring privacy as all data remains processed within the subsystem.
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
The SCR4 Microcontroller Core provides enhanced computational capability in a 32/64-bit architecture, equipped with a 5-stage in-order pipeline. Designed for embedded systems, it features integrated floating-point unit (FPU) and memory protection unit (MPU) for increased precision and reliability. Supporting multicore configurations, this core is adept at handling sophisticated industrial and IoT applications. Its cache hierarchy, comprising L1 and L2 caches, enhances data handling efficiency, crucial for time-sensitive processing tasks. The SCR4 core's SystemVerilog-configured design, coupled with a complete development toolkit and FPGA SDK, ensures that developers have the resources necessary for expedited development and deployment. This core balances advanced functionality with efficient power use, making it a prime choice for demanding embedded applications.
Designed for application-class deployments, the SCR5 Application Core is a Linux-capable processor with enhanced data processing capabilities. Its 9-stage in-order pipeline provides a robust platform for mid- to high-performance applications, making it suitable for AI, ML, and mobile device contexts. Featuring memory management units (MMU) and cache coherency, the SCR5 core facilitates efficient task management and data processing. Its support for L1 and L2 caches ensures streamlined data operations, which is critical in high throughput environments. SCR5's SystemVerilog architecture is supported by an extensive development toolkit and platform, facilitating accelerated deployment and innovation. This core offers an ideal combination of functionality, efficiency, and configurability, making it an ideal choice for developers seeking high-performance application cores.
Nuclei's UX Class RISC-V CPU IP represents a high-caliber offering crafted for Linux-based systems in data centers and networks. This IP harnesses a 64-bit architecture, incorporating a Memory Management Unit to enhance system operations and facilitate the processing of heavy data loads. It is designed to meet the rigorous standards of data-intensive environments while maintaining a focus on efficiency and seamless integration within established systems. Built with a focus on adaptability, the UX Class IP can be configured to meet a variety of operational specifications, making it a versatile choice for data center applications that require robust and reliable processing power. It supports a dual-issue pipeline structure, enabling more efficient management of concurrent processing tasks and enhancing throughput across complex computing scenarios. Furthermore, the UX Class IP integrates a range of functionalities intended to bolster system security and reliability. Trusted execution environments and advanced physical security measures ensure that sensitive data remains protected, which is a critical requirement in network and data center environments. By supporting a comprehensive toolchain, including RTOS and Linux environments, the UX Class IP ensures developers have access to essential resources that streamline development processes and enhance application standards.
The Y51 processor employs the 8051 Instruction Set Architecture designed as a 2-clock machine cycle unit, building efficiency into its operation across compact environments. Crafted for projects requiring the enduring and well-understood 8051 architecture, Y51 aligns itself with established norms in processor functionality. Equipped for direct compatibility, the Y51 serves legacy system necessities by maintaining a connection to traditional frameworks, enhancing performance without complicating its architectural premise. It is a cost-effective solution acknowledging the persisting demand for traditional instruction sets. Expectations for high integration and seamless operation find a fitting response in Y51’s reliable structure. It supports continuous, effective processing within systems relying on substantial historical computing protocols, maintaining high standards of processor core efficiency.
The M8051EW expands upon the M8051W's impressive performance by incorporating on-chip debugging capabilities. This microcontroller core offers not only rapid execution but also integrates a JTAG debug port for compatibility with external debugging tools. Additionally, this core is designed with hardware breakpoints and instruction tracebacks, providing full read and write access across all register and memory locations. Such capabilities, together with its fast execution cycle, make it an ideal choice for designs requiring advanced debugging and real-time control.
As the third generation in the Rabbit series, the Rabbit 4000 integrates 161k gates with 128 pins, an evolution that supports intensive computational applications. Its foundation is technology-independent, ensuring extensive adaptability in design applications requiring high throughput and robust reliability. This model comes with a comprehensive package supporting full silicon verification, backed by Systemyde’s thorough documentation. It extends usability into challenging environments, blending synthesized Verilog design with significant processing power across ASIC, FPGA, and custom scenarios. Superior architectural design underpins the Rabbit 4000, emphasizing seamless integration within diverse use cases, including high-performance embedded systems. It supports sophisticated data handling and processing, vital in achieving complex digital operations and ensuring long-term viability in excessive functional demands.
Building upon the Y180, the Y180S represents a safe-state iteration with approximately 10k gates. This model ensures reliable performance with added safety features that are crucial for sensitive applications requiring enhanced security and reliable operations. The design integrates improvement over the basic Y180, embedding security measures that provide steady and secure processing. With an emphasis on curated safety standards, Y180S delivers consistent outcomes even in challenging circumstances where secure data handling is pivotal. This CPU variant serves specialized needs, blending core functionality with critical safety advancements, suitable for operations that necessitate safeguarded data integrity. Well adapted for resilient computing frameworks, the Y180S stands firm in projects prioritizing secure transactional functions.
The iniCPU is a versatile processor core drawing on the widespread and trusted 6809 architecture. This processor integrates seamlessly into system-on-chip (SoC) designs, leveraging a 16-bit DSP framework to extend its utility across various computational needs. With its rich feature set, initCPU assures robust performance dynamics suitable for a range of processing environments while adhering to industry standards. Emphasizing compatibility and performance, the processor is crafted for easy integration into both FPGA and ASIC applications. Its technology-agnostic nature ensures straightforward migration paths, facilitating diverse application development and deployment. Developers are poised to benefit from its simplified architecture that promotes operational efficiency. This processor core adapts well beyond generic processing, extending to specialty applications like real-time data handling and complex algorithm processing. These capabilities make it a prime choice for applications in telecommunications, consumer electronics, and industrial automation, enhancing overall design robustness and speed-to-market results.
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