All IPs > Processor > DSP Core
In the realm of semiconductor IP, DSP Cores play a pivotal role in enabling efficient digital signal processing capabilities across a wide range of applications. Short for Digital Signal Processor Cores, these semiconductor IPs are engineered to handle complex mathematical calculations swiftly and accurately, making them ideal for integration into devices requiring intensive signal processing tasks.
DSP Core semiconductor IPs are widely implemented in industries like telecommunications, where they are crucial for modulating and encoding signals in mobile phones and other communication devices. They empower these devices to perform multiple operations simultaneously, including compressing audio, optimizing bandwidth usage, and enhancing data packets for better transmission quality. Additionally, in consumer electronics, DSP Cores are fundamental in audio and video equipment, improving the clarity and quality of sound and visuals users experience.
Moreover, DSP Cores are a linchpin in the design of advanced automotive systems and industrial equipment. In automotive applications, they assist in radar and lidar systems, crucial for autonomous driving features by processing the data needed for real-time environmental assessment. In industrial settings, DSP Cores amplify the performance of control systems by providing precise feedback loops and enhancing overall process automation and efficiency.
Silicon Hub's category for DSP Core semiconductor IPs includes a comprehensive collection of advanced designs tailored to various processing needs. These IPs are designed to integrate seamlessly into a multitude of hardware architectures, offering designers and engineers the flexibility and performance necessary to push the boundaries of technology in their respective fields. Whether for enhancing consumer experiences or driving innovation in industrial and automotive sectors, our DSP Core IPs bring unparalleled processing power to the forefront of digital innovations.
The 1G to 224G SerDes platform stands out as one of Alphawave Semi's flagship offerings. It showcases a wide range of capabilities by supporting data transmission rates from 1Gbps to a staggering 224Gbps. This SerDes solution is compatible with a multitude of industry protocols and leverages innovative signaling schemes such as PAM2, PAM4, PAM6, and PAM8, which ensures robust performance across varied applications. Engineered to facilitate seamless integration, the SerDes IP meets the expansive data needs of modern computing environments. Crafted with high-speed digital data transmission in mind, the 1G to 224G SerDes delivers outstanding performance in handling interfaces that require precise timing and jitter management. This IP is adept at boosting signal integrity, a crucial feature in high-performance data centers and telecommunications infrastructure. Additionally, it offers a flexible framework adaptable to evolving connectivity demands within para-silicon environments, making it essential for companies aiming to maintain cutting-edge data solutions. Alphawave's SerDes IP is an integral component for industries that demand reliable and accelerated data pathways. Its flexibility further allows customization to match specific client requirements, ensuring optimized performance at minimized power usage. With strategic support for a broad array of process nodes, this SerDes IP is a future-proof investment for any technology-driven enterprise.
xcore.ai stands as a cutting-edge processor that brings sophisticated intelligence, connectivity, and computation capabilities to a broad range of smart products. Designed to deliver optimal performance for applications in consumer electronics, industrial control, and automotive markets, it efficiently handles complex processing tasks with low power consumption and rapid execution speeds. This processor facilitates seamless integration of AI capabilities, enhancing voice processing, audio interfacing, and real-time analytics functions. It supports various interfacing options to accommodate different peripheral and sensor connections, thus providing flexibility in design and deployment across multiple platforms. Moreover, the xcore.ai ensures robust performance in environments requiring precise control and high data throughput. Its compatibility with a wide array of software tools and libraries enables developers to swiftly create and iterate applications, reducing the time-to-market and optimizing the design workflows.
Chimera GPNPU provides a groundbreaking architecture, melding the efficiency of neural processing units with the flexibility and programmability of processors. It supports a full range of AI and machine learning workloads autonomously, eliminating the need for supplementary CPUs or GPUs. The processor is future-ready, equipped to handle new and emerging AI models with ease, thanks to its C++ programmability. What makes Chimera stand out is its ability to manage a diverse array of workloads within a singular processor framework that combines matrix, vector, and scalar operations. This harmonization ensures maximum performance for applications across various market sectors, such as automotive, mobile devices, and network edge systems. These capabilities are designed to streamline the AI development process and facilitate high-performance inference tasks, crucial for modern gadget ecosystems. The architecture is fully synthesizable, allowing it to be implemented in any process technology, from current to advanced nodes, adjusting to desired performance targets. The adoption of a hybrid Von Neuman and 2D SIMD matrix design supports a broad suite of DSP operations, providing a comprehensive toolkit for complex graph and AI-related processing.
The Jotunn 8 is heralded as the world's most efficient AI inference chip, designed to maximize AI model deployment with lightning-fast speeds and scalability. This powerhouse is crafted to efficiently operate within modern data centers, balancing critical factors such as high throughput, low latency, and optimization of power use, all while maintaining a sustainable infrastructure. With the Jotunn 8, AI investments reach their full potential through high-performance inference solutions that significantly reduce operational costs while committing to environmental sustainability. Its ultra-low latency feature is crucial for real-time applications such as chatbots and fraud detection systems. Not only does it deliver high throughput needed for demanding services like recommendation engines, but it also proves cost-efficient, aiming to lower the cost per inference crucial for businesses operating at a large scale. Additionally, the Jotunn 8 boasts performance per watt efficiency, a major factor considering that power is a significant operational expense and a driver of the carbon footprint. By implementing the Jotunn 8, businesses can ensure their AI models deliver maximum impact while staying competitive in the growing real-time AI services market. This chip lays down a new foundation for scalable AI, enabling organizations to optimize their infrastructures without compromising on performance.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
The Spiking Neural Processor T1 represents a significant leap in neuromorphic microcontroller technology, blending ultra-low power consumption with advanced spiking neural network capabilities. This microcontroller stands as a complete solution for processing sensor data with unprecedented efficiency and speed, bringing intelligence directly to the sensor. Incorporating a nimble RISC-V processor core alongside its spiking neural network engine, the T1 is engineered for seamless integration into next-generation AI applications. Within a tightly constrained power envelope, it excels at signal processing tasks that are crucial for battery-operated, latency-sensitive devices. The T1's architecture allows for fast, sub-1mW pattern recognition, enabling real-time sensory data processing akin to the human brain's capabilities. This microcontroller facilitates complex event-driven processing with remarkable efficiency, reducing the burden on application processors by offloading sensor data processing tasks. It is an enabler of groundbreaking developments in wearables, ambient intelligence, and smart devices, particularly in scenarios where power and response time are critical constraints. With flexible interface support, including QSPI, I2C, UART, and more, the T1 is designed for easy integration into existing systems. Its compact package size further enhances its suitability for embedded applications, while its comprehensive Evaluation Kit (EVK) supports developers in accelerating application development. The EVK provides extensive performance profiling tools, enabling the exploration of the T1's multifaceted processing capabilities. Overall, the T1 stands at the forefront of bringing brain-inspired intelligence to the edge, setting a new standard for smart sensor technology.
The SCR3 microcontroller core serves as an efficient platform for a range of embedded applications, characterized by its ability to handle both 32/64-bit constructs. Capable of supporting up to four symmetric multiprocessing (SMP) cores, this core is perfect for applications demanding enhanced computational power and multitasking abilities. It operates with a 5-stage in-order pipeline, which, coupled with privilege mode support, ensures that it can manage multiple tasks smoothly while maintaining operational integrity. Such capabilities make the SCR3 microcontroller core particularly well-suited for domains like industrial control systems and automotive applications, where precision and reliability are paramount. The inclusion of a memory protection unit (MPU) and layered L1 and L2 caches significantly boosts data processing rates, optimizing system performance. Bringing these features together, the core maintains high functionality while ensuring energy efficiency—an essential factor for high-demand embedded systems. A prominent feature of the SCR3 core is its flexibility. It can be extensively configured to match specific project requirements, from simple embedded devices to complex sensor networks. The provision of comprehensive documentation and development toolkits simplifies the integration process, supporting designers in developing robust and scalable solutions. Continued innovation and customization potential solidify the SCR3's position as a pivotal component in harnessing the power of RISC-V architectures.
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
The Codasip RISC-V BK Core Series represents a family of processor cores that bring advanced customization to the forefront of embedded designs. These cores are optimized for power and performance, striking a fine balance that suits an array of applications, from sensor controllers in IoT devices to sophisticated automotive systems. Their modular design allows developers to tailor instructions and performance levels directly to their needs, providing a flexible platform that enhances both existing and new applications. Featuring high degrees of configurability, the BK Core Series facilitates designers in achieving superior performance and efficiency. By supporting a broad spectrum of operating requirements, including low-power and high-performance scenarios, these cores stand out in the processor IP marketplace. The series is verified through industry-leading practices, ensuring robust and reliable operation in various application environments. Codasip has made it straightforward to use and adapt the BK Core Series, with an emphasis on simplicity and productivity in customizing processor architecture. This ease of use allows for swift validation and deployment, enabling quicker time to market and reducing costs associated with custom hardware design.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
The SiFive Performance family is at the forefront of providing maximum throughput and performance across a spectrum of computing requirements, from datacenter workloads to consumer applications. These 64-bit, out-of-order cores incorporate advanced vector processing capabilities up to 256-bit, supporting a diversity of workloads including AI. The architecture spans from three to six-wide out-of-order cores, optimized for either dedicated vector engines or a balanced energy-efficient setup, making it a versatile choice for high-performance needs. Engineered for modern AI workloads, the Performance series offers a robust compute density and performance efficiency that is ideal for both mobile and stationary infrastructure. Customers can take advantage of flexible configuration options to balance power and area constraints, thanks to SiFive's state-of-the-art RISC-V solutions. The family’s cores, such as the P400, P600, and P800 Series, offer scalability from low-power tasks to demanding datacenter applications. The series is particularly adept at handling AI workloads, making it suitable for applications that demand high-speed data processing and analysis, such as internet of things (IoT) devices, network infrastructure, and high-volume consumer electronics. Customers benefit from the ability to combine various performance cores into a unified, high-performance CPU optimized for minimal power consumption, making it possible to design systems that balance performance and efficiency.
The Tyr family of processors brings the cutting-edge power of Edge AI to the forefront, emphasizing real-time data processing directly at its point of origin. This capability facilitates instant insights with reduced latency and enhanced privacy, as it limits the reliance on cloud-based processing. Ideal for settings such as autonomous vehicles and smart factories, Tyr is engineered to operate faster and more secure with data-center-class performance in a compact, ultra-efficient design. The processors within the Tyr family are purpose-built to support local processing, which saves bandwidth and protects sensitive data, making it suitable for real-world applications like autonomous driving and factory automation. Edge AI is further distinguished by its ability to provide immediate analysis and decision-making capabilities. Whether it's enabling autonomous vehicles to understand their environment for safe navigation or facilitating real-time industrial automation, the Tyr processors excel in delivering low-latency, high-compute performance essential for mission-critical operations. The local data processing capabilities inherent in the Tyr line not only cut down on costs associated with bandwidth but also contribute towards compliance with stringent privacy standards. In addition to performance and privacy benefits, the Tyr family emphasizes sustainability. By minimizing cloud dependency, these processors significantly reduce operational costs and the carbon footprint, aligning with the growing demand for greener AI solutions. This combination of performance, security, and sustainability makes Tyr processors a cornerstone in advancing industrial and consumer applications using Edge AI.
Enclustra's Universal Drive Controller is a versatile IP core designed for controlling a range of motors directly from FPGAs. This robust solution allows simultaneous position and velocity control of up to eight different DC, BLDC, or stepper motors, offering high flexibility for a variety of industrial and robotic applications. The drive controller provides precise and independent motor management features through its customizable architecture, ensuring optimized performance tailored to specific motion control requirements. This capability reduces the need for additional external components, streamlining integration and reducing system complexity. In addition to its primary control features, the Universal Drive Controller supports various communication interfaces, enabling seamless integration into existing systems. This IP core is essential for developers focusing on high-performance motor control systems, thanks to its scalable and adaptable approach to motor management.
The iCan PicoPop® System on Module offers a compact solution for high-performance computing in constrained environments, particularly in the realm of aerospace technology. This system on module is designed to deliver robust computing power while maintaining minimal space usage, offering an excellent ratio of performance to size. The PicoPop® excels in integrating a variety of functions onto a single module, including processing, memory, and interface capabilities, which collectively handle the demanding requirements of aerospace applications. Its efficient power consumption and powerful processing capability make it ideally suited to a range of in-flight applications and systems. This solution is tailored to support the development of sophisticated aviation systems, ensuring scalability and flexibility in deployment. With its advanced features and compact form, the iCan PicoPop® System on Module stands out as a potent component for modern aerospace challenges.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
Tensix Neo represents a transformative leap in enhancing AI computational efficiency, specifically designed to empower developers working on sophisticated AI networks and applications. Built around a Network-on-Chip (NoC) framework, Tensix Neo optimizes performance-per-watt, a critical factor for AI processing. It supports multiple precision formats to adapt to diverse AI workloads efficiently, allowing seamless integration with existing models and enabling scalability. Careful design ensures that Tensix Neo delivers consistent high performance across varied AI tasks, from image recognition algorithms to advanced analytics, making it an essential component in the AI development toolkit. Its capability to connect with an expanding library of AI models allows developers to leverage its full potential across multiple cutting-edge applications. This synthesis of performance and efficiency makes Tensix Neo a vital player in fields requiring high adaptability and rapid processing, such as autonomous vehicles, smart devices, and dynamic data centers. Moreover, the compatibility of Tensix Neo with Tenstorrent's other solutions underscores its importance as a flexible and powerful processing core. Designed with the contemporary developer in mind, Tensix Neo integrates seamlessly with open-source resources and tools, ensuring that developers have the support and flexibility needed to meet the challenges of tomorrow's AI solutions.
Designed for efficiency in microcontroller applications, the SCR4 microcontroller core offers a balance between capabilities and resource management. Its 5-stage in-order pipeline ensures robust task management, featuring privilege modes for comprehensive application control, while boasting both 32 and 64-bit support. This core stands out due to its floating-point unit (FPU) integration, enhancing its capacity for handling complex computational tasks effectively. The SCR4 is highly applicable in industrial settings, specifically in environments requiring real-time data handling and swift computational responses. Its architectural design includes memory protection and cache layers, ensuring that data processes are not only fast but also secure, mitigating risks of data loss or corruption. Whether deployed in advanced control systems or real-time monitoring devices, the SCR4 adapts flexibly to meet stringent performance benchmarks. Accompanied by complete development support through comprehensive toolkits and resources, this core reduces the time needed for deployment and testing, allowing for quicker iteration cycles in product development. The SCR4's adaptability and efficiency contribute to its practicality in a variety of applications, from automotive to IoT devices, consistently delivering high-performance outcomes tailored to the modern technological landscape.
Designed to cater to the needs of edge computing, the Neural Network Accelerator by Gyrus AI is a powerhouse of performance and efficiency. With a focus on graph processing capabilities, this product excels in implementing neural networks by providing native graph processing. The accelerator attains impressive speeds, achieving 30 TOPS/W, while offering efficient computational power with significantly reduced clock cycles, ranging between 10 to 30 times less compared to traditional models. The design ensures that power consumption is kept at a minimum, being 10-20 times lower due to its low memory usage configuration. Beyond its power efficiency, this accelerator is designed to maximize space with a smaller die area, ensuring an 8-10 times reduction in size while maintaining high utilization rates of over 80% for various model structures. Such design optimizations make it an ideal choice for applications requiring a compact, high-performance solution capable of delivering fast computations without compromising on energy efficiency. The Neural Network Accelerator is a testament to Gyrus AI's commitment to enabling smarter edge computing solutions. Additionally, Gyrus AI has paired this technology with software tools that facilitate the execution of neural networks on the IP, simplifying integration and use in various applications. This seamless integration is part of their broader strategy to augment human intelligence, providing solutions that enhance and expand the capabilities of AI-driven technologies across industries.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
The Codasip L-Series DSP Core offers specialized features tailored for digital signal processing applications. It is designed to efficiently handle high data throughput and complex algorithms, making it ideal for applications in telecommunications, multimedia processing, and advanced consumer electronics. With its high configurability, the L-Series can be customized to optimize processing power, ensuring that specific application needs are met with precision. One of the key advantages of this core is its ability to be finely tuned to deliver optimal performance for signal processing tasks. This includes configurable instruction sets that align precisely with the unique requirements of DSP applications. The core’s design ensures it can deliver top-tier performance while maintaining energy efficiency, which is critical for devices that operate in power-sensitive environments. The L-Series DSP Core is built on Codasip's proven processor design methodologies, integrating seamlessly into existing systems while providing a platform for developers to expand and innovate. By offering tools for easy customization within defined parameters, Codasip ensures that users can achieve the best possible outcomes for their DSP needs efficiently and swiftly.
Secure Protocol Engines by Secure-IC are high-performance IP blocks designed to offload the intensive computational tasks of network and security processing from primary processors. These engines improve overall system efficiency by handling complex security protocols, ensuring that the main computing resources are available for critical applications. They are architected to provide robust protection against security breaches while ensuring swift data processing, maintaining the integrity, confidentiality, and availability of data across networks.
iniDSP is a state-of-the-art digital signal processor tailored for high-performance and real-time processing. Designed for integration into complex systems, iniDSP excels in handling demanding applications with precision. This DSP core is structured around a robust framework that ensures optimal processing speed and efficiency in various signal processing tasks. The architecture of the iniDSP is optimized to deliver excellent computational power, making it suitable for a wide range of industrial and consumer electronics applications. It offers flexible configuration options, allowing developers to tailor its capabilities to specific needs, thus enhancing overall system performance. Furthermore, iniDSP is supported by a comprehensive suite of development tools, including simulation libraries and comprehensive user documentation, which aid in streamlining the design process. Whether used in automotive systems or digital communication solutions, iniDSP is a critical building block for modern electronics.
The Universal DSP Library by Enclustra is designed to streamline digital signal processing across various applications. This library provides an extensive collection of DSP functions optimized for FPGA performance, enabling users to implement complex signal processing algorithms with ease and efficiency. It's tailored for image processing, audio applications, and other demanding DSP tasks, ensuring high performance and resource-efficient implementations. The library supports fixed-point and floating-point operations, offering flexibility in design according to specific needs. This makes it an invaluable resource for both prototyping and deployment in production environments, minimizing development time and maximizing performance. Furthermore, the Universal DSP Library includes a comprehensive set of features that are readily integrable with existing FPGA designs. Complementing its robust algorithmic offerings, Enclustra ensures that their DSP library is highly customizable, catering to unique processing requirements. This adaptability helps maintain high signal integrity and algorithm precision, making it an ideal choice for engineers looking to optimize their FPGA-based signal processing systems.
AON1100 is acclaimed as a forefront AI chip specifically for voice and sensor applications. Known for its extraordinary power efficiency, it consumes less than 260μW, excelling in sub-0dB signal-to-noise ratio environments while maintaining 90% accuracy. Designed for constantly operating devices, this chip leverages high-precision processing, facilitating its extensive application in always-on technologies like smart homes and automotive systems.
TUNGA is an advanced System on Chip (SoC) leveraging the strengths of Posit arithmetic for accelerated High-Performance Computing (HPC) and Artificial Intelligence (AI) tasks. The TUNGA SoC integrates multiple CRISP-cores, employing Posit as a core technology for real-number calculations. This multi-core RISC-V SoC is uniquely equipped with a fixed-point accumulator known as QUIRE, which allows for extremely precise computations across vectors as long as 2 billion entries. The TUNGA SoC includes programmable FPGA gates for enhancing field-critical functions. These gates are instrumental in speeding up data center services, offloading tasks from the CPU, and advancing AI training and inference efficiency using non-standard data types. TUNGA's architecture is tailored for applications demanding high precision, including cryptography and variable precision computing tasks, facilitating the transition towards next-generation arithmetic. In the computational ecology, TUNGA stands out by offering customizable features and rapid processing capabilities, making it suitable not only for typical data center functions but also for complex, precision-demanding workloads. By capitalizing on Posit arithmetic, TUNGA aims to deliver more efficient and powerful computational performance, reflecting a strategic advancement in handling complex data-oriented processes.
The Cottonpicken DSP Engine by section5 is an advanced digital signal processing solution crafted for high-speed signal manipulation. The engine supports Bayer pattern decoding and facilitates conversion to multiple formats including YUV 4:2:2, YUV 4:2:0, and RGB, with several programmable delays to optimize processing timelines. Additionally, the engine is equipped with sophisticated YUV conversion capabilities featuring support for color formats like YCrCb and YCoCg. Beyond color conversion, the Cottonpicken Engine integrates filter kernels and matrix operations, offering cascading support that enhances its processing efficiency. It boasts an impressive operational capacity within pixel clocks of up to 150 MHz, subject to the intricacies of the deployment platform, ensuring high-speed performance for complex DSP tasks. The engine is available only as a netlist object, included in specific development packages, providing users with a closed-source solution that integrates seamlessly into broader system designs. This specialized DSP engine is tailored to maximize data throughput and processing accuracy, delivering optimized signal processing performance in multimedia applications.
The NoISA processor by Hotwright Inc. is designed based on the innovative Hotstate machine, offering a departure from traditional ISA-based systems. Unlike conventional processors that rely on fixed ALU and register files, the NoISA processor features a programmable microcoded algorithmic state machine. It is especially useful in situations where a softcore CPU becomes too cumbersome in terms of space or performance, as it requires less area and energy. This makes it a suitable choice for IoT and edge applications where power efficiency is a crucial factor. This processor offers flexibility by allowing its behavior to be modified through the reloading of microcode rather than relying on a rigid set of instructions. This enables the processor to adapt quickly to varying needs, making it a powerful choice for scenarios like developing on FPGA or creating controller-based applications. It addresses the stiffness of standard ISA processors by delivering a processor that can change its function without altering the hardware design. The NoISA processor offers significant benefits in applications requiring quick adjustments and efficient processing, such as edge computing and IoT devices. It serves as a formidable option for developers looking to maximize performance without being limited by traditional processor constraints. This technology also provides developers the freedom to explore innovative computational designs, thanks to the Hotstate machine's ability to handle different programming requirements with ease.
The RFicient chip is crafted to transform the Internet of Things (IoT) by delivering unprecedented energy efficiency. It is engineered to power sustainable IoT applications, minimizing energy consumption to nearly negligible levels. Utilizing this technology, devices can operate over extended periods without the need for frequent battery replacements or extensive power sources. Equipped with advanced RF capabilities, this chip is tailored for long-range connectivity, enabling devices to communicate across vast distances seamlessly. It is suited for deployment in varied environments, ensuring robust performance even in shifting conditions. The innovation behind this chip lies in its integration of cutting-edge circuit design which maintains low power usage while maximizing performance. RFicient's potential extends far beyond simple connectivity. It supports IoT devices with minimal energy resources, proving critical in domains where maintenance accessibility is limited. Its adaptive technologies can foster new IoT applications, paving the way for a future where technology adapts intuitively to the needs of diverse sectors and environments.
The TSP1 Neural Network Accelerator is a state-of-the-art AI chip designed for versatile applications across various industries, including voice interfaces, biomedical monitoring, and industrial IoT. Engineered for efficiency, the TSP1 handles complex workloads with minimal power usage, making it ideal for battery-powered devices. This AI chip is capable of advanced bio-signal classification and natural voice interface integration, providing self-contained processing for numerous sensor signal applications. A notable feature is its high-efficiency neural network processing element fabric, which empowers signal pattern recognition and other neural network tasks, thereby reducing power, cost, and latency. The TSP1 supports powerful AI inference processes with low latency, enabling real-time applications like full vocabulary speech recognition and keyword spotting with minimal energy consumption. It's equipped with multiple interfaces for seamless integration and offers robust on-chip storage for secure network and firmware management. The chip is available in various packaging options to suit different application requirements.
The AON1020 is an AI processing IP within the AONSens Neural Network cores, designed for both voice recognition and additional sensor applications. Its robust capabilities are provided through an AI engine developed in Verilog RTL, suitable for logic synthesis for both ASICs and FPGAs. Notably excelling in noisy environments, it supports applications such as human activity detection with high adaptability and accuracy, making it ideal for use across diverse scenarios.
The Prodigy Universal Processor by Tachyum represents a landmark in processor technology, designed to facilitate a range of functions from general computing applications to AI-specific tasks. It integrates the benefits of CPUs, GPGPUs, and TPUs into a singular, cohesive architecture, showcasing a significant leap in performance efficiency and energy sustainability. The Prodigy chip radically lowers data center power use, thereby cutting carbon emissions and amplifying server efficiency. Additionally, this processor supports a reliable infrastructure that maximizes resource utilization across hyperscale data centers, AI enterprises, and HPC configurations.
The Domain-Specific RISC-V Cores from Bluespec are engineered to facilitate hardware acceleration in a streamlined and efficient manner. By packaging accelerators as software threads, these cores deliver high concurrency and efficient system performance. The scalability embedded in this technology caters to a range of application needs, enabling systematic hardware acceleration for developers and organizations aiming to optimize RISC-V implementations.
The AON1000 is a robust AI processing engine designed specifically for wake word detection, voice command recognition, acoustic event detection, and speaker identification. Tailored for always-on devices, it operates with exceptional power efficiency and accuracy in noisy conditions. The AON1000 is part of the AONVoice processor family and integrates proprietary neural network architecture and optimized inference algorithms to deliver industry-leading performance per microwatt.
The ARC Processor family offers highly configurable RISC and DSP cores designed for energy-efficient and high-performance applications. These processors are tailored to meet specific application requirements through customizable instruction sets and support for a variety of add-ons such as security extensions and DSP functionality. Synopsys ARC processors are optimal for applications within automotive, IoT, consumer electronics, and more. They provide flexibility for system designers to balance performance, power, and area, often reducing the need for subsequent redesigns.
The Blazar Bandwidth Accelerator Engine is designed to provide in-memory computing capabilities alongside high capacity and low latency memory solutions for applications demanding extreme data processing speeds. With embedded compute features and capacities reaching up to 1Gb, this engine supports applications that require fast and high-volume data handling, such as network processing and large-scale data analytics. This cutting-edge product integrates advanced in-memory functions such as burst and read-modify-write (RMW) operations, which are specifically designed to execute faster than conventional memory processes. These functions allow for efficient data manipulation and movement, enabling systems to achieve higher throughput and reduced operational commands. Additionally, the Blazar engine supports dual-port memory configurations which can handle simultaneous data read and write operations, optimizing data flow and reducing latency. The inclusion of optional RISC cores augments computing capabilities, providing a versatile platform for handling complex algorithms and real-time data requirements. Highly applicable for smart network interface cards (NICs) and high-performance computing environments, the Blazar Accelerator Engine is built to enhance the data processing abilities of modern IT infrastructure significantly. It represents a leap forward in memory architecture, supporting applications that are foundational to advancing fields like 5G rollouts, cloud computing, and advanced analytics.
Designed as a highly accurate FPGA system timer, the TimeServo IP core delivers unparalleled resolution and timing precision. Its primary function focuses on providing a reliable timebase that meets the high demands of packet timestamping, necessary for line-rate independent applications. TimeServo employs a PI-DPLL to synchronize with an external Pulse-Per-Second (PPS) signal, thus ensuring precise timekeeping and syntonicity across various system components. TimeServo can be configured as TimeServoPTP, embodying an IEEE-1588v2/PTP compliant slave device that seamlessly operates without requiring host processor intervention. Featuring flexible and independent clock domains, TimeServo caters to various control-plane and reference clock needs, supporting up to 32 outputs for expansive use in complex timing requirements. The core of TimeServo integrates a 120-bit resolution phase accumulator, offering fractional control and synchronization, all observed and controlled via an AXI-compliant software interface. It also boasts minimal jitter for both simulation and real-world conditions, making it an exemplary fit for applications where precise synchronization is paramount, like telecommunications and advanced networking systems.
Specialty Microcontrollers from Advanced Silicon harness the capabilities of the latest RISC-V architectures for advanced processing tasks. These microcontrollers are particularly suited to applications involving image processing, thanks to built-in coprocessing units that enhance their algorithm execution efficiency. They serve as ideal platforms for sophisticated touch screen interfaces, offering a balance of high performance, reliability, and low power consumption. The integrated features allow for the enhancement of complex user interfaces and their interaction with other system components to improve overall system functionality and user experience.
The Trifecta-GPU is a sophisticated commercial-off-the-shelf (COTS) peripheral designed to enhance computational capacity by integrating NVIDIA RTX A2000 Embedded GPUs within PXIe/CPCIe platforms. Aimed at modular Test & Measurement (T&M) and Electronic Warfare (EW) applications, it offers unmatched compute acceleration and a user-friendly programming environment. This solution delivers up to 8.3 FP32 TFLOPS peak compute performance, effectively supporting advanced signal processing and machine learning applications. The module supports PCIe Gen 4 x8 interfaces, which future-proofs its performance capabilities, while also featuring 8GB GDDR6 DRAM. The Trifecta-GPU is specifically crafted to maximize compute performance in constrained environments, such as Test & Measurement systems, thereby facilitating efficient analysis of data directly where it is acquired. The versatility of the architecture allows it to support extensive computing frameworks like MATLAB, Python, and C/C++. Trifecta-GPU’s advanced acceleration features include full resolution outputs for multi-monitor setups and specialized programming support for deep learning applications. This modular unit exemplifies how cutting-edge computing power can be seamlessly integrated into existing systems, facilitating ongoing operations without compromising data processing efficiency.
AON1010 represents a significant advancement in voice and audio recognition technology, forming part of the AONVoice Neural Network cores. This IP utilizes an AI processing engine delivered in Verilog RTL that suits ASIC and FPGA platforms. Designed for high accuracy in both quiet and noisy conditions, it manages multi-wake word detection, on-device voice commands, and provides adaptive voice activity detection, making it ideal for always-listening applications.
This dual-core ARM Cortex A9-based audio-video player provides a low-power solution for playing H.264 HD content. Integrated within a Xilinx Zynq-Z7010 platform, it serves numerous applications like digital signage, automotive infotainment, and industrial displays. With its capability to handle digital AV playback seamlessly, it supports various industry verticals by delivering high-def audiovisual output in a compact, efficient format.
The v-MP6000UDX Visual Processing Unit is a highly versatile processor featuring a unified processing architecture. This unit specializes in enabling real-time execution of the most intensive neural network tasks with exceptional power efficiency and a minimal silicon footprint. It supports a broad array of processing needs, effectively integrating deep learning, computer vision, image processing, and video compression on a single architecture. Designed to meet the rigorous demands of modern applications, the v-MP6000UDX offers unparalleled performance with its single software-programmable platform. Developers benefit from reduced development complexity, faster speed to market, and increased product lifespans. The processor can efficiently map and execute all layers of neural networks, easing the burden on software engineers and allowing seamless transitions across different machine learning frameworks. The versatility and high efficiency of the v-MP6000UDX make it an ideal choice for industries such as automotive, gaming, and mobile devices. Its ability to seamlessly integrate into system-on-chip designs further broadens its appeal, offering enhanced optimization opportunities for developers and significantly reducing integration overhead.
The xcore-200 is a versatile microcontroller renowned for its advanced multi-core processing capabilities and robustness in managing real-time applications. It is engineered to deliver high-performance outputs, making it an ideal choice for tasks that require precision and fast execution. With an emphasis on low-latency processing, the xcore-200 excels in applications such as voice and audio processing, enabling efficient interfacing and data management across various systems. Its architecture supports complex computational tasks while maintaining energy efficiency, a critical factor for applications across industrial and consumer sectors. Integrating flexible I/O capabilities, it is highly adaptable to a diverse range of hardware environments. This flexibility ensures it can meet the custom needs of projects, continuous with rapidly evolving technology landscapes, emphasizing smart and connected solutions.
Panmnesia's PanAccelerator is a high-performance solution crafted to boost the processing power of AI systems. It is tailored for leading-edge machine learning workloads that require high-bandwidth memory expansion and rapid GPU interconnection. This accelerator supports efficient power usage and offers expansive scalability, making it ideal for large-scale AI training environments.
Expanding the features of AON1100, AON1120 offers enhanced I/O and RISC-V support, tailored for smart home and automotive contexts. This AI chip extends its high precision capabilities, delivering improved interaction and growth potential across intelligent environments. Designed for superior performance in legacy systems, its adaptive interfaces ensure seamless integration into various application landscapes.
The FPGA Image Processing Core is engineered to accelerate the processing of digital images, enabling rapid analysis and enhancement for a myriad of applications. Suited for sectors where high-performance image analysis is critical, this core provides robust capabilities in delivering real-time image processing solutions. With advanced algorithms embedded within the core, it efficiently manages tasks such as image filtering, edge detection, and image transformation. This flexibility ensures its applicability in industries ranging from medical imaging, surveillance to augmented reality, where swift data handling and processing are paramount. Deployment of this core within digital imaging infrastructures ensures significant boosts in processing speed and accuracy, facilitating enhanced performance in complex image-handling tasks. By leveraging FPGA technology, the Image Processing Core allows for scalable solutions that enhance throughput while maintaining high-quality outputs. This core is a key component in pushing the envelope of what's achievable in digital image processing.
The Electrical PAM-X DSP by 1-VIA represents an innovative breakthrough in copper connectivity. Engineered to handle enhanced signal integrity over longer distances, this technology allows network infrastructures to significantly extend their reach without compromising on data quality. With its robust architecture, the PAM-X DSP supports high-frequency data transfer, making it an ideal solution for modern data centers. This DSP technology is pivotal for driving efficiency in data communication over copper wires, offering industries a competitive edge through reliable connectivity solutions. By maximizing bandwidth while maintaining low power consumption, the Electrical PAM-X DSP integrates seamlessly into various applications requiring robust data handling capabilities. The technology facilitates next-generation data center operations, empowering users to meet increasing demands for high-speed connectivity. As data volumes continue to grow, the Electrical PAM-X DSP ensures networks remain scalable and efficient, addressing both current and future connectivity needs.
The v-MP4000UDX Visual Processing Unit is designed for high-performance visual computing tasks, leveraging a unified platform that integrates various computational functions. It excels in processing intensive applications such as computer vision, improving both performance and power efficiency significantly. This processor features an architecture that accommodates a wide range of tasks including video encoding and decoding, image processing, and drive assistance systems. Its design ensures developers can utilize the same tools across different types of software applications, facilitating seamless integration and development acceleration. Ideal for use in smart consumer electronics and automotive industries, the v-MP4000UDX supports efficient processing of high-resolution video, including advanced video coding standards. It significantly cuts down on system complexity and development costs, all while meeting the increasing demand for smarter, more capable embedded solutions.
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