All IPs > Processor > DSP Core
In the realm of semiconductor IP, DSP Cores play a pivotal role in enabling efficient digital signal processing capabilities across a wide range of applications. Short for Digital Signal Processor Cores, these semiconductor IPs are engineered to handle complex mathematical calculations swiftly and accurately, making them ideal for integration into devices requiring intensive signal processing tasks.
DSP Core semiconductor IPs are widely implemented in industries like telecommunications, where they are crucial for modulating and encoding signals in mobile phones and other communication devices. They empower these devices to perform multiple operations simultaneously, including compressing audio, optimizing bandwidth usage, and enhancing data packets for better transmission quality. Additionally, in consumer electronics, DSP Cores are fundamental in audio and video equipment, improving the clarity and quality of sound and visuals users experience.
Moreover, DSP Cores are a linchpin in the design of advanced automotive systems and industrial equipment. In automotive applications, they assist in radar and lidar systems, crucial for autonomous driving features by processing the data needed for real-time environmental assessment. In industrial settings, DSP Cores amplify the performance of control systems by providing precise feedback loops and enhancing overall process automation and efficiency.
Silicon Hub's category for DSP Core semiconductor IPs includes a comprehensive collection of advanced designs tailored to various processing needs. These IPs are designed to integrate seamlessly into a multitude of hardware architectures, offering designers and engineers the flexibility and performance necessary to push the boundaries of technology in their respective fields. Whether for enhancing consumer experiences or driving innovation in industrial and automotive sectors, our DSP Core IPs bring unparalleled processing power to the forefront of digital innovations.
The Jotunn8 represents a leap in AI inference technology, delivering unmatched efficiency for modern data centers. This chip is engineered to manage AI model deployments with lightning-fast execution, at minimal cost and high scalability. It ensures optimal performance by balancing high throughput and low latency, while being extremely power-efficient, which significantly lowers operational costs and supports sustainable infrastructures. The Jotunn8 is designed to unlock the full capacity of AI investments by providing a high-performance platform that enhances the delivery and impact of AI models across applications. It is particularly suitable for real-time applications such as chatbots, fraud detection, and search engines, where ultra-low latency and very high throughput are critical. Power efficiency is a major emphasis of the Jotunn8, optimizing performance per watt to control energy as a substantial operational expense. Its architecture allows for flexible memory allocation ensuring seamless adaptability across varied applications, providing a robust foundation for scalable AI operations. This solution is aimed at enhancing business competitiveness by supporting large-scale model deployment and infrastructure optimization.
The Chimera GPNPU from Quadric is designed as a general-purpose neural processing unit intended to meet a broad range of demands in machine learning inference applications. It is engineered to perform both matrix and vector operations along with scalar code within a single execution pipeline, which offers significant flexibility and efficiency across various computational tasks. This product achieves up to 864 Tera Operations per Second (TOPs), making it suitable for intensive applications including automotive safety systems. Notably, the GPNPU simplifies system-on-chip (SoC) hardware integration by consolidating hardware functions into one processor core. This unification reduces complexity in system design tasks, enhances memory usage profiling, and optimizes power consumption when compared to systems involving multiple heterogeneous cores such as NPUs and DSPs. Additionally, its single-core setup enables developers to efficiently compile and execute diverse workloads, improving performance tuning and reducing development time. The architecture of the Chimera GPNPU supports state-of-the-art models with its Forward Programming Interface that facilitates easy adaptation to changes, allowing support for new network models and neural network operators. It’s an ideal solution for products requiring a mix of traditional digital signal processing and AI inference like radar and lidar signal processing, showcasing a rare blend of programming simplicity and long-term flexibility. This capability future-proofs devices, expanding their lifespan significantly in a rapidly evolving tech landscape.
xcore.ai is a powerful platform tailored for the intelligent IoT market, offering unmatched flexibility and performance. It boasts a unique multi-threaded micro-architecture that provides low-latency and deterministic performance, perfect for smart applications. Each xcore.ai contains 16 logical cores distributed across two multi-threaded processor tiles, each equipped with 512kB of SRAM and capable of both integer and floating-point operations. The integrated interprocessor communication allows high-speed data exchange, ensuring ultimate scalability across multiple xcore.ai SoCs within a unified development environment.
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
The eSi-3264 epitomizes the pinnacle of the eSi-RISC portfolio, presenting a 32/64-bit processor furnished with SIMD extensions catering to high-performance requirements. Designed for applications demanding digital signal processing functionality, this processor capitalizes on minimal silicon usage while ensuring exceedingly low power consumption. Incorporating an extensive pipeline capable of dual and quad multiply-accumulate operations, the eSi-3264 significantly benefits applications in audio processing, sensor control, and touch interfacing. Its built-in IEEE-754 single and double-precision floating point operations promote comprehensive data processing capabilities, extending versatility across computationally intensive domains. The processor accommodates configurable caching attributes and a memory management unit to bolster performance amidst off-chip memory access. Its robust instruction repertoire, optional custom operations, and user-privilege modes ensure full control in secure execution environments, supporting diverse operational requirements with unmatched resource efficiency.
Tensix Neo represents the next evolution in AI processing, offering robust capabilities for handling modern AI challenges. Its design focuses on maximizing performance while maintaining efficiency, a crucial aspect in AI and machine learning environments. Tensix Neo facilitates advanced computation across multiple frameworks, supporting a range of AI applications. Featuring a strategic blend of core architecture and integrated memory, Tensix Neo excels in both processing speed and capacity, essential for handling comprehensive AI workloads. Its architecture supports multi-threaded operations, optimizing performance for parallel computing scenarios, which are common in AI tasks. Tensix Neo's seamless connection with Tenstorrent's open-source software environment ensures that developers can quickly adapt it to their specific needs. This interconnectivity not only boosts operational efficiency but also supports continuous improvements and feature expansions through community contributions, positioning Tensix Neo as a versatile solution in the landscape of AI technology.
The iniDSP is a high-performance 16-bit fixed-point Digital Signal Processor (DSP) built for system-on-chip applications. Its architecture, inspired by the CD2450A design from Clarkspur Inc., provides exceptional processing power with minimal energy consumption, making it well-suited for both consumer electronics like hearing aids and more complex control systems in industrial settings. This DSP core offers enhanced computational capabilities, including a 16x16 multiplier with a 40-bit accumulator, which allows for precise and rapid signal processing tasks. Its flexible and fully synchronous design ensures compatibility with a variety of systems and technologies, supporting seamless integration into existing infrastructures or new developments. The iniDSP core is accompanied by comprehensive software tools, including an assembler, linker, and debugger, providing a solid foundation for developers to implement complex algorithms efficiently. The design’s emphasis on low power consumption, combined with robust high-performance operations, makes it an attractive choice for a broad range of applications ranging from audio processing to adaptive control systems.
The Spiking Neural Processor T1 is a microcontroller tailored for ultra-low-power applications demanding high-performance pattern recognition at the sensor edge. It features an advanced neuromorphic architecture that leverages spiking neural network engines combined with RISC-V core capabilities. This architecture allows for sub-milliwatt power dissipation and sub-millisecond latency, enabling the processor to conduct real-time analysis and identification of embedded patterns in sensor data while operating in always-on scenarios. Additionally, the T1 provides diverse interfaces, making it adaptable for use with various sensor types.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
The Codasip RISC-V BK Core Series is designed to offer highly performant solutions suitable for a range of tasks from embedded applications to more demanding compute environments. By leveraging the RISC-V architecture, the BK Core Series provides a balance of power efficiency and processing capability, which is ideal for IoT edge applications and sensor controllers. The series is built around the philosophy of flexibility, allowing for modifications and enhancements to meet specific application requirements, including the integration of custom instructions to accommodate special workloads. This series also supports functional safety and security measures as outlined by industry standards, ensuring a robust foundation for critical applications.
The SCR3 core by Syntacore is a silicon-proven microcontroller aimed at applications requiring both high performance and power efficiency. This 32/64-bit processor core supports a variety of RISC-V standard extensions, including atomic operations and bit manipulation, optimizing it for real-time applications needing reliable interrupt handling through its PLIC, ACLINT, and IPIC units. It features a 5-stage in-order pipeline paired with branch prediction and cache systems to enhance speed and execution efficiency. With considerable support for seamless memory operations, it includes both L1 and L2 caches and a TCM unit capable of housing up to 256KB of data, alongside an integrated Memory Protection Unit for executing multiple privilege modes. Ideal for industrial automation and IoT usage, the SCR3 core facilitates multicore operations with cache coherency for up to 4 simultaneous cores. Extensive development tools are provided, including simulators, IDE support, and a comprehensive FPGA-based SDK, allowing for immediate application development and deployment.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
Secure Protocol Engines offer high-performance IP blocks designed to enhance network and security processing capabilities. These engines support critical operations like cryptographic functions, dramatically offloading the central processing units within SoCs. They ensure secure communication channels for embedded systems by seamlessly integrating into existing security frameworks, thereby bolstering the system's defense mechanisms against potential cyber threats.
The **Ceva-SensPro DSP family** unites scalar processing units and vector processing units under an 8-way VLIW architecture. The family incorporates advanced control features such as a branch target buffer and a loop buffer to speed up execution and reduce power. There are six family members, each with a different array of MACs, targeted at different application areas and performance points. These range from the Ceva-SP100, providing 128 8-bit integer or 32 16-bit integer MACs at 0.2 TOPS performance for compact applications such as vision processing in wearables and mobile devices; to the Ceva-SP1000, with 1024 8-bit or 256 16-bit MACs reaching 2 TOPS for demanding applications such as automotive, robotics, and surveillance. Two of the family members, the Ceva-SPF2 and Ceva-SPF4, employ 32 or 64 32-bit floating-point MACs, respectively, for applications in electric-vehicle power-train control and battery management. These two members are supported by libraries for Eigen Linear Algebra, MATLAB vector operations, and the TVM graph compiler. Highly configurable, the vector processing units in all family members can add domain-specific instructions for such areas as vision processing, Radar, or simultaneous localization and mapping (SLAM) for robotics. Integer family members can also add optional floating-point capabilities. All family members have independent instruction and data memory subsystems and a Ceva-Connect queue manager for AXI-attached accelerators or coprocessors. The Ceva-SensPro2 family is programmable in C/C++ as well as in Halide and Open MP, and supported by an Eclipse-based development environment, extensive libraries spanning a wide range of applications, and the Ceva-NeuPro Studio AI development environment. [**Learn more about Ceva-SensPro2 solution>**](https://www.ceva-ip.com/product/ceva-senspro2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_senspro2_page)
The Universal Drive Controller is an advanced motion control solution tailored for DC, brushless, and stepper motors. Encompassing position control and a sophisticated trajectory planner, this IP core eliminates the necessity for additional drive control chips, optimizing PCB space and system bill of materials. By choosing this Enclustra IP core, developers benefit from significantly reduced time-to-market and decreased system costs. Engineered for low total solution cost, the Universal Drive Controller supports a range of motors and encoders with field-oriented control for BLDC motors. It boasts autonomous error handling and provides excellent reusability due to its configurable structure. This IP core is capable of handling up to eight drives per controller, featuring up to four PID controllers per drive, enhancing precision and efficiency in motion control applications. Integration with existing systems is streamlined due to its industry-standard AXI-4 interface, and the IP core is fully compatible with leading development environments such as Quartus and Vivado. Designed to foster easy customization and integration, it significantly lowers CPU load thanks to its autonomous control loops and offers substantial parallel processing power without compromising on precision.
The SCR4 core is a high-performance, area-efficient RISC-V processor with floating-point computation capabilities. Targeting mobile and industrial applications, it supports both single and double precision, adhering to IEEE 754-2008 standards. Its instruction set is complete with advanced extensions, including atomic and cryptography functions for secure and efficient operations. With a powerful 5-stage in-order pipeline and a dedicated FPU, the SCR4 can handle complex mathematical tasks swiftly. Its memory architecture features both L1 and L2 caches, alongside a TCM unit, enabling rapid data access and management essential in real-time environments. Incorporating a robust branch prediction unit and support for multicore setups, the SCR4 excels in environments demanding synchronized computing tasks across multiple processors. It’s supported by comprehensive development kits and detailed documentation to expedite the design and implementation processes across diverse platforms.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The Universal DSP Library offers a comprehensive suite of digital signal processing components optimized for FPGA implementations. This library integrates seamlessly with the AMD Vivado ML Design Suite, providing essential components such as FIR filters, CIC decimating filters, mixers, and CORDIC function approximations. It includes tools that facilitate the connection of DSP systems together, allowing for rapid assembly of signal processing chains using Vivado’s GUI or direct VHDL instantiation. Each component within the library is accessible in both raw VHDL code and as an AMD Vivado ML Design Suite IPI block. This dual availability enables quick development and simulation of processing chains before moving to FPGA implementation. The Universal DSP Library is equipped with bit-true software models for each DSP block, allowing developers to evaluate and optimize systems in software to ensure precise functioning when deployed on hardware. Key features include support for multiple data channels, continuous wave, and pulse processing, as well as real and complex signal support. It utilizes the AXI4-Stream protocol, providing a standardized interface that simplifies integration and enhances the development of specific DSP solutions. The library is suitable for applications ranging from software-defined radio and communication systems to robotics and medical diagnostics, showcasing its versatility in various high-tech fields.
The iCan PicoPop® is a sophisticated System on Module (SOM) based on Xilinx's Zynq UltraScale+. This miniaturized module is pivotal in simulations requiring high-performance processes like video signal processing within aerospace applications. It serves as the backbone for complex embedded systems, ensuring reliable and efficient operation in demanding environments.
The Tyr AI Processor Family is designed around versatile programmability and high performance for AI and general-purpose processing. It consists of variants such as Tyr4, Tyr2, and Tyr1, each offering a unique performance profile optimized for different operational scales. These processors are fully programmable and support high-level programming throughout, ensuring they meet diverse computing needs with precision. Each member of the Tyr family features distinct core configurations, tailored for specific throughput and performance needs. The top-tier Tyr4 boasts 8 cores with a peak capability of 1600 Tflops when leveraging fp8 tensor cores, making it suitable for demanding AI tasks. Tyr2 and Tyr1 scale down these resources to 4 and 2 cores, respectively, achieving proportional efficiency and power savings. All models incorporate substantial on-chip memory, optimizing data handling and execution efficiency without compromising on power use. Moreover, the Tyr processors adapt AI processes automatically on a layer-by-layer basis to enhance implementation efficiency. This adaptability, combined with their near-theory performance levels, renders them ideal for high-throughput AI workloads that require flexible execution and dependable scalability.
The Satellite Navigation SoC Integration offered by GNSS Sensor Ltd stands at the forefront of satellite-based navigation solutions. This product focuses on integrating multiple navigation systems like GPS, GLONASS, and Galileo into a single system-on-chip (SoC), offering a comprehensive satellite tracking mechanism. By harnessing independent fast search engines for each navigation system, this solution ensures an efficient and swift signal acquisition and processing capability. The integration process is streamlined through the use of their versatile GNSS library, which provides simplicity in merging these navigation systems into various platforms. This modularity and ease of deployment make it highly compatible with both ASIC and FPGA platforms, allowing rapid prototyping and faster time-to-market. The SoC integration also includes power management features ensuring optimal performance of the navigation systems while conserving energy. Engineered for robust performance, the Satellite Navigation SoC Integration is positioned as a highly adaptable solution. It accommodates varying configuration needs from different applications, providing high levels of precision and reliability, and is capable of handling complex signal processing tasks. With advancements in its design, the SoC can effectively serve as a foundational component in consumer electronics, automotive navigation systems, and more.
TUNGA is an advanced System on Chip (SoC) leveraging the strengths of Posit arithmetic for accelerated High-Performance Computing (HPC) and Artificial Intelligence (AI) tasks. The TUNGA SoC integrates multiple CRISP-cores, employing Posit as a core technology for real-number calculations. This multi-core RISC-V SoC is uniquely equipped with a fixed-point accumulator known as QUIRE, which allows for extremely precise computations across vectors as long as 2 billion entries. The TUNGA SoC includes programmable FPGA gates for enhancing field-critical functions. These gates are instrumental in speeding up data center services, offloading tasks from the CPU, and advancing AI training and inference efficiency using non-standard data types. TUNGA's architecture is tailored for applications demanding high precision, including cryptography and variable precision computing tasks, facilitating the transition towards next-generation arithmetic. In the computational ecology, TUNGA stands out by offering customizable features and rapid processing capabilities, making it suitable not only for typical data center functions but also for complex, precision-demanding workloads. By capitalizing on Posit arithmetic, TUNGA aims to deliver more efficient and powerful computational performance, reflecting a strategic advancement in handling complex data-oriented processes.
The Codasip L-Series DSP Core is engineered to deliver exceptional digital signal processing capabilities, boasting high configurability to accommodate a range of signal processing tasks. Ideal for applications that require intensive computation like audio processing, the L-Series excels in scenarios demanding high performance from constrained power and area budgets. Utilizing the RISC-V architecture, it supports extensive customization, empowering users to tweak instruction sets and enhance microarchitectural elements for tailored efficiency. Beyond its raw processing prowess, the L-Series DSP Core incorporates advanced verification protocols ensuring reliability in critical operations, all while staying adaptable to the shifting demands of modern technological applications.
AON1100 is acclaimed as the leading edge AI chip optimized for voice and sensor applications. With a power consumption of less than 260µW, it excels in delivering near-perfect accuracy even in challenging environments. This makes it indispensably suited for continuously active devices that require both precision and energy efficiency.
The Cottonpicken DSP Engine is a sophisticated micro-coded digital signal processor designed to handle complex data conversion tasks efficiently. Developed in-house, this DSP engine offers versatility in pixel data manipulation, including Bayer pattern decoding and YUV conversion. It supports various formats such as YUV 4:2:2 or RGB and is capable of processing filter kernels up to 5x5, making it suitable for a wide range of image processing applications. Capable of operating at clock speeds up to 150 MHz, this engine provides high-speed data processing applicable to real-time video conversion and multimedia tasks. The architecture is designed to facilitate the seamless translation of raw pixel data into formats suitable for further processing or display. Given its powerful matrix operations and programmable delay configurations, the Cottonpicken DSP Engine is ideal for real-time image conversion tasks where flexibility and speed are critical. This DSP core, available as a closed-source netlist, emphasizes section5's ability to deliver high-performance solutions tailored to specific customer needs. By incorporating advanced matrix operations and various color space conversions, the Cottonpicken engine offers an all-inclusive solution for developers looking to implement advanced digital signal processing in their products while maintaining high throughput and precision.
The TSP1 Neural Network Accelerator is a state-of-the-art AI chip designed for versatile applications across various industries, including voice interfaces, biomedical monitoring, and industrial IoT. Engineered for efficiency, the TSP1 handles complex workloads with minimal power usage, making it ideal for battery-powered devices. This AI chip is capable of advanced bio-signal classification and natural voice interface integration, providing self-contained processing for numerous sensor signal applications. A notable feature is its high-efficiency neural network processing element fabric, which empowers signal pattern recognition and other neural network tasks, thereby reducing power, cost, and latency. The TSP1 supports powerful AI inference processes with low latency, enabling real-time applications like full vocabulary speech recognition and keyword spotting with minimal energy consumption. It's equipped with multiple interfaces for seamless integration and offers robust on-chip storage for secure network and firmware management. The chip is available in various packaging options to suit different application requirements.
The Domain-Specific RISC-V Cores from Bluespec are engineered to facilitate hardware acceleration in a streamlined and efficient manner. By packaging accelerators as software threads, these cores deliver high concurrency and efficient system performance. The scalability embedded in this technology caters to a range of application needs, enabling systematic hardware acceleration for developers and organizations aiming to optimize RISC-V implementations.
The NoISA Processor by Hotwright Inc. is designed to revolutionize conventional processing paradigms by eliminating the constraints of fixed instruction set architectures. Utilizing the Hotstate machine, this processor is an advanced runtime loadable microcoded algorithmic state machine that operates based on a specialized subset of C code. Unlike traditional processors that use predefined ALUs, register files, and controllers, the NoISA Processor is highly adaptable, allowing for dynamic modifications via microcode rather than rigid instructions. The design philosophy behind the NoISA Processor is to offer a solution for applications where traditional softcore CPUs are either too resource-intensive or insufficiently fast. It excels in power efficiency, making it particularly suitable for edge computing and IoT devices where every milliwatt counts. With the ability to rapidly design small, efficient controllers or C-programmable state machines, it provides unparalleled freedom and performance without being tied to a fixed instruction set. Additionally, the NoISA Processor offers significant advantages for systolic arrays and FPGA-related applications, allowing changes in the behavior without hardware modification. This flexibility enables developers to achieve peak performance levels as the processor's behavior can be updated by simply reloading microcode, thus offering a more agile and powerful alternative to traditional processors.
The Prodigy Universal Processor from Tachyum is a groundbreaking innovation designed to revolutionize data center performance. It remarkably integrates the power of CPUs, GPGPUs, and TPUs into a single homogeneous architecture. This processor architecture supports not only general computing tasks but also excels in high-performance computing, AI, and deep machine learning applications. The Prodigy is engineered to reduce power consumption drastically while significantly boosting server utilization and space efficiency, a much-needed advantage for modern data centers. One of its most praised attributes is its unrivaled performance per watt, being able to deliver up to 18 times higher performance and six times better energy efficiency compared to its peers. The processor's design overcomes the technological bottlenecks that have traditionally hindered data center efficiency, such as excessive power usage and low server utilization rates. Its streamlined architecture simplifies programming, offering a coherent multiprocessor model that easily integrates into existing data center infrastructures. Moreover, Tachyum's Universal Processor breaks free from the constraints imposed by Moore's Law, setting new standards in computational power and energy utilization. Its innovative approach allows seamless execution of traditional and high-demand AI tasks without necessitating significant overhauls in the software environment. As such, this processor is poised to be a key player in emerging technologies, driving future developments in AI and helping propel forward-thinking organizational strategies across the globe.
The AON1000 is a cutting-edge AI processing engine designed with super low-power and high-accuracy capabilities for edge applications. It's specifically built for efficient wake word, voice command, acoustic event, and speaker identification, making it ideal for devices that need to be always on, such as wearables and IoT devices. AON1000 utilizes proprietary neural network architectures and tuned inference algorithms, ensuring unmatched performance in real-world conditions that are typically noisy.
The AON1020 enhances the capabilities of edge AI by addressing not only voice and audio but also various sensor applications. It extends the AONSens™ Neural Network cores line to include comprehensive sensor activities such as human motion detection. This IP delivers its AI processing engine in Verilog RTL, making it versatile for inclusion in numerous ASIC and FPGA designs, while maintaining a focus on low power consumption and high functional accuracy.
The Neural Network Accelerator by Gyrus AI is designed for high-performance and energy-efficient computation in edge computing environments. With a core focus on maximizing throughput and minimizing latency, this accelerator implements advanced graph processing techniques. It achieves impressive performance metrics, delivering up to 30 Tera Operations Per Second per Watt (TOPS/W), alongside significantly lower power requirements, thanks to its optimized memory usage configurations. This minimizes the die area and power consumption while supporting various neural network models efficiently. Leveraging this technology, companies can enhance computational speed and reduce energy expenditure in their AI applications, making it particularly suitable for enterprises aiming to deploy AI at scale on the edge. Gyrus AI's solution also includes complementary software tools that facilitate seamless integration and operation of neural networks, ensuring they run smoothly on the hardware without extensive manual intervention. The Neural Network Accelerator thus stands out as a critical component for businesses looking to leverage AI-powered tools and applications on reduced hardware footprints, emphasizing not just performance, but also operational economy and sustainability. Supported by state-of-the-art software applications and designed for easy adaptability across various hardware architectures, this solution empowers enterprises to transition smoothly to AI-driven operations, enhancing both computing efficiency and strategic business outcomes.
eSi-Floating Point cores offer a complete suite for executing IEEE 754-2008 compliant floating-point arithmetic operations, integral for projects requiring mathematical precision and effective data handling in sophisticated computing environments. These operations include addition, subtraction, multiplication, division, and more, applicable for single, double, and half-precision contexts. Cores within this suite are engineered to accommodate denormalized numbers, infinities, NaNs, and support rounding strategies alongside exception flags indicating calculation precision or errors. This solidifies their functionally robust design adaptable to diverse floating-point processor requirements. Fully pipelined to ensure one output per cycle, the distribution of these IP cores includes technology-independent formats (Verilog HDL), ensuring compatibility across ASIC and FPGA deployments. This versatility makes them an essential asset for computational applications across industries demanding high precision and consistent performance.
Advanced Silicon's Specialty Microcontrollers set a new standard in high-performance computing with their integration of cutting-edge RISC-V architectures and advanced coprocessing capabilities. These MCUs are tailored for demanding applications requiring precise and rapid data processing, including image processing and complex algorithm execution. The specialty microcontrollers boast sophisticated features like embedded algorithms that cater to modern interactive touchscreen and machine learning applications. They perfectly complement Advanced Silicon's touch components, providing high levels of user interface innovation, system reliability, and operational efficiency. Whether for small-scale or expansive digital touch interfaces, these MCUs offer the processing power and integration needed to meet the demands of interactive technology solutions. Advanced Silicon continues to enhance these MCUs’ feature sets, keeping them at the forefront of technological capabilities in computing and interfacing systems.
The ARC Processor IP provided by Synopsys stands out with its customizable architecture tailored for a variety of embedded system applications. This processor IP supports 32-/64-bit execution, featuring an extensible instruction set that can be modified for specific processing needs. Suitable for automotive applications requiring real-time performance, the ARC Processor IP delivers energy-efficient operations, essential for applications like IoT devices and mobile computing. Additionally, the processor infrastructure is supported by a comprehensive toolchain, enabling developers to fine-tune software performance to boost system efficiency. Its low power and high-performance capabilities make it a preferred choice for modern, versatile embedded designs.
The nxFramework Development Kit is a comprehensive FPGA development environment aimed at simplifying the creation and management of ultra-low latency applications in the financial industry. This framework combines hardware and software tools to support a wide range of FPGA applications, including trading engines, risk gateways, and data distribution systems. With a focus on reducing time-to-production, nxFramework offers a vast library of utility cores and connectivity components that provide essential building blocks for high-performance projects. Features like memory management and math functions are optimized for low latency, helping developers efficiently build and deploy applications. The platform also includes in-depth support for test bench setups, simulation tools, and live debugging environments, ensuring a seamless development process from conception to implementation. Capable of integrating with various hardware platforms, nxFramework facilitates the development of portable, robust, and scalable FPGA solutions tailored for the fast-evolving financial markets.
The Blazar Bandwidth Accelerator Engine is a cutting-edge solution for enhancing the performance of FPGA-based systems. This IC specializes in in-memory compute capabilities, enabling the acceleration of functions while providing high capacity, low latency memory for demanding applications. With bandwidth capabilities reaching an impressive 640 Gbps, this engine manages 5 billion reads per second, ideal for high-speed data environments. Incorporating optional RISC cores for enhanced computation, the Blazar Bandwidth Accelerator Engine supports dual port memory configurations and comes with 576Mb or 1Gb of embedded memory. These features make it well-suited for applications like SmartNIC & SmartSwitch, metering and statistics, and 5G UPF and BNG offload. Blazar's integration into systems allows for efficient serial link aggregation and simplifies the sub-system design for high-performing network infrastructures. The design focus on in-memory compute makes it a powerful tool for modern communication and data processing needs.
The Prodigy FPGA-Based Emulator by Tachyum offers a versatile platform for testing and evaluating the performance of their universal processors. This hardware emulator uses multiple FPGA and IO boards, networked within a rack configuration, providing a comprehensive environment for performance measurement and debugging. It supports product evaluation at scale, giving users the ability to test and develop applications efficiently. Designed to emulate full processor cores, each board in the system includes vector and matrix fixed and floating-point processing units, ensuring that a wide variety of computational tasks can be accurately simulated. The architecture of the emulator is particularly beneficial for organizations needing to assess software development and compatibility testing across various hardware configurations. Tachyum’s emulator system becomes an invaluable asset for enterprises planning to integrate Prodigy processors into their infrastructure by providing a low-cost, low-risk evaluation method. This platform aids partners and developers in understanding how Prodigy's unique processor capabilities can be fully exploited in real-world applications, thereby facilitating a smoother transition from existing architectures to Tachyum’s advanced computing solutions.
The RFicient chip, designed for Internet of Things (IoT) applications, is renowned for its energy efficiency and wireless communication capabilities. This chip has been exactly engineered to drastically reduce power consumption, making it a pivotal component in sustainable IoT solutions. It plays a critical role in IoT devices, seeking to maximize data transmission while minimizing energy use, catering to an ever-expanding network of interconnected devices. By utilizing the RFicient chip, users can leverage advancements in technology while ensuring beneficial environmental impacts. One notable feature of the RFicient chip is its capability to handle a massive volume of messages daily, making it integral to Industrial IoT applications that require robust and reliable communication streams. Its adaptability allows deployment across various IoT domains, thus supporting varied applications, from smart agriculture to industrial automation. The innovation behind the RFicient chip lies in its capacity to perform effectively within sub-GHz spectrum ranges, ensuring long-range connectivity and resilience against interference. This makes it an attractive solution for environments that require a stable, far-reaching, and energy-frugal connectivity option. Its adoption is set to enhance efficiency and sustainability across industries that depend on IoT technologies.
Menta’s Adaptive Digital Signal Processor (DSP) is tailored for managing and optimizing signal processing tasks within embedded systems. This IP is ideal for applications demanding high processing performance without compromising energy consumption or space. Utilizing Menta’s standard-cell approach, this DSP ensures ease of integration across various process nodes with high efficiency. Integrated with customizable algorithms and interfaces, Menta’s DSP provides engineers the flexibility to implement specific processing tasks tailored to their applications. This adaptability is crucial for areas like real-time data analysis and machine learning, where rapid response and prediction accuracy are essential. By leveraging the advantages of Menta’s eFPGA base, such processors offer exemplary processing speed, reduced latency, and energy-efficient operation. These attributes significantly contribute to optimizing applications across sectors including automotive, telecommunications, and portable electronics, making Menta’s DSP a standout choice for developers seeking performance and innovation.
TimeServo serves as a precise FPGA system timer or clock that supports line-rate independent packet timestamping while addressing high-resolution, modest accuracy timekeeping needs. Engineered with a PI-DPLL, it synchronizes local TCXO with an external 1 PPS signal, enabling high syntonicity and facilitating accurate timestamping with MAC-integrated environments. The component can be extended to TimeServoPTP for a fully compliant IEEE-1588v2/PTP configuration, creating a standalone slave device without the need for host intervention. Providing up to 32 runtime-tunable outputs, TimeServo operates independently across diverse clock domains and supports various output formats including binary, IEEE ordinary, and transparent. Management and observability through an AXI control plane enable dynamic time adjustments and phase-frequency monitoring, ensuring operational adaptability. The attribute of using a standard AXI4-Lite interface strengthens integration prospects with existing FPGA setups. TimeServo's robust phase lock capabilities are backed by a 120-bit resolution phase accumulator and phase-locked loop (PLL) systems capable of maintaining jitter accuracy and flexibility. The design advances are supplemented with application examples and software tools to ease setup and implementation, supporting a wide range of time-sensitive industrial applications.
Meet our high-performance Low SWaP SDR optimized for AI & ML at the RF edge. Optimized for small form factor applications with challenging SWaP-C requirements and superior integration capabilities, it is ideal for applications like UsX payloads.
The Miscellaneous FEC and DSP IP Cores from Creonic encompass a comprehensive range of digital signal processing and forward error correction solutions tailored for various communication challenges. These cores are pivotal for enhancing signal integrity and performance across diverse communication frameworks. A standout feature within this collection is the Fast Fourier Transform (FFT/IFFT) core, which is crucial in converting signals between time and frequency domains, a key process in modern communication systems. Meanwhile, the DVB-GSE encapsulates data, optimizing payload organization for effective data transfer in broadcasting and network systems. Additional offerings include exemplary channel simulations, such as the Doppler Channel Core, which is essential for accurately predicting signal behavior in dynamic environments. These cores are crafted to provide maximum efficiency and can be seamlessly adapted for specific application requirements, ensuring high performance and resilience across a range of technological landscapes.
The AON1010 is tailored for processing microphone data for voice and audio recognition. As part of the AONVoice™ Neural Network cores line, this IP provides a robust framework for developing applications that require high accuracy in varying auditory environments. Its delivery in Verilog RTL makes it accessible for a range of fabrication technologies, such as ASIC and FPGA, allowing vast customization in product development.
The Atria Logic AL-AVPLR-IPC player is a low power, file-based AV decoder targeting industrial and consumer electronics applications. It features a compact design suitable for energy-efficient environments, such as digital signage and infotainment systems in transportation and hospitality industries. The player combines an H.264 Baseline Profile HD decoder and an AAC-LC stereo decoder, with a versatile interface that supports essential playback controls. Constructed on a Xilinx Zynq 7010 FPGA platform, the player comprises ARM Cortex-A9 cores and Neon DSP engines, leveraging these processors for its operations while leaving FPGA gates available for additional developments. This low power implementation aligns with cost-sensitive applications, offering an adaptable solution to diverse AV content needs in dynamic environments. The AV Player's Linux-based operation and compatibility with the GStreamer framework make it flexible and readily customizable. Whether enhancing digital media presentations in public spaces or functioning within automotive infotainment systems, this player offers a complete solution that balances power efficiency with performance robustness.
Building upon the foundation of AON1100, the AON1120 introduces enhanced input/output capabilities and RISC-V support. Designed for smart home and automotive contexts, it provides extensive flexibility in developing applications that benefit from more robust processing and expanded interfacing opportunities.
The FPGA Image Processing Core is designed to deliver high-performance image processing capabilities, making it suitable for advanced applications in surveillance, robotics, and industrial inspection. This core leverages the computational power of FPGAs to process vast amounts of image data real-time. Utilizing parallel processing, the FPGA Image Processing Core can perform operations such as image filtering, edge detection, feature extraction, and more, all with reduced latency. Its capabilities allow for complex image analytics to be conducted at high frame rates, expanding the potential for applications requiring precision and speed. Its integration flexibility makes it a powerful tool for developing bespoke imaging solutions custom-tailored to specific needs. By streamlining intricate image processing tasks, this core enhances the effectiveness and responsiveness of vision-based systems, contributing to more intelligent automation and detailed visual assessments.
The xcore-200 series is engineered for embedded system designers aiming to innovate with specific interfaces and capabilities. This platform offers a high level of customization, supported by fast processing, low-latency performance, and scalability across a range of multicore options. Available with up to 32 cores and featuring on-chip memory, it supports applications requiring USB, RGMII Gigabit Ethernet, and Flash memory options, ensuring it meets modern IoT demands with ease. With integrated features like secure boot and support for multiple interfaces, xcore-200 is an ideal choice for today's dynamic and growing market.
The Electrical PAM-X DSP from 1-VIA is engineered to enhance signal transmission over copper networks, maximizing data throughput while minimizing power consumption. This product is pivotal for active electrical cables, enabling long-distance transmission with superior signal integrity. With its state-of-the-art design, the Electrical PAM-X DSP sets new standards in high-speed data movement, making it an indispensable asset for modern data centers. This DSP technology paves the way for revolutionary advancements in connectivity by significantly improving bandwidth performance over existing copper infrastructures. Integrating seamlessly into diverse applications, the Electrical PAM-X DSP ensures reliable and efficient data processing across extensive networks. Its innovative approach allows for enhanced signal clarity, catering to industries seeking high-speed, low-power solutions. Ideal for a variety of telecommunications needs, the DSP serves as a cornerstone for developing improved copper-based communication modules. Benefiting from 1-VIA's advanced engineering and extensive testing, the Electrical PAM-X DSP promises market-leading performance. Users can expect unparalleled data handling capabilities, which are crucial for the ongoing evolution of digital and telecommunication infrastructures. Its compatibility with existing systems makes it easy to deploy and manage, offering great flexibility to users seeking to upgrade their networking environments and satisfy increasing demands for bandwidth-intensive applications.
The Complex DSP Engine provided by IPCoreWorx incorporates advanced digital signal processing with a robust architecture designed to optimize performance. It is delivered as a netlist or synthesizable RTL source code in VHDL, complete with a comprehensive verification test bench and vectors also in VHDL. The package includes detailed integration documentation and user guides to ensure that developers can effectively implement the engine into their systems. This DSP Engine is particularly adept at handling complex computational tasks, offering significant enhancements in processing speed and efficiency.
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