All IPs > Platform Level IP > Processor Core Independent
In the ever-evolving landscape of semiconductor technologies, processor core independent IPs play a crucial role in designing flexible and scalable digital systems. These semiconductor technologies offer the versatility of enabling functionalities independent of a specific processor core, making them invaluable for a variety of applications where flexibility and reusability are paramount.
Processor core independent semiconductor IPs are tailored to function across different processor architectures, avoiding the constraints tied to any one specific core. This characteristic is particularly beneficial in embedded systems, where designers aim to balance cost, performance, and power efficiency while ensuring seamless integration. These IPs provide solutions that accommodate diverse processing requirements, from small-scale embedded controllers to large-scale data centers, making them essential components in the toolkit of semiconductor design engineers.
Products in this category often include memory controllers, I/O interfaces, and various digital signal processing blocks, each designed to operate autonomously from the central processor's architecture. This independence allows manufacturers to leverage these IPs in a broad array of devices, from consumer electronics to automotive systems, without the need for extensive redesigns for different processor families. Moreover, this flexibility championed by processor core independent IPs significantly accelerates the time-to-market for many devices, offering a competitive edge in high-paced industry environments.
Furthermore, the adoption of processor core independent IPs supports the development of customized, application-specific integrated circuits (ASICs) and system-on-chips (SoCs) that require unique configurations, without the overhead of processor-specific dependencies. By embracing these advanced semiconductor IPs, businesses can ensure that their devices are future-proof, scalable, and capable of integrating new functionalities as technologies advance without being hindered by processor-specific limitations. This adaptability positions processor core independent IPs as a vital cog in the machine of modern semiconductor design and innovation.
The CXL 3.1 Switch by Panmnesia is a high-performance solution facilitating flexible and scalable inter-device connectivity. Designed for data centers and HPC systems, this switch supports extensive device integration, including memory, CPUs, and accelerators, thanks to its advanced connectivity features. The switch's design allows for complex networking configurations, promoting efficient resource utilization while ensuring low-latency communication between connected devices. It stands as an essential component in disaggregated compute environments, driving down latency and operational costs.
Axelera AI has crafted a PCIe AI acceleration card, powered by their high-efficiency quad-core Metis AIPU, to tackle complex AI vision tasks. This card provides an extraordinary 214 TOPS, enabling it to process the most demanding AI workloads. Enhanced by the Voyager SDK's streamlined integration capabilities, this card promises quick deployment while maintaining superior accuracy and power efficiency. It is tailored for applications that require high throughput and minimal power consumption, making it ideal for edge computing.
Exostiv is designed to provide significant visibility inside FPGA systems, enabling engineers to conduct real-environment testing and ensure that designs function efficiently before entering production. Featuring high-speed probes capable of capturing complex signals, Exostiv supports advanced FPGA debugging through its user-centric interface and adaptable insertion flows. It facilitates both pre-silicon validation and debugging by allowing in-depth monitoring across various clock domains. With connectivity options like QSFP28 and SAMTEC ARF-6, Exostiv empowers engineers with a flexible approach to manage different prototyping platforms effectively. The scalability of Exostiv allows its users to adapt to diverse FPGA configurations by adjusting the number and type of probes. Exostiv significantly reduces the likelihood of FPGA bugs in end-user environments by enabling engineers to thoroughly validate and adjust designs dynamically as needed. Its modular setup characterizes the adaptive nature of Exostiv’s architecture, making it suitable for application-specific optimizations in complex design environments.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The Yitian 710 Processor is an advanced Arm-based server chip developed by T-Head, designed to meet the extensive demands of modern data centers and enterprise applications. This processor boasts 128 high-performance Armv9 CPU cores, each coupled with robust caches, ensuring superior processing speeds and efficiency. With a 2.5D packaging technology, the Yitian 710 integrates multiple dies into a single unit, facilitating enhanced computational capability and energy efficiency. One of the key features of the Yitian 710 is its memory subsystem, which supports up to 8 channels of DDR5 memory, achieving a peak bandwidth of 281 GB/s. This configuration guarantees rapid data access and processing, crucial for high-throughput computing environments. Additionally, the processor is equipped with 96 PCIe 5.0 lanes, offering a dual-direction bandwidth of 768 GB/s, enabling seamless connectivity with peripheral devices and boosting system performance overall. The Yitian 710 Processor is meticulously crafted for applications in cloud services, big data analytics, and AI inference, providing organizations with a robust platform for their computing needs. By combining high core count, extensive memory support, and advanced I/O capabilities, the Yitian 710 stands as a cornerstone for deploying powerful, scalable, and energy-efficient data processing solutions.
The Chimera GPNPU by Quadric redefines AI computing on devices by combining processor flexibility with NPU efficiency. Tailored for on-device AI, it tackles significant machine learning inference challenges faced by SoC developers. This licensable processor scales massively offering performance from 1 to 864 TOPs. One of its standout features is the ability to execute matrix, vector, and scalar code in a single pipeline, essentially merging the functionalities of NPUs, DSPs, and CPUs into a single core. Developers can easily incorporate new ML networks such as vision transformers and large language models without the typical overhead of partitioning tasks across multiple processors. The Chimera GPNPU is entirely code-driven, empowering developers to optimize their models throughout a device's lifecycle. Its architecture allows for future-proof flexibility, handling newer AI workloads as they emerge without necessitating hardware changes. In terms of memory efficiency, the Chimera architecture is notable for its compiler-driven DMA management and support for multiple levels of data storage. Its rich instruction set optimizes both 8-bit integer operations and complex DSP tasks, providing full support for C++ coded projects. Furthermore, the Chimera GPNPU integrates AXI Interfaces for efficient memory handling and configurable L2 memory to minimize off-chip access, crucial for maintaining low power dissipation.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
The RISC-V Core-hub Generators from InCore are tailored for developers who need advanced control over their core architectures. This innovative tool enables users to configure core-hubs precisely at the instruction set and microarchitecture levels, allowing for optimized design and functionality. The platform supports diverse industry applications by facilitating the seamless creation of scalable and customizable RISC-V cores. With the RISC-V Core-hub Generators, InCore empowers users to craft their own processor solutions from the ground up. This flexibility is pivotal for businesses looking to capitalize on the burgeoning RISC-V ecosystem, providing a pathway to innovation with reduced risk and cost. Incorporating feedback from leading industry partners, these generators are designed to lower verification costs while accelerating time-to-market for new designs. Users benefit from InCore's robust support infrastructure and a commitment to simplifying complex chip design processes. This product is particularly beneficial for organizations aiming to integrate RISC-V technology efficiently into their existing systems, ensuring compatibility and enhancing functionality through intelligent automation and state-of-the-art tools.
The Talamo SDK is a comprehensive software development toolkit designed to facilitate the creation and deployment of advanced neuromorphic AI models on Innatera's Spiking Neural Processor (SNP). It integrates into the PyTorch environment, allowing developers to seamlessly build, train, and deploy neural network models, enhancing flexibility and accessibility in developing AI applications tailored to specific needs without requiring detailed expertise in neuromorphic computing. Talamo enhances the development workflow by offering standard and custom function integration, model zoo access, and application pipeline construction. The SDK provides profiling and optimization tools to ensure applications are both efficient and performant, allowing for quick design iterations. It also includes a hardware architecture simulator, enabling developers to validate and iterate their designs rapidly before implementation on actual hardware. With the Talamo SDK, developers can exploit the SNP's heterogeneous computing capabilities, utilizing its diverse architectural elements to optimize application performance. Additionally, its support for end-to-end application development, without the necessity of deep SNN knowledge, allows for broader reach and application, from research to industrial solutions.
The AndeShape Platforms are designed to streamline system development by providing a diverse suite of IP solutions for SoC architecture. These platforms encompass a variety of product categories, including the AE210P for microcontroller applications, AE300 and AE350 AXI fabric packages for scalable SoCs, and AE250 AHB platform IP. These solutions facilitate efficient system integration with Andes processors. Furthermore, AndeShape offers a sophisticated range of development platforms and debugging tools, such as ADP-XC7K160/410, which reinforce the system design and verification processes, providing a comprehensive environment for the innovative realization of IoT and other embedded applications.
The Jotunn8 is engineered to redefine performance standards for AI datacenter inference, supporting prominent large language models. Standing as a fully programmable and algorithm-agnostic tool, it supports any algorithm, any host processor, and can execute generative AI like GPT-4 or Llama3 with unparalleled efficiency. The system excels in delivering cost-effective solutions, offering high throughput up to 3.2 petaflops (dense) without relying on CUDA, thus simplifying scalability and deployment. Optimized for cloud and on-premise configurations, Jotunn8 ensures maximum utility by integrating 16 cores and a high-level programming interface. Its innovative architecture addresses conventional processing bottlenecks, allowing constant data availability at each processing unit. With the potential to operate large and complex models at reduced query costs, this accelerator maintains performance while consuming less power, making it the preferred choice for advanced AI tasks. The Jotunn8's hardware extends beyond AI-specific applications to general processing (GP) functionalities, showcasing its agility. By automatically selecting the most suitable processing paths layer-by-layer, it optimizes both latency and power consumption. This provides its users with a flexible platform that supports the deployment of vast AI models under efficient resource utilization strategies. This product's configuration includes power peak consumption of 180W and an impressive 192 GB on-chip memory, accommodating sophisticated AI workloads with ease. It aligns closely with theoretical limits for implementation efficiency, accentuating VSORA's commitment to high-performance computational capabilities.
Time-Triggered Ethernet (TTEthernet) represents a significant advancement in network technology by integrating time-triggered communication over standard Ethernet infrastructures. This technology is designed to meet the stringent real-time requirements of aerospace and industrial applications, offering deterministic data transfer alongside regular Ethernet traffic within a shared network. TTEthernet delivers seamless synchronization across all network devices, ensuring that time-critical data packets are processed with precise timing. This capability is essential for applications where simultaneous actions from multiple systems require tight coordination, such as flight control systems or automated industrial processes. The protocol's compatibility with existing Ethernet environments allows for easy integration into current systems, reducing costs associated with network infrastructure upgrades. TTEthernet also enhances network reliability through redundant data paths and failover mechanisms, which guarantee continuous operation even in the event of link failures. As a result, TTEthernet provides a future-proof solution for managing both regular and mission-critical data streams within a single unified network environment. Its capacity to support various operational modes makes it an attractive choice for industries pursuing high standards of safety and efficiency.
The Dynamic Neural Accelerator (DNA) II offers a groundbreaking approach to enhancing edge AI performance. This neural network architecture core stands out due to its runtime reconfigurable architecture that allows for efficient interconnections between compute components. DNA II supports both convolutional and transformer network applications, accommodating an extensive array of edge AI functions. By leveraging scalable performance, it makes itself a valuable asset in the development of systems-on-chip (SoC) solutions. DNA II is spearheaded by EdgeCortix's patented data path architecture, focusing on technical optimization to maximize available computing resources. This architecture uniquely allows DNA II to maintain low power consumption while flexibly adapting to various task demands across diverse AI models. Its higher utilization rates and faster processing set it apart from traditional IP core solutions, addressing industry demands for more efficient and effective AI processing. In concert with the MERA software stack, DNA II optimally sequences computation tasks and resource distribution, further refining efficiency and effectiveness in processing neural networks. This integration of hardware and software not only aids in reducing on-chip memory bandwidth usage but also enhances the parallel processing ability of the system, catering to the intricate needs of modern AI computing environments.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
The Tyr Superchip is engineered to tackle the most daunting computational challenges in edge AI, autonomous driving, and decentralized AIoT applications. It merges AI and DSP functionalities into a single, unified processing unit capable of real-time data management and processing. This all-encompassing chip solution handles vast amounts of sensor data necessary for complete autonomous driving and supports rapid AI computing at the edge. One of the key challenges it addresses is providing massive compute power combined with low-latency outputs, achieving what traditional architectures cannot in terms of energy efficiency and speed. Tyr chips are surrounded by robust safety protocols, being ISO26262 and ASIL-D ready, making them ideally suited for the critical standards required in automotive systems. Designed with high programmability, the Tyr Superchip accommodates the fast-evolving needs of AI algorithms and supports modern software-defined vehicles. Its low power consumption, under 50W for higher-end tasks, paired with a small silicon footprint, ensures it meets eco-friendly demands while staying cost-effective. VSORA’s Superchip is a testament to their innovative prowess, promising unmatched efficiency in processing real-time data streams. By providing both power and processing agility, it effectively supports the future of mobility and AI-driven automation, reinforcing VSORA’s position as a forward-thinking leader in semiconductor technology.
The Ultra-Low-Power 64-Bit RISC-V Core by Micro Magic, Inc. is engineered to operate efficiently with minimal power consumption, making it a standout solution for high-performance applications. This processor core is capable of running at an impressive 5GHz, yet it only consumes 10mW at 1GHz, illustrating its capability to deliver exceptional performance while keeping power usage to a minimum. Ideal for scenarios where energy efficiency is crucial, it leverages advanced design techniques to reduce voltage alongside high-speed processing. Maximizing power efficiency without compromising speed, this RISC-V core is suited for a wide array of applications ranging from IoT devices to complex computing systems. Its design allows it to maintain performance even at lower power inputs, a critical feature in sectors that prioritize energy savings and sustainability. The core's architecture supports full configurability, catering to diverse design needs across different technological fields. In addition to its energy-efficient design, the core offers robust computational capabilities, making it a competitive choice for companies looking to implement high-speed, low-power processing solutions in their product lines. The flexibility and power of this core accentuate Micro Magic's commitment to delivering top-tier semiconductor solutions that meet the evolving demands of modern technology.
GSHARK is a high-performance GPU IP designed to accelerate graphics on embedded devices. Known for its extreme power efficiency and seamless integration, this GPU IP significantly reduces CPU load, making it ideal for use in devices like digital cameras and automotive systems. Its remarkable track record of over one hundred million shipments underscores its reliability and performance. Engineered with TAKUMI's proprietary architecture, GSHARK integrates advanced rendering capabilities. This architecture supports real-time, on-the-fly graphics processing similar to that found in PCs, smartphones, and gaming consoles, ensuring a rich user experience and efficient graphics applications. This IP excels in environments where power consumption and performance balance are crucial. GSHARK is at the forefront of embedded graphics solutions, providing significant improvements in processing speed while maintaining low energy usage. Its architecture easily handles demanding graphics rendering tasks, adding considerable value to any embedded system it is integrated into.
aiWare stands out as a premier hardware IP for high-performance neural processing, tailored for complex automotive AI applications. By offering exceptional efficiency and scalability, aiWare empowers automotive systems to harness the full power of neural networks across a wide variety of functions, from Advanced Driver Assistance Systems (ADAS) to fully autonomous driving platforms. It boasts an innovative architecture optimized for both performance and energy efficiency, making it capable of handling the rigorous demands of next-generation AI workloads. The aiWare hardware features an NPU designed to achieve up to 256 Effective Tera Operations Per Second (TOPS), delivering high performance at significantly lower power. This is made possible through a thoughtfully engineered dataflow and memory architecture that minimizes the need for external memory bandwidth, thus enhancing processing speed and reducing energy consumption. The design ensures that aiWare can operate efficiently across a broad range of conditions, maintaining its edge in both small and large-scale applications. A key advantage of aiWare is its compatibility with aiMotive's aiDrive software, facilitating seamless integration and optimizing neural network configurations for automotive production environments. aiWare's development emphasizes strong support for AI algorithms, ensuring robust performance in diverse applications, from edge processing in sensor nodes to high central computational capacity. This makes aiWare a critical component in deploying advanced, scalable automotive AI solutions, designed specifically to meet the safety and performance standards required in modern vehicles.
ZIA Stereo Vision by Digital Media Professionals Inc. revolutionizes three-dimensional image processing by delivering exceptional accuracy and performance. This stereo vision technology is particularly designed for use in autonomous systems and advanced robotics, where precise spatial understanding is crucial. It incorporates deep learning algorithms to provide robust 3D mapping and object recognition capabilities. The IP facilitates extensive depth perception and analyzed spatial data for applications in areas like automated surveillance and navigation. Its ability to create detailed 3D maps of environments assists machines in interpreting and interacting with their surroundings effectively. By applying sophisticated AI algorithms, it enhances the ability of devices to make intelligent decisions based on rich visual data inputs. Integration into existing systems is simplified due to its compatibility with a variety of platforms and configurations. By enabling seamless deployment in sectors demanding high reliability and accuracy, ZIA Stereo Vision stands as a core component in the ongoing evolution towards more autonomous and smart digital environments.
Dillon Engineering's 2D FFT Core is specifically developed for applications involving two-dimensional data processing, perfect for implementations in image processing and radar signal analysis. This FFT Core operates by processing data in a layered approach, enabling it to concurrently handle two-dimensional data arrays. It effectively leverages internal and external memory, maximizing throughput while minimizing the impact on bandwidth, which is crucial in handling large-scale data sets common in imaging technologies. Its ability to process data in two dimensions simultaneously offers a substantial advantage in applications that require comprehensive analysis of mass data points, including medical imaging and geospatial data processing. With a focus on flexibility, the 2D FFT Core, designed using the ParaCore Architect, offers configurable data processing abilities that can be tailored to unique project specifications. This ensures that the core can be adapted to meet a range of application needs while maintaining high-performance standards that Dillon Engineering is renowned for.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The SAKURA-II AI accelerator is designed specifically to address the challenges of energy efficiency and processing demands in edge AI applications. This powerhouse delivers top-tier performance while maintaining a compact and low-power silicon architecture. The key advantage of SAKURA-II is its capability to handle vision and Generative AI applications with unmatched efficiency, thanks to the integration of the Dynamic Neural Accelerator (DNA) core. This core exhibits run-time reconfigurability that supports multiple neural network models simultaneously, adapting in real-time without compromising on speed or accuracy. Focusing on the demanding needs of modern AI applications, the SAKURA-II easily manages models with billions of parameters, such as Llama 2 and Stable Diffusion, all within a mere power envelope of 8W. It supports a large memory bandwidth and DRAM capacity, ensuring smooth handling of complex workloads. Furthermore, its multiple form factors, including modules and cards, allow for versatile system integration and rapid development, significantly shortening the time-to-market for AI solutions. EdgeCortix has engineered the SAKURA-II to offer superior DRAM bandwidth, allowing for up to 4x the DRAM bandwidth of other accelerators, crucial for low-latency operations and nimbly executing large-scale AI workflows such as Language and Vision Models. Its architecture promises higher AI compute utilization than traditional solutions, thus delivering significant energy efficiency advantages.
SiFive Essential family offers a highly customizable set of processor IPs suitable for a range of applications, from embedded microcontrollers to full-fledged Linux-capable designs. This family presents the flexibility to tailor power, area, and performance metrics according to specific market needs, ensuring that designers can optimize their solutions for diverse applications. The Essential lineup is structured to allow easy adaptability, featuring scalable microarchitectures that cater to every stage of product development. From lightweight, power-efficient processors optimized for IoT devices to more robust configurations designed for real-time control and processing, SiFive Essential processors cover a broad spectrum of use cases. Key features include advanced trace and debug capabilities and an open, scalable platform enhancing the overall security of SoC designs. With its comprehensive customization options, the Essential family is perfect for designers who need to strike a balance between performance and power efficiency. This versatility positions the SiFive Essential series as a cornerstone in providing quality RISC-V solutions, allowing for innovation without compromise on customizability and scalability.
Wormhole is a versatile communication system designed to enhance data flow within complex computational architectures. By employing state-of-the-art connectivity solutions, it enables efficient data exchange, critical for high-speed processing and low-latency communication. This technology is essential for maintaining optimal performance in environments demanding seamless data integration. Wormhole's ability to manage significant data loads with minimal latency makes it particularly suitable for applications requiring real-time data processing and transfer. Its integration into existing systems can enhance overall efficiency, fostering a more responsive computational environment. This makes it an invaluable asset for sectors undergoing digital transformation. The adaptability of Wormhole to various technological requirements ensures it remains relevant across diverse industry applications. This flexibility means that it can scale with ongoing technological advancements, cementing its role as a cornerstone in the evolving landscape of high-speed data communications.
The Codasip RISC-V BK Core Series is engineered to deliver flexibility and adaptability for a variety of embedded applications. These cores are designed to be low-power, offering an excellent balance of performance and energy efficiency. The series provides a spectrum of configurations, allowing developers to customize them to align with unique project requirements, ensuring each processor operates at peak efficiency for its specific use case. The cores are RISC-V compliant and adhere to stringent industry standards for quality, making them a reliable choice for sensitive applications.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The Universal Chiplet Interconnect Express (UCIe) by Extoll is a cutting-edge technology designed to meet the increasing demand for seamless integration of chiplets within a system. UCIe offers a highly efficient interconnect framework that underpins the foundational architecture of heterogeneous systems, enabling enhanced interoperability and performance across various chip components. UCIe distinguishes itself by offering an ultra-low power profile, making it a preferred option for power-sensitive applications. Its design focuses on facilitating high bandwidth data transfer, essential for modern computing environments that require the handling of vast amounts of data with speed and precision. Furthermore, UCIe supports a diverse range of process nodes, ensuring it integrates well with existing and emerging technologies. This innovation plays a pivotal role in accelerating the transition to advanced chiplet-based architectures, enabling developers to create systems that are both scalable and efficient. By providing a robust interconnect solution, UCIe helps reduce overall system complexity, lowers development costs, and improves design flexibility — making it an indispensable tool for forward-thinking semiconductor designs.
The Azurite Core-hub by InCore Semiconductors is a sophisticated solution designed to offer scalable RISC-V SoCs with high-speed secure interconnect capabilities. This processor is tailored for performance-demanding applications, ensuring that systems maintain robust security while executing tasks at high speeds. Azurite leverages advanced interconnect technologies to enhance the communication between components within a SoC, making it ideal for industries that require rapid data transfer and high processing capabilities. The core is engineered to be scalable, supporting a wide range of applications from edge AI to functional safety systems, adapting seamlessly to various industry needs. Engineered with a focus on security, the Azurite Core-hub incorporates features that protect data integrity and system operation in a dynamic technological landscape. This makes it a reliable choice for companies seeking to integrate advanced RISC-V architectures into their security-focused applications, offering not just innovation but also peace of mind with its secure design.
The eSi-ADAS IP suite is tailored to enhance radar processing for Advanced Driver Assistance Systems (ADAS). It includes a powerful radar co-processor engine that boosts the performance of radar systems used in automotive, drone, and UAV applications. The IP has gained adoption by prominent automotive suppliers and finds use in production vehicles, illustrating its reliability and effectiveness in real-world conditions. Key functionalities of eSi-ADAS encapsulate a wide range of radar hardware accelerators which enhance radar's performance capabilities, ensuring precise situational awareness.
The SiFive Performance family is tailored for maximum throughput in datacenter workloads, serving environments from web servers to networking and storage. This collection of processors boasts 64-bit, Out of Order (OoO) cores optimized for energy-efficient, high-performance computation. Designed to handle AI workloads with specific vector engines, the Performance processors offer a scalable core architecture, ranging from three-wide to six-wide out-of-order configurations. The P870-D processor, a standout in the Performance series, is engineered for datacenters and AI, supporting scalable compute density across multiple cores. Among other products, the Performance family includes the P650, P550, and P450, each offering varying multi-core and pipeline structures to cater to different workload needs. The blend of top-tier performance, compact footprint, and cost efficiency makes these processors an optimal choice for modern high-performance applications and environments. SiFive's Performance series is built to not only meet but surpass the demands of various markets, including mobile, consumer, datacenter, and industrial automation. It represents SiFive's commitment to advancing the scope of RISC-V technology, pushing boundaries in high-performance processing through careful design and innovation.
The Nerve IIoT Platform by TTTech Industrial is engineered to bridge the gap between real-time data and IT functionalities in industrial environments. This platform allows machine builders and operators to effectively manage edge computing needs with a cloud-managed approach, ensuring safe and flexible deployment of applications and data handling. At its core, Nerve is designed to deliver real-time data processing capabilities that enhance operational efficiency. This platform is distinguished by its integration with off-the-shelf hardware, providing scalability from gateways to industrial PCs. Its architecture supports virtual machines and network protocols such as CODESYS and Docker, thereby enabling a diverse range of functionalities. Nerve’s modular system allows users to license features as needed, optimizing both edge and cloud operations. Additionally, Nerve delivers substantial business benefits by increasing machine performance and generating new digital revenue streams. It supports remote management and updates, reducing service costs and downtime, while improving cybersecurity through standards compliant measures. Enterprises can use Nerve to connect multiple machines globally, facilitating seamless integration into existing infrastructures and expanding digital capabilities. Overall, Nerve positions itself as a formidable IIoT solution that combines technical sophistication with practical business applications, merging the physical and digital worlds for smarter industry operations.
The Software-Defined High PHY from AccelerComm is designed for adaptability and high efficiency across ARM processor architectures. This product brings flexibility in software-defined radio applications by facilitating easy optimization for different platforms, considering power and capacity requirements. It allows integration without hardware acceleration based on the needs of specific deployments.\n\nA key feature of the Software-Defined High PHY is its capability for customization. Users can tailor this IP to work optimally across various platforms, either independently or coupled with hardware-accelerated functionalities. This ensures the high-performance needed for modern network demands is met without unnecessary resource consumption.\n\nPerfect for scenarios needing O-RAN compliance, this PHY solution supports high adaptability and scalability for different use cases. It is ideal for developers who require robust communication solutions tuned for efficient execution in varying environmental conditions, contributing to lower latency and higher throughput in network infrastructures.
The ZIA DV700 Series is a high-performance AI processor designed by Digital Media Professionals Inc., providing extensive capabilities for deep learning inference on the edge. It is optimized for executing sophisticated neural network models efficiently, accommodating a wide range of AI applications. By incorporating advanced floating-point precision processing, the DV700 series enhances accuracy in areas where computational precision is pivotal. This processor series is particularly tailored for deployment in systems requiring reliable real-time decision-making capabilities, such as robotics and autonomous vehicles. It supports a variety of neural network frameworks, allowing for seamless integration with existing AI models and architectures, thus expanding its deployment flexibility in adaptive technology environments. The series also includes an adaptable software development kit to facilitate easy implementation and iterative testing of AI models. By supporting prevalent AI frameworks like TensorFlow and Caffe, it empowers developers to optimize their models for maximum performance and efficiency. The ZIA DV700 Series stands out as a competitive edge solution in high-stakes technological applications, ensuring superior operational standards in demanding projects.
The Ncore Cache Coherent Interconnect by Arteris addresses the multifaceted challenges of multi-core ASIC design, offering a production-ready, highly configurable coherent NoC interconnect solution. Ncore is tailored for high-performance applications, supporting a variety of protocols compatible with Arm and RISC-V processors while enhancing inter-core communication and synchronization. Ncore is designed with functional safety in mind, making it suitable for ISO 26262 certification, a crucial factor for safety-critical applications such as automotive systems. It ensures credible operation in these environments with built-in safety and reliability features, including FMEDA data and ASIL certification. The IP supports multi-protocol coherency with CHI-B, CHI-E, and ACE alongside I/O coherent agent interfaces, providing versatility and backward compatibility for diverse SoC architectures. Enhanced with unique proxy caches, Ncore lowers power requirements while maintaining high performance, offering a scalable, power-efficient interconnect fabric suitable for a wide array of system scales, from small embedded solutions to extensive multi-billion transistor designs.
PACE, or Photonic Arithmetic Computing Engine, represents a significant leap forward in computing by using optical components to perform mathematical operations. This breakthrough allows for speed and efficiency improvements that are hard to replicate with traditional electronic designs. The PACE engine is engineered to accelerate the execution of complex algorithms, essential for high-performance applications such as artificial intelligence and large-scale data processing. With its ability to process computations at the speed of light, it opens new avenues for ultra-fast data analysis, making it a pivotal tool for industries relying on rapid data processing and intelligence. Emphasizing low energy consumption, PACE leverages the inherent energy efficiency of photonic processes, minimizing the power requirements compared to electronic counterparts. This feature is crucial for sustainability, reducing the overall energy footprint of data centers and large computing facilities. The engine's design is not only focused on speed but also on operational stability, ensuring consistent performance under intensive computational loads. Integration with existing systems is seamless, as PACE is compatible with current technological infrastructures. This compatibility ensures that businesses can adopt this advanced technology with minimal disruption, enhancing their computational capabilities without the need for extensive overhauls. The photonic nature of the PACE engine ensures future scalability, aligning with the evolving demands of data-driven industries.
FlexWay Interconnect from Arteris provides a streamlined network-on-chip solution, ideally suited for low-power IoT edge devices and microcontrollers. This NoC IP is renowned for its efficiency and cost-effectiveness, making it an ideal candidate for embedded applications where power conservation is crucial. These interconnect mechanisms are constructed from rudimentary components, guided by robust algorithms and an intuitive graphical interface to facilitate the development of optimally configured topologies. FlexWay is adept at managing smaller scale systems, delivering smooth scalability from simple to medium complexity designs without unnecessary bloat. It maintains performance integrity across varied workloads, ensuring expedited on-chip data flow. Despite its power-efficient architecture, FlexWay handles bandwidth demands proficiently, supporting robust data transportation for embedded systems. Key capabilities include multi-clock, power, and voltage domain management, and comprehensive support for AMBA protocols to maintain a versatile environment, addressing diverse industrial standards. With SystemC simulation and UVM verification, FlexWay Interconnect ensures coherent design flows, reducing potential integration issues within the overall system architecture.
Monolithic Microsystems represents a technological leap in integrated system design, featuring multiple micro-engineered elements within a single chip. This system leverages advanced CMOS technology to unify electronic, photonic, and micromechanical devices, creating a compact and efficient platform suited for a variety of applications. By integrating different functionalities within a single substrate, these Microsystems can enhance performance while reducing the overall system footprint. They are increasingly being used in fields such as telecommunications, medical devices, and consumer electronics, where precision, reliability, and miniaturization are of paramount importance.
The RV32EC_P2 Processor Core is a compact, high-efficiency RISC-V processor designed for low-power, small-scale embedded applications. Featuring a 2-stage pipeline architecture, it efficiently executes trusted firmware. It supports the RISC-V RV32E base instruction set, complemented by compression and optional integer multiplication instructions, greatly optimizing code size and runtime efficiency. This processor accommodates both ASIC and FPGA workflows, offering tightly-coupled memory interfaces for robust design flexibility. With a simple machine-mode architecture, the RV32EC_P2 ensures swift data access. It boasts extended compatibility with AHB-Lite and APB interfaces, allowing seamless interaction with memory and I/O peripherals. Designed for enhanced power management, it features an interrupt system and clock-gating abilities, effectively minimizing idle power consumption. Developers can benefit from its comprehensive toolchain support, ensuring smooth firmware and virtual prototype development through platforms such as the ASTC VLAB. Further distinguished by its vectored interrupt system and support for application-specific instruction sets, the RV32EC_P2 is adaptable to various embedded applications. Enhancements include wait-for-interrupt commands for reduced power usage during inactivity and multiple timer interfaces. This versatility, along with integrated GNU and Eclipse tools, makes the RV32EC_P2 a prime choice for efficient, low-power technology integrations.
The Cobra platform, based on the Xilinx Kintex-7 architecture, serves as a versatile development environment for testing and iterative designs of various IPs. This platform is tailored to optimize the prototyping and development processes by providing a high-performance FPGA foundation. The Kintex-7 series is known for its balance of high performance and logic capacity, making it suitable for a range of applications where precision and efficiency are crucial. Cobra facilitates seamless integration and testing of DisplayPort solutions, offering developers a convenient platform to validate designs prior to ASIC production. It supports comprehensive data management, encryption-verification processes, and multimedia operations all in one framework, reducing the design cycle and overall project costs. The platform is also equipped with advanced features for real-time signal processing and enhanced data throughput, catering to industries from automotive to broadcast technology. The Cobra platform, thus, accelerates the development timeline while continuing to maintain high fidelity and robust functionality necessary in modern electronic design workflows.
The iCan PicoPop® System on Module (SOM) by Oxytronic is an ultra-compact computing solution designed for high-performance and space-constrained environments within the aerospace industry. Utilizing the Xilinx Zynq UltraScale+ MPSoC, this module delivers significant processing power ideal for complex signal processing and other demanding tasks. This module's design caters to embedded system applications, offering robust capabilities in avionics where size, weight, and power efficiency are critical considerations. It provides core functionalities that support advanced video processing, making it a pivotal component for those requiring cutting-edge technological support in minimal form factors. Oxytronic ensures that the iCan PicoPop® maintains compatibility with a wide range of peripherals, facilitating easy integration into existing systems. Its architectural innovation signifies Oxytronic's understanding of aviation challenges, providing solutions that are both technically superior and practically beneficial for modern aerospace applications.
The CurrentRF CC-100 Power Optimizer is central to the company's innovative energy harvesting technology, utilized in devices like the PowerStic and Exodus. This optimizer is engineered to be a fundamental component in intercepting digital noise currents and recycling them back into the system, effectively reducing operational power. It supports the enhancement of system battery life by up to 40%, serving as a critical device in power-conscious design strategies for integrated circuits and electric vehicles. The CC-100 ensures power savings when systems remain active, making it a vital tool for extending battery life in IC and systems design.
The ONNC Calibrator is engineered to ensure high precision in AI System-on-Chips using post-training quantization (PTQ) techniques. This tool enables architecture-aware quantization, which helps maintain 99.99% precision even with fixed-point architecture, such as INT8. Designed for diverse heterogeneous multicore setups, it supports multiple engines within a single chip architecture and employs rich entropy calculation techniques. A major advantage of the ONNC Calibrator is its efficiency; it significantly reduces the time required for quantization, taking only seconds to process standard computer vision models. Unlike re-training methods, PTQ is non-intrusive, maintains network topology, and adapts based on input distribution to provide quick and precise quantization suitable for modern neural network frameworks such as ONNX and TensorFlow. Furthermore, the Calibrator's internal precision simulator uses hardware control registers to maintain precision, demonstrating less than 1% precision drop in most computer vision models. It adapts flexibly to various hardware through its architecture-aware algorithms, making it a powerful tool for maintaining the high performance of AI systems.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
Tensix Neo is a high-performance processor designed to accelerate AI tasks with remarkable efficiency. By optimizing for performance per watt, it caters to AI developers needing robust technology for power-intense projects. Its architectural design supports a wide range of precision formats, ensuring that varying AI workloads are managed effectively. Central to its design is a specialized Network-on-Chip (NoC) that facilitates highly efficient data transfer and communication, enabling scalable AI solutions. This NoC allows the processor to evolve alongside an ever-changing landscape of AI models and applications, making it an asset for developers focused on scalability. Tensix Neo is particularly suited for environments where adaptability and performance are crucial, such as large-scale data processing centers and real-time computational tasks. It provides the technological backbone needed for developing next-gen AI systems that require flexible and powerful processing capabilities.
The Trifecta-GPU is a sophisticated family of COTS PXIe/CPCIe GPU Modules by RADX Technologies, designed for substantial computational acceleration and ease of use in PXIe/CPCIe platforms. Powered by the NVIDIA RTX A2000 Embedded GPU, it boasts up to 8.3 FP32 TFLOPS performance, becoming a preferred choice for modular Test & Measurement (T&M) and Electronic Warfare (EW) systems. It integrates seamlessly into systems, supporting MATLAB, Python, and C/C++ programming, making it versatile for signal processing, machine learning, and deep learning inference applications. A highlight of the Trifecta-GPU is its remarkable computing prowess coupled with its design that fits within power and thermal constraints of legacy and modern chassis. It is available in both single and dual-slot variants, with the capability to dissipate power effectively, allowing users to conduct fast signal analysis and execute machine learning algorithms directly where data is acquired within the system. With its peak performance setting new standards for cost-effective compute acceleration, the Trifecta-GPU also supports advanced computing frameworks, ensuring compatibility with a myriad of applications and enhancing signal classification and geolocation tasks. Its hardware capabilities are complemented by extensive software interoperability, supporting both Windows and Linux environments, further cementing its position as a top-tier solution for demanding applications.
VisualSim Architect serves as a comprehensive platform for modeling and simulating complex systems, offering engineers a robust framework to analyze system performance, power, and functionality. The platform boasts a vast library of basic modeling constructs and supports multi-core execution, providing flexibility to integrate with external tools and languages. This integration helps in assembling graphical models using pre-defined, parameterized Technology IP blocks. These blocks are instrumental in simulating various use cases, optimizing architecture specifications, and generating detailed performance reports. One of the significant advantages of VisualSim Architect is its ability to forecast potential risks in system development, both from technical and business perspectives. It assists engineers in identifying and mitigating risks that could lead to product failures or underperformance. By facilitating early-stage design optimizations, VisualSim Architect effectively shortens the time-to-market for new products. The platform is also designed to be operating system-agnostic, running seamlessly on Windows, Linux, and Mac OS/X platforms, which ensures broad accessibility for diverse user bases. Moreover, VisualSim Architect supports a collaborative development environment, allowing system models to be shared and viewed within a web browser. This capability fosters internal and external collaboration, making it easier for teams to discuss and refine ongoing projects. The system’s batch mode further enables large-scale system analysis through offline scripting and results storage, ensuring scalability and efficiency in modeling tasks.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
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