All IPs > Multimedia > WMV
The WMV (Windows Media Video) category within the realm of multimedia semiconductor IPs is dedicated to components and solutions that support the encoding, decoding, and processing of WMV video formats. WMV is a widely used video codec developed by Microsoft, designed to offer high quality video streaming and playback. This category is crucial for industries looking to integrate Windows-compatible video functionality into their products, including consumer electronics, PCs, and media servers.
WMV semiconductor IPs are essential for facilitating seamless video streaming services and applications. They are tailored to optimize the efficiency of video playback, ensuring reduced latency and enhanced video quality in both online and offline settings. These IPs support various levels of video resolution, making them suitable for different types of digital content, from standard to high definition. The integration of WMV IPs allows manufacturers to expand the video capabilities of their devices, ensuring compatibility with a broad spectrum of media content and providing users with a reliable, high-quality viewing experience.
Incorporating WMV multimedia semiconductor IPs can significantly enhance the capabilities of digital devices, providing support for dynamic video applications. Devices such as smart TVs, video game consoles, set-top boxes, and mobile phones can benefit from these IPs, enabling them to exploit advanced video codecs to deliver a superior media experience. These IPs ensure that products remain competitive in a rapidly evolving digital market by allowing for smooth integration of video technologies that meet consumer demands for quality and performance.
Developers and designers in the multimedia field will find a range of products within this category, including video encoder and decoder IPs that are highly configurable, enabling custom solutions tailored to specific needs and performance benchmarks. Whether designing for consumer electronics, professional multimedia equipment, or enterprise-level digital broadcasting tools, WMV multimedia semiconductor IPs offer indispensable functionality to meet the diverse demands of the multimedia industry.
Addressing the need for high-performance AI processing, the Metis AIPU PCIe AI Accelerator Card from Axelera AI offers an outstanding blend of speed, efficiency, and power. Designed to boost AI workloads significantly, this PCIe card leverages the prowess of the Metis AI Processing Unit (AIPU) to deliver unparalleled AI inference capabilities for enterprise and industrial applications. The card excels in handling complex AI models and large-scale data processing tasks, significantly enhancing the efficiency of computational tasks within various edge settings. The Metis AIPU embedded within the PCIe card delivers high TOPs (Tera Operations Per Second), allowing it to execute multiple AI tasks concurrently with remarkable speed and precision. This makes it exceptionally suitable for applications such as video analytics, autonomous driving simulations, and real-time data processing in industrial environments. The card's robust architecture reduces the load on general-purpose processors by offloading AI tasks, resulting in optimized system performance and lower energy consumption. With easy integration capabilities supported by the state-of-the-art Voyager SDK, the Metis AIPU PCIe AI Accelerator Card ensures seamless deployment of AI models across various platforms. The SDK facilitates efficient model optimization and tuning, supporting a wide range of neural network models and enhancing overall system capabilities. Enterprises leveraging this card can see significant improvements in their AI processing efficiency, leading to faster, smarter, and more efficient operations across different sectors.
The Metis AIPU M.2 Accelerator Module by Axelera AI is a compact and powerful solution designed for AI inference at the edge. This module delivers remarkable performance, comparable to that of a PCIe card, all while fitting into the streamlined M.2 form factor. Ideal for demanding AI applications that require substantial computational power, the module enhances processing efficiency while minimizing power usage. With its robust infrastructure, it is geared toward integrating into applications that demand high throughput and low latency, making it a perfect fit for intelligent vision applications and real-time analytics. The AIPU, or Artificial Intelligence Processing Unit, at the core of this module provides industry-leading performance by offloading AI workloads from traditional CPU or GPU setups, allowing for dedicated AI computation that is faster and more energy-efficient. This not only boosts the capabilities of the host systems but also drastically reduces the overall energy consumption. The module supports a wide range of AI applications, from facial recognition and security systems to advanced industrial automation processes. By utilizing Axelera AI’s innovative software solutions, such as the Voyager SDK, the Metis AIPU M.2 Accelerator Module enables seamless integration and full utilization of AI models and applications. The SDK offers enhancements like compatibility with various industry tools and frameworks, thus ensuring a smooth deployment process and quick time-to-market for advanced AI systems. This product represents Axelera AI’s commitment to revolutionizing edge computing with streamlined, effective AI acceleration solutions.
The Ncore Cache Coherent Interconnect is designed to tackle the complexities inherent in multicore SoC environments. By maintaining coherence across heterogeneous cores, it enables efficient data sharing and optimizes cache use. This in turn enhances the throughput of the system, ensuring reliable performance with reduced latency. The architecture supports a wide range of cores, making it a versatile option for many applications in high-performance computing. With Ncore, designers can address the challenges of maintaining data consistency across different processor cores without incurring significant power or performance penalties. The interconnect's capability to handle multicore scenarios means it is perfectly suited for advanced computing solutions where data integrity and speed are paramount. Additionally, its configuration options allow customization to meet specific project needs, maintaining flexibility in design applications. Its efficiency in multi-threading environments, coupled with robust data handling, marks it as a crucial component in designing state-of-the-art SoCs. By supporting high data throughput, Ncore keeps pace with the demands of modern processing needs, ensuring seamless integration and operation across a variety of sectors.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
The ASRC-Pro offers advanced functionalities as a 24-bit multi-channel audio sample rate converter, designed to handle diverse and demanding audio processing tasks effectively. With an exceptionally low total harmonic distortion and noise (THD+N) of -130dB, this converter is engineered for high-performance audio applications where precision and clarity are paramount. This converter allows asynchronous conversion between differing sample rates, using dual, unrelated clock signals to maintain precise timing and performance. The ASRC-Pro is essential for environments where multiple devices operate at different sampling rates, offering quick and accurate synchronization without compromising audio quality. Its output signal frequencies can be set over a spectrum from 64x to 1024xFSout, maintaining sonic accuracy and stability. Compatibility with various standard interfaces, such as SPDIF-AES3, I2S, and TDM, enhances the adaptability of this converter in different audio setups. This flexibility ensures seamless integration into complex audio processing chains, supporting a range of professional audio applications where high fidelity is critical.
The ASRC-Lite is a multi-channel audio sample rate converter designed for efficient handling of 16-bit audio with a THD+N of -90dB. It is particularly useful for interfacing digital audio equipment that operates at varying sample rates, facilitating seamless audio synchronization across devices. The converter supports configurations with multiple audio channels, perfect for applications requiring precise audio data handling and conversion. This audio sample rate converter operates asynchronously, requiring distinct clock signals for the input and output, ensuring flexibility in audio processing tasks. With predefined options for output clock signal frequencies ranging from 64x to 1024x of FSout, it allows for high adaptability in various audio processing scenarios. Pertinent to its performance, the ASRC-Lite epitomizes efficiency, maintaining optimal power use and performance levels for superior audio fidelity. Moreover, the device supports numerous standard audio interfaces, including Parallel TDM, I2S, and SPDIF-AES3, providing broad applicability across different audio processing setups. It caters to the synchronization needs of systems working with disparate clock domains, guaranteeing stable and consistent performance in professional audio environments.
FlexNoC Interconnect stands as a cornerstone technology for developers aiming to enhance the performance and efficiency of their SoC designs. This flexible, high-performance interconnect supports a multitude of protocols, offering advanced Quality of Service (QoS) and debug features. FlexNoC's capability to accommodate diverse IP cores within a single system enables optimized communication paths, thereby reducing latency and improving data throughput across the chipset. FlexNoC is particularly adept at managing system complexities, thanks to its dynamic configuration abilities. By reducing interconnect wire lengths and facilitating easier integration, it streamlines the backend design process. This not only aids in achieving quicker timing closure but also enhances the overall SoC economics by minimizing manufacturing costs. The interconnect's strength is evidenced by its utilization in various high-demand sectors such as automotive, industrial, and consumer electronics, where the fast, reliable processing of information is crucial. Its ability to balance load and administer traffic control effectively extends its utility across a wide array of applications, ensuring it remains a vital tool for modern SoC development.
The Vega eFPGA is a flexible programmable solution crafted to enhance SoC designs with substantial ease and efficiency. This IP is designed to offer multiple advantages such as increased performance, reduced costs, secure IP handling, and ease of integration. The Vega eFPGA boasts a versatile architecture allowing for tailored configurations to suit varying application requirements. This IP includes configurable tiles like CLB (Configurable Logic Blocks), BRAM (Block RAM), and DSP (Digital Signal Processing) units. The CLB part includes eight 6-input Lookup Tables that provide dual outputs, and also an optional configuration with a fast adder having a carry chain. The BRAM supports 36Kb dual-port memory and offers flexibility for different configurations, while the DSP component is designed for complex arithmetic functions with its 18x20 multipliers and a wide 64-bit accumulator. Focused on allowing easy system design and acceleration, Vega eFPGA ensures seamless integration and verification into any SoC design. It is backed by a robust EDA toolset and features that allow significant customization, making it adaptable to any semiconductor fabrication process. This flexibility and technological robustness places the Vega eFPGA as a standout choice for developing innovative and complex programmable logic solutions.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
Recognized as a powerful tool in audio coding, the MPEG-H Audio System has transformed audio experiences for both television and virtual reality ecosystems. By supporting immersive and interactive soundscapes, it allows viewers to control elements like dialogue levels and creates a more personalized listening experience. The adoption of this system in international broadcasting standards is a testament to its robustness and innovation.
The SerDes PHY offered by Terminus Circuits is a crucial element for data communication, designed to manage the bandwidth and speed requirements of next-generation technologies. It serves as a comprehensive solution for SerDes design, providing industry-leading performance across various nodes and foundries. Equipped to support multiple protocols, this PHY ensures customers benefit from exceptional power savings and performance, meeting diverse technical needs. Key to its design is the seamless interoperability with existing controllers, allowing it to meet the demands of multiple market segments, including network communication, enterprise routers, servers, industrial test equipment, and more. The technology used in SerDes PHY ensures that customers can achieve their desired outcomes with reduced latency and increased power efficiency. This IP is available across multiple process nodes such as TSMC 28HPC, TSMC 28HPC+, and other significant nodes, confirming its adaptability and expanded utility in the market. Its offering is complemented with extensive deliverables, including integration guides, netlists, and verification reports—further enhancing its functionality and ease of integration.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The Ultra-Wideband (UWB) Impulse Radar Toolkit from EDI is a comprehensive package designed for applications in precise ranging and high-resolution imaging. Leveraging UWB technology, this toolkit enables detailed analysis of spatial environments, which is crucial for applications such as search and rescue operations, industrial automation, and structural monitoring. The radar toolkit supports precise measurements over short to medium ranges, making it ideal for a variety of settings, from complex industrial environments to challenging outdoor conditions. Its high-resolution data provides insights unattainable by conventional radar systems, allowing for detailed mapping and object detection. The toolkit is designed for ease of integration and can be tailored to specific applications, offering a flexible solution that can expand as project needs evolve. Whether for academic research or real-world application, this radar toolkit enhances the capability to comprehend and analyze spatial relationships and object dynamics efficiently and effectively.
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The FlexGen Smart Network-on-Chip (NoC) is a revolutionary approach to system connectivity within SoCs. Featuring AI-driven heuristics, FlexGen optimizes wire length, refines topology, and reduces latency to vastly improve performance. This intelligent NoC solution automates the network configuration process, ensuring seamless connectivity across diverse components within the system. FlexGen offers unmatched flexibility, accommodating varied requirements seamlessly, making it ideal for contemporary SoC designs that demand high efficiency and low latency. Its automation capabilities reduce development time significantly, saving resources and boosting productivity. Furthermore, FlexGen's adaptations to changes in design requirements or system components underscore its versatile application. In scenarios where speed and reliability are paramount, FlexGen smart NoC delivers. It assures that advanced technological demands are met without compromising on quality or performance, reinforcing its status as a leading choice for modern high-speed applications.
HES Proto-AXI is a software package that, when combined with HES prototyping boards, provides a robust environment for rapid design prototyping or algorithm accelerator development. It offers a seamless design and testing framework that supports the rapid integration of designs, ensuring quick time-to-market for new products.
ASRC-Lite-up is engineered for multi-channel audio applications, focusing on converting 16-bit audio sample rates with a THD+N of -90dB. This upscaling converter is built for upgrading audio stream sampling rates, ensuring smooth integration and enhanced audio fidelity in systems requiring such adjustments. Designed to deliver consistent output quality, it orchestrates asynchronous sample rate conversions using independent clock signals. This freedom from clock rate dependency allows it to adapt across various digital audio setups. Whether synchronizing audio equipment at different sampling rates or converging disparate streams, ASRC-Lite-up maintains performance integrity. The converter supports a variety of interfaces, offering flexibility in digital audio environments. Incorporating options like I2S, TDM, and SPDIF, ASRC-Lite-up integrates easily into audio systems without the need for external analog components, facilitating straightforward and reliable audio operations.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The ASRC-Premier is tailored for handling advanced audio processing needs, featuring 20-bit resolution with a THD+N of -120dB. It plays a key role in managing multi-channel audio sample rate conversion, ensuring precision and high-quality audio output across varied sound systems. By supporting asynchronous conversion between different sample rates, it decouples input from output clock domains, allowing highly accurate and independent timing. This results in seamless integration and reliability in complex audio signal paths. ASRC-Premier is ideal for environments requiring consistent and high-caliber audio processing capabilities. Compatible with several standard audio interfaces, such as SPDIF-AES3, I2S, and TDM, the ASRC-Premier ensures compatibility and flexibility in diverse audio operations. This adaptability guarantees smooth operation and simplifies the task of maintaining high audio quality across varied systems, making it suitable for use in professional audio setups.
The Akeana 5000 Series represents the pinnacle of RISC-V-based performance, tailored for ultra-high performance applications such as AI training, data centers, and advanced mobile computing environments. These processors feature out-of-order execution and extensive multi-threading support, enabling them to handle complex computational loads with ease and scalability. Equipped with advanced pipeline architectures and expanded cache levels, the 5000 Series can efficiently manage high data throughput and latency-sensitive applications. The series provides extensive expandability options through configurable cores and cache settings, allowing for precise calibration to meet specific demand characteristics. Moreover, integrating industry-leading clock frequency operations and support for rich operating systems like Android and Linux, the 5000 Series excels in environments where high-performance computation and robust scalability are prerequisites. Its capability to support virtualization and coherent processor clusters further underscores its suitability for next-generation, high-demand applications.
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