All IPs > Multimedia > MPEG / MPEG2
The MPEG and MPEG2 categories of semiconductor IPs are essential for managing digital video compression and playback in a variety of multimedia applications. These IPs are designed to facilitate efficient encoding, decoding, and transmission of video content, leveraging the capabilities of the well-established MPEG and MPEG2 standards. The technology serves as a backbone for many digital video products, enabling manufacturers to deliver high-quality video experiences in consumer electronics, broadcasting, and streaming services.
MPEG, which stands for Moving Picture Experts Group, encompasses a suite of standards for audio and video compression and transmission. MPEG semiconductor IPs support a wide range of functions, from basic video compression to more complex tasks like multiplexing video streams. MPEG2, an evolution of the original MPEG standard, further enhances video and audio quality and is particularly noted for its use in DVDs and digital television broadcasting. The IPs in this category are optimized for high-efficiency encoding processes, ensuring smoother playback and better bandwidth utilization.
These semiconductor IPs are crucial as they empower developers to create devices capable of handling intense video processing tasks with lower power requirements and greater speed. Companies in consumer electronics, such as TV manufacturers, set-top box designers, and digital video recorders, commonly utilize MPEG and MPEG2 IPs. Moreover, the broadcasting sector benefits significantly from their use in creating and managing content delving into formats suitable for various transmission channels.
In addition to consumer electronics and broadcasting, streaming services use MPEG and MPEG2 IPs to manage and deliver clear, sharp videos over the internet. By employing these semiconductor IPs, developers ensure compatibility with a broad range of devices and network conditions, providing flexible solutions that meet the dynamic needs of modern multimedia consumption. Whether the application demands real-time video processing or offline content delivery, MPEG and MPEG2 semiconductor IPs offer robust solutions that maintain the integrity and quality of visual content across multiple platforms.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
The JPEG Encoder is a highly efficient IP solution crafted for superior image compression, leveraging in-house developed technologies to provide high-quality image processing capabilities. This encoder supports up to 12 bits, offering two main variants that cater to different performance needs. The L1 variant focuses on monochrome or YUV420 multiplexed pipeline encoding with a pixel clock capacity of up to 150 MHz, whereas the L2 variant allows dual pipe encoding for high-quality YUV422 with pixel clock capabilities of up to 100 MHz. Ideal for machine vision applications, this encoder IP delivers reliable and streamlined video streaming functionalities, particularly across FPGA platforms. Its design ensures robust streaming performance, supporting formats like RFC2435 standard MJPEG for networking applications. A notable feature of this encoder is its compatibility with UDP/Ethernet streaming, making it perfectly suited for applications in surveillance and broadcasting, where real-time video data transmission is critical. Moreover, the JPEG Encoder is specifically engineered to minimize power consumption through its clock synchronous, distributed operation mechanism. By doing so, it addresses the stringent power requirements of modern embedded systems, ensuring efficient operation in a compact footprint. This product, available in both open-source and proprietary forms, underscores section5's commitment to delivering scalable, high-quality video processing IP.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The EZiD211 DVB-S2X is a sophisticated demodulator/modulator device tailored for satellite communication demands. Developed as part of EASii IC's SATCOM products, this device supports advanced satellite features such as Beam Hopping and Super Frame technologies. The compact design and high-performance capabilities make it suitable for integration into modem solutions across LEO, MEO, and GEO satellite communications, enhancing connectivity and data transmission effectiveness in diverse environments.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The High Performance FPGA PCIe Accelerator Card serves as a high-speed addition for enhancing computational capacity in server units, utilizing Intel Arria 10 FPGA technology. It features dual DDR3 memory banks and a PCIe 3.0 interface, making it perfect for tasks that require rapid data transfer. Designed for high-density server environments, it aids in offloading processing tasks, lowering power consumption while maintaining high performance. This card excels in applications that demand high throughput, such as real-time video processing and algorithm acceleration. In addition to video acceleration capabilities, it supports up to 4k UHD through bi-directional Quad 3G SDI interfaces. Available as a standalone solution or combined with other Korusys IPs, this card is versatile enough to replace or enhance GPU solutions, making it a comprehensive tool for various computational disciplines.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
The MPEG-H Audio System revolutionizes audio experience by offering immersive sound capabilities tailored for TV and virtual reality environments. This next-level audio system allows for an interactive and personalized listening experience, enabling users to adjust audio settings such as dialogue level, enabling a more tailored and enriched auditory experience. Supporting advanced audio features, it delivers a three-dimensional sound experience by utilizing object-based audio technologies. MPEG-H Audio is designed to adapt to various broadcasting standards worldwide, making it a versatile solution for broadcasters aiming to enhance their listener's engagement. It provides a seamless mixing of different audio objects, allowing the audio scene to be dynamically recreated according to user preference and environmental settings. Additionally, MPEG-H Audio has been adopted as a mandatory audio system for certain regions’ next-gen TV technology. This indicates its significant role in future-proofing broadcast environments and enhancing audio output quality. The MPEG-H Audio System stands out as a compelling solution for broadcasters, technology developers, and AV enthusiasts seeking to enhance audio quality and user experience across media platforms.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The JPEG 2000 CODEC by intoPIX is designed for high-performance encoding and decoding, catering to applications that demand superior image quality such as digital cinema, broadcasting, and medical imaging. This codec supports a wide array of resolutions and is optimized for both FPGA and ASIC platforms, offering flexibility for diverse deployable environments. JPEG 2000 excels with its ability to deliver visually and mathematically lossless compression, safeguarding image quality during intense processing. It is equipped to handle deep color depths and various color spaces, ensuring compatibility with modern cinema standards and broadcast protocols. The codec's architecture is highly scalable, making it suitable for applications requiring from HD to 8K resolution handling. Its unique ultra-low latency mode ensures rapid encoding and decoding, vital for real-time transmission requirements. The codec is compatible with numerous wavelet transform options, facilitating its adaptability to specific use cases where efficiency and quality convergence is essential. This robust solution supports progressive decoding, offering advantages in scenarios requiring real-time image manipulation and display.
The logiJPGD provides baseline-compliant JPEG decoding, capable of processing multiple high-definition video inputs concurrently. This IP core is tailored for video over IP applications, facilitating robust image decompression in real-time applications. It's particularly useful for systems needing to handle several HD streams, ensuring high efficiency and reliability.
The AL-H264E-4KI422-HW is an advanced H.264 UHD Hi422 Intra encoder optimized for low-latency and high-quality video applications. Targeted at fields requiring high precision like medical imaging and live broadcasting, this encoder supports the High-422 profile with 10-bit color depth, ensuring that visual details remain intact without color banding. Designed to work seamlessly with Atria Logic's AL-H264D-4KI422-HW decoder, it ensures an end-to-end low-latency transmission setup, which is crucial for real-time broadcasting and interactive applications such as robotic surgery assistance. The encoder's intuitive architecture achieves sub-frame latency, making it suitable for environments where time synchronization is critical. Implemented on a Xilinx Zynq-7000 series SoC, this encoder leverages FPGA resources efficiently, maintaining high video quality suitable for broadcasting over HDBaseT or through computer-connected displays. It not only supports variable and constant bit rate encoding but also integrates an Ethernet MAC for streamlined IP streaming. By offering comprehensive support for UHD encoding with high flexibility, the encoder fits diverse applications, including industrial machinery monitoring and dynamic broadcasting environments.
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The AL-MPEG2E-SW encoder offers software-based MPEG-2 Main Profile encoding primarily for applications demanding efficient power usage and strong compression capabilities. Its design adheres to ISO standards, ensuring compatibility and high quality in various industrial and medical contexts where image fidelity is paramount. Supporting Main Profile encoding with Low and Main Level definitions, this encoder excels in applications like portable recorders and medical video archiving. Its power-optimized algorithms make it ideal for deployment on devices ranging from low-power ARM processors to high-performance embedded systems, facilitating diverse usage scenarios. Equipped with features like robust rate distortion optimization and variable bitrate support, the AL-MPEG2E-SW stands as a reliable choice for applications needing scalable video quality control. Whether in a broadcast contribution setup or used for personal video recorders, this encoder delivers consistent performance aligned with stringent quality standards.
This IP core efficiently handles lossless motion JPEG decoding in line with Annex H of the ISO/IEC 10918-1 JPEG standard. It's well-suited for AMD MPSoC, SoC, and FPGA platforms, offering reliable decompression in both video and still image applications. The logiJPGD-LS IP core meets stringent requirements for precision and quality, making it optimal for applications demanding exact image reproduction.
Suitable for still image and video compression in line with the JPEG standard baseline, the logiJPGE encoder IP core offers robust performance for streaming and storage applications. It's particularly advantageous in scenarios requiring efficient encoding of multiple HD video channels, ensuring streamlined processing and integration into various multimedia systems.
Designed for lossless motion JPEG encoding, this IP core complies with Annex H of the ISO/IEC 10918-1 standard. It supports AMD MPSoC, SoC, and FPGA devices, providing seamless integration for video and still image compression tasks. The logiJPGE-LS ensures high-quality output suitable for demanding media processing applications requiring precise compression capabilities.
IPrium's STB modem solutions focus on providing optimally designed System-on-Chip (SoC) architectures tailored for the latest set-top box (STB) technologies. These solutions brag of high-quality video and audio transmission capabilities with support for various modulation schemes. They encompass features such as advanced error correction and encryption mechanisms, ensuring the delivery of high-bandwidth content with reduced latency. The SoC designs integrate multiple processing cores to support high-definition video and audio streams, maximizing bandwidth efficiency. They are built to handle various broadcast standards, providing universal applicability across multiple regions and compliance with international standards. The architectures emphasize low power consumption while maintaining superior processing speeds, making them an ideal choice for modern digital broadcasting infrastructure. Furthermore, the STB modem SoCs are engineered to support interactive functionalities, such as video-on-demand and IPTV services. By facilitating seamless integration with broadband networks, they ensure a smooth user experience. Their versatility and adaptability make them suitable for both current applications and future-proofing against upcoming technological trends.
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