All IPs > Multimedia > MPEG / MPEG2
The MPEG and MPEG2 categories of semiconductor IPs are essential for managing digital video compression and playback in a variety of multimedia applications. These IPs are designed to facilitate efficient encoding, decoding, and transmission of video content, leveraging the capabilities of the well-established MPEG and MPEG2 standards. The technology serves as a backbone for many digital video products, enabling manufacturers to deliver high-quality video experiences in consumer electronics, broadcasting, and streaming services.
MPEG, which stands for Moving Picture Experts Group, encompasses a suite of standards for audio and video compression and transmission. MPEG semiconductor IPs support a wide range of functions, from basic video compression to more complex tasks like multiplexing video streams. MPEG2, an evolution of the original MPEG standard, further enhances video and audio quality and is particularly noted for its use in DVDs and digital television broadcasting. The IPs in this category are optimized for high-efficiency encoding processes, ensuring smoother playback and better bandwidth utilization.
These semiconductor IPs are crucial as they empower developers to create devices capable of handling intense video processing tasks with lower power requirements and greater speed. Companies in consumer electronics, such as TV manufacturers, set-top box designers, and digital video recorders, commonly utilize MPEG and MPEG2 IPs. Moreover, the broadcasting sector benefits significantly from their use in creating and managing content delving into formats suitable for various transmission channels.
In addition to consumer electronics and broadcasting, streaming services use MPEG and MPEG2 IPs to manage and deliver clear, sharp videos over the internet. By employing these semiconductor IPs, developers ensure compatibility with a broad range of devices and network conditions, providing flexible solutions that meet the dynamic needs of modern multimedia consumption. Whether the application demands real-time video processing or offline content delivery, MPEG and MPEG2 semiconductor IPs offer robust solutions that maintain the integrity and quality of visual content across multiple platforms.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
This JPEG Encoder is a highly efficient IP core designed for image compression in machine vision applications. It supports pixel bit depths up to 12 bits, ensuring quality retention in diverse imaging scenarios. The encoder is particularly effective for use in standard FPGAs, offering cost-efficient solutions for high-speed data processing needs. Available in two main configurations, it can handle monochrome or YUV420 multiplexed pipeline at 150 MHz pixel clock, optimizing throughput in demanding environments. The dual pipe simultaneous encoding variant enhances video quality in YUV422 formats, ideal for resolutions such as 1280×720 at 60 frames per second. Additionally, the encoder provides an option for higher pixel clock operations tailored to specific platform requirements. Deployment over Ethernet with UDP capabilities ensures seamless data transmission, backed by robust gstreamer-based applications for both Linux and Windows platforms. To meet diverse application needs, the JPEG Encoder includes both lossy and lossless compression configurations. It is validated to perform optimally through extensive co-simulations and functional verifications, ensuring compliance with industry standards. This thorough validation process guarantees reliable performance in real-world applications, making it a preferred choice for professionals requiring high-quality imaging solutions.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Korusys's High-Performance FPGA PCIe Accelerator Card is designed to power complex computational tasks with its Intel Arria 10 FPGA architecture. This card provides extensive bandwidth through a PCIe 3.0 x8 host interface and supports bidirectional Quad 3G-SDI, making it ideal for applications needing high-throughput data processing. Equipped with dual DDR3 banks, it ensures large memory capacity crucial for intensive computation. Perfect for accelerating algorithms in video and image processing or scientific computing, this accelerator card accommodates increasing demands for processing power and data handling efficiency. Available independently or bundled with Korusys IP solutions, this card exemplifies leading-edge technology for varied high-performance needs.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The MPEG-H Audio System brings a new dimension to audio experiences in TVs and Virtual Reality (VR), offering users an immersive and interactive sound environment. Known for its advanced capabilities, this system allows for personalized audio adjustments which enable listeners to modify elements of the sound to their liking, such as changing the volume of dialogues or commentary. This customization ensures that the audio experience can be tailored to fit personal preferences, leading to enhanced viewer engagement and satisfaction. The MPEG-H Audio System is crucial for the next generation of broadcast services, being particularly adept at delivering high-quality, multi-dimensional sound over a range of devices. This readiness for future audio trends aligns perfectly with modern media consumption needs, where immersive experiences are increasingly demanded. In terms of functionality, the MPEG-H system supports not only traditional stereo and surround sound but also advanced setups through headphones, soundbars, and television speakers, accommodating varying listener environments. Another significant aspect of the MPEG-H Audio System is its integration into various international broadcast standards, underscoring its versatility and wide applicability. It brings unrivaled clarity and dynamics to television broadcasts and VR simulations, pushing the boundaries of sound technology and augmenting the audio-visual narrative of both everyday and cinematic content. Its implementation heralds a shift toward more engaging and personalized media consumption experiences.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
As an upgrade to its predecessor, the JH7110 platform integrates enhanced AI capabilities and processing power. Built to support a wider array of applications including cloud computing and industrial control, this platform is perfect for use in environments that require robust performance and security. It features a quad-core architecture and an enhanced GPU for superior graphics rendering. With improved memory bandwidth and a faster processor, the JH7110 delivers better performance metrics and a broader range of high-speed interfaces. This platform is designed for current and emerging markets, such as personal computing and NAS applications. StarFive ensures that the platform remains adaptable, giving developers a reliable foundation equipped for modern AI and multimedia processing.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The v-MP6000UDX Visual Processing Unit is a highly versatile processor featuring a unified processing architecture. This unit specializes in enabling real-time execution of the most intensive neural network tasks with exceptional power efficiency and a minimal silicon footprint. It supports a broad array of processing needs, effectively integrating deep learning, computer vision, image processing, and video compression on a single architecture. Designed to meet the rigorous demands of modern applications, the v-MP6000UDX offers unparalleled performance with its single software-programmable platform. Developers benefit from reduced development complexity, faster speed to market, and increased product lifespans. The processor can efficiently map and execute all layers of neural networks, easing the burden on software engineers and allowing seamless transitions across different machine learning frameworks. The versatility and high efficiency of the v-MP6000UDX make it an ideal choice for industries such as automotive, gaming, and mobile devices. Its ability to seamlessly integrate into system-on-chip designs further broadens its appeal, offering enhanced optimization opportunities for developers and significantly reducing integration overhead.
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
IPrium's STB Modem System-on-Chip Solutions are engineered to revolutionize the set-top box market by integrating advanced modem functionalities directly into the chipset. This innovation allows for greater efficiency and compact design, catering to the evolving demands of digital television and broadband services. The system-on-chip (SoC) architecture combines various modem features, supporting a wide range of communication standards. This integration reduces the need for additional components, streamlining manufacturing processes and reducing costs while enhancing performance. Perfect for modern broadcasting and telecommunications industries, these solutions offer enhanced processing capabilities and improved data throughput, ensuring seamless delivery of digital content. The flexibility of the STB modem solutions also promises future-proof adaptability for emerging technologies and services.
The MPEG-1/2 - Layer I/II Audio Decoder offers advanced real-time decoding capabilities designed for crucial audio applications where synchronization and quality are vital. This decoder is part of the CWda75 line-up and is engineered for both FPGA and ASIC environments. Handling multiple audio streams with ease, the decoder ensures high performance with a focus on energy efficiency. Its architecture employs low-latency designs to synchronize audio outputs effectively, which is critical in both professional studio settings and consumer media devices. Supporting multiple audio format configurations, this decoder is adaptable to various applications, powered by Coreworks' Multimedia Platform. It provides potential for future upgrades, ensuring longevity and compatibility with emerging technologies in audio processing.
Designed for seamless real-time audio decoding, the AAC-LC and HE-AAC Audio Decoder from Coreworks delivers high-fidelity sound output across multiple platforms. Standing in the CWda73 framework, it supports a variety of audio streams, making it suitable for professional and consumer audio applications. Implementing this decoder ensures optimal sound quality, facilitated by the support for both AAC-LC and HE-AAC formats. Its real-time decoding capabilities guarantee synchronized output, essential for applications where audio clarity and timing are critical, such as media playback and streaming. Bolstered by Coreworks’ Multimedia Platform, this decoder offers low energy consumption while maximizing audio output quality. Its ability to integrate diverse stream configurations underlines its utility in dynamic audio processing environments, ensuring an adaptable solution that meets current and future audio processing demands.
Coreworks provides an AAC-LC and HE-AAC Audio Encoder designed for real-time audio encoding across diverse platforms. Capable of handling multiple audio streams, this encoder is optimized for both FPGA and ASIC environments, ensuring flexibility and robust performance for audio applications keen on high-quality sound delivery. Residing in the CWda72 framework, this encoder accommodates a wide array of audio formats, supporting varied channel numbers suitable for different user needs. The inclusion of a latency controller guarantees synchronized audio output, crucial for professional audio-video production chains, enhancing the listening experience with reduced delays. Engineered for low power consumption, this IP ensures efficient energy use without sacrificing audio fidelity. Its adaptability makes it appropriate for single or multiple audio stream configurations, supported by a customizable Multimedia Platform backbone, ensuring optimal application-specific performance.
The v-MP4000UDX Visual Processing Unit is designed for high-performance visual computing tasks, leveraging a unified platform that integrates various computational functions. It excels in processing intensive applications such as computer vision, improving both performance and power efficiency significantly. This processor features an architecture that accommodates a wide range of tasks including video encoding and decoding, image processing, and drive assistance systems. Its design ensures developers can utilize the same tools across different types of software applications, facilitating seamless integration and development acceleration. Ideal for use in smart consumer electronics and automotive industries, the v-MP4000UDX supports efficient processing of high-resolution video, including advanced video coding standards. It significantly cuts down on system complexity and development costs, all while meeting the increasing demand for smarter, more capable embedded solutions.
This component features both LDPC and BCH decoding functionalities tailored for DVB-S2X applications. It enhances signal processing by improving error correction and data integrity, essential for satellite communication systems. With its robust design, it ensures the reliable transmission of high-quality broadcast signals.
For comprehensive decoding solutions, the MPEG-1/2 + AAC Audio Decoders are engineered to support a multitude of audio formats in real-time, ensuring flexibility and high performance. Encompassed in Coreworks' CWda99 platform, these decoders are tailored for high-efficiency environments, meeting the demands of both professional and entertainment audio systems. These decoders provide seamless handling of multi-stream configurations, ensuring synchronized and high-fidelity sound output across various devices. The fusion of MPEG-1/2 formats with AAC decoding extends their usability across different application needs where speed and quality are non-negotiable. Built on Coreworks' innovative Multimedia Platform, the decoders optimize power consumption while providing scalable solutions suitable for FPGA and ASIC environments. Their design accommodates future upgrades, maintaining relevance with evolving technology trends in audio processing.
This MPEG-1/2 - Layer I/II Audio Encoder is a sophisticated IP core dedicated to the real-time encoding of audio streams tailored for quality-centric applications. Integrated within the CWda74 framework, it supports various stream types, ideally structured for FPGA and ASIC platforms. This encoder handles multiple streams efficiently, offering a flexible encoding process that accommodates an array of channel configurations. Its low-frequency power architecture ensures minimal energy consumption while maintaining top-tier audio integrity, vital for both broadcasting and consumer electronics. Supporting a wide variety of audio formats, this encoder utilizes a proprietary customizable infrastructure to ensure superb audio delivery. The latency controller is a key feature, ensuring perfect synchronization for high-demand applications such as professional studio environments, which require precise audio synchronization with video inputs.
Built for DVB-S2X standards, this modulator ensures efficient signal modulation for satellite broadcast systems. Its advanced features incorporate a wide range of modulation schemes, cultivating superior signal integrity and lower power consumption. This modulator is fundamental for maintaining high-quality broadcast signals across various satellite communication platforms.
The logiJPGD-LS, a Motion JPEG (MJPEG) Lossless Decoder, adheres to Annex H of the ISO/IEC 10918-1 JPEG standard. It is optimized for still image and video decompression applications on AMD's MPSoC, SoC, and FPGA platforms, providing high-quality image output without data loss. This decoder is designed to maintain fidelity even in demanding environments, ensuring that decompressed images preserve their original quality. It supports a variety of video applications where maintaining image integrity is critical. With its focus on lossless decompression, the logiJPGD-LS serves applications that require precision and quality, making it essential for sectors like broadcasting, video archiving, and medical imaging, where data integrity is paramount.
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Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!