All IPs > Multimedia > MPEG 4
In the realm of multimedia, MPEG 4 semiconductor IPs play a pivotal role by providing essential technology for audio and video compression. These IPs facilitate the efficient storage and transmission of high-quality multimedia content, making them indispensable for a wide array of applications. Developed as a comprehensive digital multimedia encoding standard, MPEG 4 semiconductor IPs are foundational in enabling devices to handle complex media files such as video, audio, and 3D graphics, ensuring smooth playback and quality user experiences.
MPEG 4 technology has permeated various industries thanks to its flexibility and scalability. It supports interactive media applications, enhances web-based content, and empowers broadcasting services with its advanced compression techniques. Whether you're creating entertainment systems, digital TVs, or mobile applications, MPEG 4 semiconductor IPs offer robust solutions that address the increasing demand for efficient data processing and reduced bandwidth usage without compromising on quality.
The MPEG 4 semiconductor IP category encompasses a variety of products that cater to different encoding and decoding needs. These include codec solutions, which are essential for transforming raw data into a format suitable for playback and storage. Embedded systems utilize these IPs to seamlessly integrate multimedia capabilities, further broadening the scope of devices that can support rich, interactive content.
Harnessing MPEG 4 semiconductor IP not only aids in maintaining the integrity and performance of multimedia content but also optimizes it for modern digital ecosystems. As consumer trends continue to move towards rich, immersive experiences, the technology behind MPEG 4 is more relevant than ever, delivering competent solutions for present and future multimedia challenges across platforms.
The KL520 marks Kneron's foray into the edge AI landscape, offering an impressive combination of size, power efficiency, and performance. Armed with dual ARM Cortex M4 processors, this chip can operate independently or as a co-processor to enable AI functionalities such as smart locks and security monitoring. The KL520 is adept at 3D sensor integration, making it an excellent choice for applications in smart home ecosystems. Its compact design allows devices powered by it to operate on minimal power, such as running on AA batteries for extended periods, showcasing its exceptional power management capabilities.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
The DisplayPort 1.4 core provides a comprehensive solution for DisplayPort requirements, implementing both source and sink capabilities. It supports link rates ranging from 1.62 Gbps to 8.1 Gbps, fitting standard DisplayPort and eDP scenarios efficiently. Users can take advantage of its support for multiple lanes, specifically 1, 2, and 4 lanes configurations, enabling versatile video interface options such as Native and AXI stream interfaces. This facilitates a strong multimedia performance, catering to both Single Stream Transport (SST) and Multi Stream Transport (MST) modes. The video processing toolkit accompanying this IP aims at aiding users in diverse video operations. These tools include a timing generator, a versatile test pattern generator, and crucial video clock recovery mechanisms. To simplify the integration into various systems, the IP is supported across a broad range of FPGA devices, including AMD and Intel lines, providing users with choice and flexibility for their specific application needs. Notably, it supports diverse video formats and color spaces, such as RGB, YCbCr 4:4:4, 4:2:2, and 4:2:0 at pixel depths of 8 and 10 bits. Secondary data packets handling audio and metadata enhance its multimedia capabilities. Furthermore, Parretto offers the source code on GitHub for ease of custom development, ensuring developers have the tools they need to adapt the IP to their unique systems.
The ISPido on VIP Board is tailored specifically for Lattice Semiconductor's Video Interface Platform (VIP) and is designed to achieve clear and balanced real-time imaging. This ISPido variant supports automatic configuration options to provide optimal settings the moment the board is powered on. Alternatively, users can customize their settings through a menu interface, allowing for adjustments such as gamma table selection and convolutional filtering. Equipped with the CrossLink VIP Input Bridge, the board features dual Sony IMX 214 image sensors and an ECP5 VIP Processor. The ECP5-85 FPGA ensures reliable processing power while potential outputs include HDMI in YCrCb 4:2:2 format. This flexibility ensures users have a complete, integrated solution that supports runtime calibration and serial port menu configuration, making it an extremely practical choice for real-time applications. The ISPido on VIP Board is built to facilitate seamless integration and high interoperability, making it a suitable choice for those engaged in designing complex imaging solutions. Its adaptability and high-definition support make it particularly advantageous for users seeking to implement sophisticated vision technologies in a variety of industrial applications.
The Hyperspectral Imaging System developed by Imec is designed to capture images across numerous wavelengths, enabling detailed analysis of spectral information beyond conventional imaging. This hyperspectral imaging technology is pivotal in extracting valuable insights in fields such as precision agriculture, environmental monitoring, and industrial inspection. With its versatile applications, it offers enhanced capabilities in material identification, chemical analysis, and quality control processes. This system incorporates state-of-the-art sensors that capture data with high spectral and spatial resolution, providing a comprehensive spectral fingerprint of the imaged scene. It excels in distinguishing subtle differences in material properties by analyzing the light reflected from different surfaces across various spectral bands. By using this advanced imaging system, users can perform complex analyses such as vegetation monitoring, pollution detection, and mineral mapping with unprecedented precision. It allows for non-destructive testing, which is crucial for industries like food safety, pharmaceutical production, and environmental science.
ISPido is a powerful and flexible image signal processing pipeline tailored for high-resolution image processing and tuning. It supports a comprehensive pipeline of image enhancement features such as defect correction, color filter array interpolation, and various color space conversions, all configurable via the AXI4-LITE protocol. Designed to handle input depths of 8, 10, or 12 bits, ISPido excels in processing high-definition resolutions up to 7680x7680 pixels, making it highly suitable for a variety of advanced vision applications. The architecture of ISPido is built to be highly compatible with AMBA AXI4 standards, ensuring that it can be seamlessly integrated into existing systems. Each module in the pipeline is individually configurable, allowing for extensive customization to optimize performance. Features such as auto-white balance, gamma correction, and HDR chroma resampling empower developers to produce precise and visually accurate outputs in complex environments. ISPido's modular and versatile design makes it an ideal choice for deploying in heterogeneous processing environments, ranging from low-power battery-operated devices to sophisticated vision systems capable of handling resolutions higher than 8K. This adaptability makes it a prime solution for developers working across various sectors demanding high-quality image processing.
Featuring a shader architecture, the GSV3100 supports OpenGL ES 2.0 and 1.1, as well as OpenVG 1.1, for powerful 3D graphical processing. This IP is ideal for complex rendering tasks in applications requiring sophisticated graphics and animation. It efficiently integrates hardware processing pipelines to handle demanding graphics loads without compromising on performance or energy efficiency.
The Tentiva FMC board is a robust platform designed for superior video processing capabilities. Featuring a modular setup, it supports extensive customization and application-specific configuration with dual modular PHY slots tailored for flexible expansions. This design facilitates effortless connection with various PHY cards, granting users the adaptability needed for a broad spectrum of video communication applications. Supporting data rates up to 20 Gbps, the Tentiva board is equipped to handle high-speed communication, ensuring smooth and efficient video data processing. Its compatibility with myriad FPGA development boards courtesy of a standard FMC header, further accentuates its usability in diverse operational contexts. From video transmission to intricate processing tasks, the Tentiva board ensures quality and reliability across all video endeavors. The availability of specialized PHY cards, including DisplayPort and HDMI interfaces, enables unparalleled customization options, allowing developers to address precise project needs with ease. As a resource for advanced video applications, Tentiva exemplifies Parretto’s innovative approach to impactful, scalable technology solutions.
Combining 2D vector and 3D rendering capabilities, the GV580 is designed for high performance and low power consumption. It supports both OpenVG 1.1 and OpenGLES 1.1 standards, bringing together advanced rendering features suitable for a wide range of graphical applications. This GPU IP is perfect for enhancing device displays with dynamic graphics without overloading the CPU.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
The JPEG2000 Video Compression Solution is designed to enable high-quality video compression and decompression within FPGAs, supporting both lossy and lossless compression. Utilizing JPEG2000 standards, the solution provides superior image quality and flexibility for a wide range of applications, from digital cinema to medical imaging. It allows for scalable processing, eliminating the need for external processors, and supports extensive customization to meet specific project needs.
Recognized as a powerful tool in audio coding, the MPEG-H Audio System has transformed audio experiences for both television and virtual reality ecosystems. By supporting immersive and interactive soundscapes, it allows viewers to control elements like dialogue levels and creates a more personalized listening experience. The adoption of this system in international broadcasting standards is a testament to its robustness and innovation.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The v-MP6000UDX Visual Processing Unit is a powerhouse of the Videantis portfolio, offering extensive capabilities for handling deep learning, computer vision, and video coding across a singular architecture. This unit brings prowess in processing tasks that require real-time performance and energy efficiency, making it pivotal for next-generation intelligent devices. Designed to support multiple computational requirements, the v-MP6000UDX processes deep learning models efficiently, acting as a unified platform that negates the need for disparate hardware accelerators. This processor's architecture is optimized for running complete neural networks swiftly and at low power, facilitating applications that demand rapid computing power with minimal energy constraints. Boasting a sophisticated memory hierarchy and high-bandwidth interfaces, the processor ensures efficient data handling and processing. Its enhanced memory architecture paired with a network-on-chip design fosters an environment where high-performance computations are achieved seamlessly. This makes the v-MP6000UDX suitable for deployment in complex systems such as autonomous vehicles, mobile technology, and industrial automation, where proficient data processing and precision are critical. Incorporating the latest design principles, the v-MP6000UDX unit integrates seamlessly into devices that require extensive video processing capabilities, benefiting from a vast library of codecs and support for emerging standards in video compression. This processing unit is indispensable for businesses aiming to enhance their product offerings with cutting-edge technology.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The H.264 UHD Hi422 Intra Video Encoder offers robust encoding for high-definition video, perfecting the balance between quality and speed for critical industries such as broadcast and medical imaging. This encoder is designed to work in tandem with its counterpart decoder for seamless, low-latency video processing. Supporting 3840x2160p video at 30fps, the encoder maintains high video quality with precise color fidelity using 10-bit color and YUV 4:2:2 chroma formats. Implemented on the versatile Xilinx Zynq-7000 platform, it optimizes logic and RAM utilization, ensuring optimal performance while leaving room for additional system enhancements.
As a pioneer in advanced semiconductor technologies, the PCIe Gen 7 by PrimeSOC Technologies sets a new benchmark for high-performance computing with unprecedented speed. Leveraging a phenomenal data rate of 128 GT/s, it is engineered to handle growing demands in data transfer and computational efficiency. Designed with ultra-low latency and optimized for maximum throughput, PCIe Gen 7 is ideal for the most demanding applications, including next-gen graphics processing and data-intensive workloads. Its architecture supports multiple topologies such as root port, endpoint, and retimer, ensuring comprehensive applicability and flexibility in deployment. The build includes advanced error correction, robust reliability measures, and scalability—vital for seamless integration into today's and future computing environments. It also includes features like Forward Error Correction (FEC), enhancing data integrity and system dependability, making it a compelling solution for future-proofing tech deployments.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The AAC-LC and HE-AAC Audio Decoder is engineered to handle real-time audio stream decoding, offering versatility through support for AAC-LC and HE-AAC formats. It is designed for reliability and high performance, catering to modern audio applications demanding precision and speed. This decoder supports multiple audio streams, perfect for complex environments where synchronization and upgradability are necessary. It facilitates seamless and efficient decoding without compromising on audio quality, essential for professional and consumer multimedia applications. Blending seamlessly with Coreworks' Multimedia Platform, this decoder optimizes energy use while maintaining a low silicon area requirement. Its robust performance metrics ensure it is well-suited for decoding tasks in dynamic audio environments, making it a preferred choice for high-fidelity needs.
The v-MP4000UDX Visual Processing Unit by Videantis is a formidable processing solution designed to meet the demands of modern deep learning and computer vision applications. This unit integrates key functionalities of image and signal processing with enhanced capabilities for video coding. Its architecture is designed to handle various data-intensive tasks on a single platform, reducing the complexity involved in developing and integrating such functionalities into embedded systems. Equipped with a unified architecture, the v-MP4000UDX ensures all embedded processing activities take place without requiring additional hardware or extensive power resources. This integration allows for streamlined workflows that keep power usage and costs to a minimum. It supports tasks like neural network computation, making it ideal for devices that require advanced visual processing such as automotive systems, mobile devices, and professional-grade equipment. The v-MP4000UDX Visual Processing Unit excels at processing high volumes of data efficiently. It is recognized for its ability to support a range of image processing functions, while also ensuring advanced video codec standards are maintained. This makes it an excellent choice for high-performance applications that demand low latency and high-quality output. The flexibility and power efficiency of this processing unit affirm its suitability for a wide array of professionals seeking reliable and cutting-edge technology solutions.
The AAC-LC and HE-AAC Audio Encoder is constructed to encode audio streams in real-time for demanding media applications. By supporting both AAC-LC and HE-AAC formats, it offers great versatility, making it suitable for various audio transmission needs while maintaining fidelity and reducing data rates. Optimized to work on FPGAs and ASICs, this encoder supports multiple audio streaming, enabling significant reductions in latency and improved synchronization of audio content. Its efficiency in coding reduces bandwidth requirements, contributing to streamlined network operations and storage. Incorporating the latest processing technologies, this encoder synchronizes seamlessly with Coreworks’ Multimedia Platform. This synergy enhances performance while minimizing energy use and silicon area, making it an excellent choice for contemporary digital audio processing systems.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!