All IPs > Multimedia > AV1
AV1 semiconductor IPs have become a pivotal component in the realm of multimedia processing. As a next-generation video codec developed by the Alliance for Open Media (AOMedia), AV1 is designed to deliver high-quality video experiences at remarkably efficient bitrates. This makes it particularly appealing for applications that demand top-tier video quality without compromising on data transmission efficiency, such as streaming services, video conferencing platforms, and various forms of digital media broadcasting.
In the rapidly evolving tech landscape, the demand for efficient data processing and transmission is paramount. AV1 semiconductor IPs offer an innovative solution by significantly reducing the bandwidth requirements for video streaming. This enables smoother delivery of high-resolution content over constrained networks, making AV1 an attractive choice for content providers aiming to deliver superior user experiences. Additionally, the open-source nature of AV1 allows for widespread adoption and adaptation across various applications and platforms.
Products within this category typically include encoder and decoder IP cores optimized for AV1 video processing. These cores are engineered to handle complex encoding tasks that efficiently compress video data without sacrificing quality, playing a crucial role in enabling high-definition streaming even at lower bitrates. As digital media consumption continues to surge, AV1 semiconductor IPs are expected to play an integral role in supporting the technological backbone necessary for emerging multimedia applications, mobile devices, and smart TVs.
Moreover, as part of a broader ecosystem, AV1 complements existing multimedia systems by providing a scalable and cost-effective solution for next-level video coding. This IP's inclusion in multimedia product offerings bridges the gap between burgeoning consumer demands and the technological requirements of the digital age. Its implementation not only ensures compatibility with modern standards but also provides a future-proof option for developers and manufacturers investing in cutting-edge multimedia solutions.
The KL720 AI SoC is designed for optimal performance-to-power ratios, achieving 0.9 TOPS per watt. This makes it one of the most efficient chips available for edge AI applications. The SOC is crafted to meet high processing demands, suitable for high-end devices including smart TVs, AI glasses, and advanced cameras. With an ARM Cortex M4 CPU, it enables superior 4K imaging, full HD video processing, and advanced 3D sensing capabilities. The KL720 also supports natural language processing (NLP), making it ideal for emerging AI interfaces such as AI assistants and gaming gesture controls.
The pPLL08 Family is a state-of-the-art lineup of all-digital RF frequency synthesizer PLLs engineered for high-frequency applications including 5G and WiFi. These PLLs are designed to deliver ultra-low jitter performance, achieving less than 300 femtoseconds RMS, while supporting frequencies up to 8GHz. Their exceptionally compact area of less than 0.05 square millimeters and low power consumption of under 15 milliwatts make them suitable for demanding RF environments. Built using Perceptia's second-generation digital PLL technology, the pPLL08 Family excels in maintaining consistent output regardless of PVT conditions, offering robust performance in RF applications as a local oscillator or clocking solution for high-performance ADCs and DACs. Its digital architecture minimizes interference from shared die circuits, ensuring superior signal-to-noise ratio performance. The PLLs in this family are available across numerous process technologies, including leading foundries like UMC and TSMC, ensuring flexibility and broad applicability. Perceptia also provides extensive integration support and adaptability for customization, tailoring solutions to meet specific hardware requirements and optimizing integration into various system architectures.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The JPEG XS Encoder/Decoder from Techno Mathematical Co., Ltd. is designed to offer visually lossless, ultra-low latency performance suitable for next-generation 5G applications. This innovative technology supports both still images and real-time video streams, making it ideal for high-quality, large-screen displays and bandwidth-efficient transmission over networks. Its mezzanine compression capabilities are particularly important for minimizing latency without sacrificing image quality, thus serving well in applications where high-speed, high-fidelity data handling is required, such as in broadcasting and professional media production.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
The HDR Core is engineered to deliver enhanced dynamic range image processing by amalgamating multiple exposures to preserve image details in both bright and dim environments. It has the ability to support 120dB HDR through the integration of sensors like IMX585 and OV10640, among others. This core applies motion compensation alongside detection algorithms to mitigate ghosting effects in HDR imaging. It operates by effectively combining staggered based, dual conversion gain, and split pixel HDR sensor techniques to achieve realistic image outputs with preserved local contrast. The core adapts through frame-based HDR processing even when used with non-HDR sensors, demonstrating flexibility across various imaging conditions. Tone mapping is utilized within the HDR Core to adjust the high dynamic range image to fit the display capabilities of devices, ensuring color accuracy and local contrast are maintained without introducing noise, even in low light conditions. This makes the core highly valuable in applications where image quality and accuracy are paramount.
Bitec's VESA Display Stream Compression (DSC) IP Core is crafted to meet the demands of modern video compression technologies by offering a visually lossless solution for real-time video streams. This IP core enables interoperability and efficient video data transmission by compressing video streams in a way that maintains quality while reducing bandwidth requirements significantly. With the growing need for efficient data handling in display technologies, DSC offers an industry-standard approach to shrink video sizes without losing image quality, thus enabling smoother and more efficient streaming and broadcasting processes. It’s particularly advantageous for high-definition interfaces like HDMI and DisplayPort, making it an essential component for manufacturers and developers focused on delivering high-resolution visual content. The core constructs a streamlined data flow, adaptable to various protocols and configurations, making it suitable for integration in both consumer electronics and professional broadcasting equipment. Serving as a bridge between high-quality display needs and limited bandwidth, the DSC IP core facilitates the adoption of higher-resolution displays such as 8K, without the penalties traditionally associated with high data throughput.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Designed for the latest graphics processing applications, the G-Series Controller supports GDDR6 memory, delivering remarkable throughput necessary for demanding multimedia tasks. Its architecture allows for data speeds up to 18 Gbps per pin and supports dual-channel implementation. The G-Series Controller integrates with a standard DFI 5.0 interface, offering hardware auto-initialization and robust error detection and correction capabilities for maintaining data integrity under heavy loads.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The MPEG-H Audio System brings a new dimension to audio experiences in TVs and Virtual Reality (VR), offering users an immersive and interactive sound environment. Known for its advanced capabilities, this system allows for personalized audio adjustments which enable listeners to modify elements of the sound to their liking, such as changing the volume of dialogues or commentary. This customization ensures that the audio experience can be tailored to fit personal preferences, leading to enhanced viewer engagement and satisfaction. The MPEG-H Audio System is crucial for the next generation of broadcast services, being particularly adept at delivering high-quality, multi-dimensional sound over a range of devices. This readiness for future audio trends aligns perfectly with modern media consumption needs, where immersive experiences are increasingly demanded. In terms of functionality, the MPEG-H system supports not only traditional stereo and surround sound but also advanced setups through headphones, soundbars, and television speakers, accommodating varying listener environments. Another significant aspect of the MPEG-H Audio System is its integration into various international broadcast standards, underscoring its versatility and wide applicability. It brings unrivaled clarity and dynamics to television broadcasts and VR simulations, pushing the boundaries of sound technology and augmenting the audio-visual narrative of both everyday and cinematic content. Its implementation heralds a shift toward more engaging and personalized media consumption experiences.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is an advanced solution designed for high-speed data transmission applications. This core incorporates all necessary high-speed serial link blocks, such as high-speed drivers and PLL architectures, which enable precise clock recovery and signal synchronization.\n\nThe transceiver core is compliant with IEEE 802.3z for Gigabit Ethernet and is also compatible with Fibre Channel standards, ensuring robust performance across a variety of network settings. It features an inherently full-duplex operation, providing simultaneous bidirectional data paths through its 10-bit controller interface. This enhances communication efficiency and overall data throughput.\n\nParticularly suited for networks requiring low jitter and high-speed operation, this transceiver includes proprietary technology for superior jitter performance and noise immunity. Its implementation in low-cost, low-power CMOS further provides a cost-effective and energy-efficient solution for high-speed networking requirements.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The Video Anonymization solution by Gyrus AI is designed to meet regulatory compliance mandates like GDPR by ensuring the privacy of individuals captured in videos. By using advanced AI techniques, it automatically detects and blurs faces, license plates, and other sensitive information in video footage. This tool not only complies with global data privacy laws but also maintains video quality, allowing businesses to handle, process, and share video content securely and ethically. One of the standout features of this solution is its ability to replace real faces with AI-generated synthetic characters. This means that identity protection is assured without losing critical non-identifying attributes, making it exceptionally suitable for industries such as automotive, healthcare, and media. The system's automated nature means that it can handle large datasets efficiently, up to 10 times more than conventional methods, and at a significantly reduced cost, often lowering expenses by up to 70%. The solution integrates seamlessly into existing workflows, thanks to its high degree of customization and compliance with various industry standards. Whether used in real-time or batch processing, its superior anonymization capabilities outperform traditional methods, enhancing privacy levels while facilitating post-processing analytics like emotion tracking and gaze detection. Gyrus AI’s tool empowers organizations to meet privacy standards effectively, thereby facilitating secure media sharing and analysis.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
TicoXS represents a revolutionary approach to image compression, setting new standards with its JPEG XS compliance. Designed by intoPIX, this technology ensures ultra-low latency and high-quality image transmission, suitable for live video feeds and other applications demanding real-time responsiveness. The IP cores are highly efficient, maintaining exceptional visual quality even at significantly reduced data rates, making it perfect for bandwidth-limited scenarios. TicoXS can be integrated into a wide range of devices including FPGAs and ASICs, offering remarkable flexibility for developers. Moreover, the support for multiple color spaces and sampling formats such as 4:2:2 and 4:4:4 makes it adaptable for varied image processing needs. TicoXS effortlessly tackles the challenges posed by high definition and ultra-high definition formats, delivering a seamless compression solution that is both resource-optimized and performance-tuned, underpinning its reputation for creating visually lossless compression even under extreme conditions.
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The H.264 Encoder from VISENGI stands as one of the market's most rapid solutions, capable of processing greater than 4K resolution at 60 frames per second, even on mid-range FPGA devices. This encoder is engineered for high-efficiency video compression, crucial for applications requiring the transmission or storage of high-quality video while minimizing bandwidth use. Its design ensures minimal delay and supports a wide array of devices, making it versatile for various digital video applications. This IP core is specifically optimized for performance across diverse hardware configurations, including both FPGA and ASIC setups. The architecture of the encoder includes advanced features that facilitate reduced power consumption while maintaining peak operational efficiency. This makes it an ideal choice for mobile and embedded systems where resources may be limited but high-quality video processing is required. Another significant advantage of VISENGI's H.264 Encoder is its scalability and flexibility. Whether used in a live broadcast setting or during complex post-production editing, its robust construction ensures consistent performance. The encoder integrates seamlessly with existing video infrastructures, providing an essential tool for professionals aiming to deliver high-definition media content.
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The JPEG XS Encoder & Decoder IP cores from intoPIX are crafted to deliver high-quality, real-time image compression and decompression capabilities. These cores represent the cutting-edge of compression technologies, providing a visually lossless solution ideal for applications requiring minimal latency and seamless interoperability with existing infrastructures. Capable of supporting a variety of color formats and resolutions, this IP is particularly well-suited for live media production, archiving, and collaborative workflows. JPEG XS standard's efficiency lies in its ability to compress data at ratios from visually lossless to near-lossless, suitable for delivering high-resolution video over standard networks without the overhead commonly associated with previous solutions. These encoder and decoder cores are scalable and compatible with various hardware configurations, making them adaptable to evolving market needs while ensuring cost-effective deployment.
Allegro DVT's AV1 Decoder, capable of 12-bit pixel size and 4:4:4 chroma sub-sampling, is crafted to support the latest innovations in video format technology. This decoder is instrumental in facilitating crisp and vibrant video playback, positioning itself as pivotal in the ongoing adaptation to new video standards in the market. Its design is tailored to manage the intricacies of high-resolution video streams efficiently, providing users with seamless video playback experiences. The decoder's ability to handle AV1, which is gaining traction as a next-generation video format, highlights Allegro DVT's commitment to staying ahead in video codec innovation. It is well-suited for applications demanding superior color fidelity and depth, such as digital broadcasting, streaming services, and media production firms. With an architecture that balances performance with minimal resource strain, this AV1 Decoder reduces the typical bottlenecks often experienced in high-demand video processing. This ensures that end-users receive uninterrupted, high-quality viewing experiences, making it a cornerstone of Allegro DVT’s media solutions.
Rafael Micro's RT125 is a high-performance component designed for optical communication networks, providing essential signal integrity and amplification functionalities. It integrates a Clock Data Recovery (CDR) circuit, Limiting Amplifier (LA), and Trans-Impedance Amplifier (TIA), capable of handling data rates up to 28Gbps. This combination offers a streamlined solution for amplifying weak signals and restoring clean data streams in telecommunications systems. Specifically designed for data centers and telecommunication infrastructures, the RT125 is optimized for integration into dense, high-bandwidth environments requiring robust data recovery and signal conditioning. Its high data rate and compact design suit high-speed network interfaces, supporting seamless data transmission over extended distances. The RT125 enhances overall system performance by leveraging leading-edge CMOS technology to ensure power-efficient operation and reliable signal processing. Its architecture handles substantial digital traffic while minimizing noise and maximizing data throughput, contributing to the overall efficacy of advanced optical network solutions.
This cryptographic IP core provides heightened security for message authentication codes, specifically using HMAC-SHA2 with defenses against differential power analysis and fault injection. It is tailored to facilitate secure communications in sensitive environments where both data integrity and privacy are crucial.
In-Memory-Compute technology from DXCorr transforms traditional memory into a dynamic processing unit, fundamentally altering the data processing landscape. It allows computations to take place directly in memory, reducing the latency and energy typically required to shuttle data between the processor and RAM. This innovation is ideal for data-intensive computations prevalent in artificial intelligence and big data sectors. The architecture underlying this solution integrates with SRAM and DRAM, leveraging both their storage capabilities and operational speed, to allow parallel processing and reduce overall computational overhead. By doing so, it significantly mitigates bandwidth bottlenecks, empowering applications to achieve higher throughput and enhanced performance metrics. DXCorr's In-Memory-Compute technology is not only a catalyst for high-performance computing but also an enabler of energy efficiency, apt for environments where power savings are critical. This technology positions itself at the forefront of the AI revolution, enabling near-memory acceleration of tasks that demand real-time processing, consequently enhancing the capability of devices including smart appliances and automotive electronics.
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