All IPs > Multimedia > AV1
AV1 semiconductor IPs have become a pivotal component in the realm of multimedia processing. As a next-generation video codec developed by the Alliance for Open Media (AOMedia), AV1 is designed to deliver high-quality video experiences at remarkably efficient bitrates. This makes it particularly appealing for applications that demand top-tier video quality without compromising on data transmission efficiency, such as streaming services, video conferencing platforms, and various forms of digital media broadcasting.
In the rapidly evolving tech landscape, the demand for efficient data processing and transmission is paramount. AV1 semiconductor IPs offer an innovative solution by significantly reducing the bandwidth requirements for video streaming. This enables smoother delivery of high-resolution content over constrained networks, making AV1 an attractive choice for content providers aiming to deliver superior user experiences. Additionally, the open-source nature of AV1 allows for widespread adoption and adaptation across various applications and platforms.
Products within this category typically include encoder and decoder IP cores optimized for AV1 video processing. These cores are engineered to handle complex encoding tasks that efficiently compress video data without sacrificing quality, playing a crucial role in enabling high-definition streaming even at lower bitrates. As digital media consumption continues to surge, AV1 semiconductor IPs are expected to play an integral role in supporting the technological backbone necessary for emerging multimedia applications, mobile devices, and smart TVs.
Moreover, as part of a broader ecosystem, AV1 complements existing multimedia systems by providing a scalable and cost-effective solution for next-level video coding. This IP's inclusion in multimedia product offerings bridges the gap between burgeoning consumer demands and the technological requirements of the digital age. Its implementation not only ensures compatibility with modern standards but also provides a future-proof option for developers and manufacturers investing in cutting-edge multimedia solutions.
xcore.ai is XMOS Semiconductor's innovative programmable chip designed for advanced AI, DSP, and I/O applications. It enables developers to create highly efficient systems without the complexity typical of multi-chip solutions, offering capabilities that integrate AI inference, DSP tasks, and I/O control seamlessly. The chip architecture boasts parallel processing and ultra-low latency, making it ideal for demanding tasks in robotics, automotive systems, and smart consumer devices. It provides the toolset to deploy complex algorithms efficiently while maintaining robust real-time performance. With xcore.ai, system designers can leverage a flexible platform that supports the rapid prototyping and development of intelligent applications. Its performance allows for seamless execution of tasks such as voice recognition and processing, industrial automation, and sensor data integration. The adaptable nature of xcore.ai makes it a versatile solution for managing various inputs and outputs simultaneously, while maintaining high levels of precision and reliability. In automotive and industrial applications, xcore.ai supports real-time control and monitoring tasks, contributing to smarter, safer systems. For consumer electronics, it enhances user experience by enabling responsive voice interfaces and high-definition audio processing. The chip's architecture reduces the need for exterior components, thus simplifying design and reducing overall costs, paving the way for innovative solutions where technology meets efficiency and scalability.
The KL720 AI SoC is designed for optimal performance-to-power ratios, achieving 0.9 TOPS per watt. This makes it one of the most efficient chips available for edge AI applications. The SOC is crafted to meet high processing demands, suitable for high-end devices including smart TVs, AI glasses, and advanced cameras. With an ARM Cortex M4 CPU, it enables superior 4K imaging, full HD video processing, and advanced 3D sensing capabilities. The KL720 also supports natural language processing (NLP), making it ideal for emerging AI interfaces such as AI assistants and gaming gesture controls.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
ISPido is a powerful and flexible image signal processing pipeline tailored for high-resolution image processing and tuning. It supports a comprehensive pipeline of image enhancement features such as defect correction, color filter array interpolation, and various color space conversions, all configurable via the AXI4-LITE protocol. Designed to handle input depths of 8, 10, or 12 bits, ISPido excels in processing high-definition resolutions up to 7680x7680 pixels, making it highly suitable for a variety of advanced vision applications. The architecture of ISPido is built to be highly compatible with AMBA AXI4 standards, ensuring that it can be seamlessly integrated into existing systems. Each module in the pipeline is individually configurable, allowing for extensive customization to optimize performance. Features such as auto-white balance, gamma correction, and HDR chroma resampling empower developers to produce precise and visually accurate outputs in complex environments. ISPido's modular and versatile design makes it an ideal choice for deploying in heterogeneous processing environments, ranging from low-power battery-operated devices to sophisticated vision systems capable of handling resolutions higher than 8K. This adaptability makes it a prime solution for developers working across various sectors demanding high-quality image processing.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
Recognized as a powerful tool in audio coding, the MPEG-H Audio System has transformed audio experiences for both television and virtual reality ecosystems. By supporting immersive and interactive soundscapes, it allows viewers to control elements like dialogue levels and creates a more personalized listening experience. The adoption of this system in international broadcasting standards is a testament to its robustness and innovation.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
The HDR Core from ASICFPGA addresses the frequent issue of capturing images with a high dynamic range that surpasses the sensor’s capabilities. By acquiring multiple exposures at different levels, this core synthesizes them into a single image that adequately preserves details across various lighting conditions. Incorporating advanced motion detection and compensation algorithms, it minimizes ghosting and compresses the high dynamic range to fit within the display device's capabilities through a unique tone mapping procedure.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is an advanced solution designed for high-speed data transmission applications. This core incorporates all necessary high-speed serial link blocks, such as high-speed drivers and PLL architectures, which enable precise clock recovery and signal synchronization.\n\nThe transceiver core is compliant with IEEE 802.3z for Gigabit Ethernet and is also compatible with Fibre Channel standards, ensuring robust performance across a variety of network settings. It features an inherently full-duplex operation, providing simultaneous bidirectional data paths through its 10-bit controller interface. This enhances communication efficiency and overall data throughput.\n\nParticularly suited for networks requiring low jitter and high-speed operation, this transceiver includes proprietary technology for superior jitter performance and noise immunity. Its implementation in low-cost, low-power CMOS further provides a cost-effective and energy-efficient solution for high-speed networking requirements.
The Flat Panel Display Interface for Advanced Processes is a sophisticated interface designed to support high-frequency display communication standards such as LVDS, mini-LVDS, and MIPI D-PHY. Tailored for modern display technologies, this interface IP provides seamless integration and communication between display panels and processors, ensuring high-quality video output and color accuracy. Engineered to cater to advanced semiconductor processes, the Flat Panel Display Interface operates at maximum frequencies of up to 1250 MHz, making it highly suitable for high-definition displays. The ability to interface various display protocols allows it to handle multiple display formats efficiently, facilitating rapid data transfer and high-definition image rendering. This adaptability ensures the IP can meet the diverse requirements of both consumer electronics and professional display applications. By supporting a wide range of bit depths and channel configurations, the interface is able to deliver exceptional video quality with minimal latency. Its low power consumption profile makes it ideal for battery-operated devices, including portable displays and digital signage. The IP's design also focuses on minimal physical footprint, optimizing it for compact and efficient integration into hardware designs. Implementing the Flat Panel Display Interface IP enhances the display subsystem by optimizing the data flow and ensuring precise synchronization between its elements. Its compatibility with advanced process nodes supports more sustainable and energy-efficient display products, bolstering the overall user experience.
The v-MP6000UDX Visual Processing Unit is a powerhouse of the Videantis portfolio, offering extensive capabilities for handling deep learning, computer vision, and video coding across a singular architecture. This unit brings prowess in processing tasks that require real-time performance and energy efficiency, making it pivotal for next-generation intelligent devices. Designed to support multiple computational requirements, the v-MP6000UDX processes deep learning models efficiently, acting as a unified platform that negates the need for disparate hardware accelerators. This processor's architecture is optimized for running complete neural networks swiftly and at low power, facilitating applications that demand rapid computing power with minimal energy constraints. Boasting a sophisticated memory hierarchy and high-bandwidth interfaces, the processor ensures efficient data handling and processing. Its enhanced memory architecture paired with a network-on-chip design fosters an environment where high-performance computations are achieved seamlessly. This makes the v-MP6000UDX suitable for deployment in complex systems such as autonomous vehicles, mobile technology, and industrial automation, where proficient data processing and precision are critical. Incorporating the latest design principles, the v-MP6000UDX unit integrates seamlessly into devices that require extensive video processing capabilities, benefiting from a vast library of codecs and support for emerging standards in video compression. This processing unit is indispensable for businesses aiming to enhance their product offerings with cutting-edge technology.
JPEG XS Encoder/Decoder is crafted for visually lossless transmission with ultra-low latency, tailored to accommodate the next-generation demands of 5G technology, large screens, and high-quality video. This codec showcases exceptional performance, making it ideal for applications demanding mezzanine compression with minimal delay. The encoder and decoder pair seamlessly adapts to environments requiring high efficiency and speed, fitting well within both consumer electronics and professional broadcasting needs. It addresses the urgent requirements of industries looking to minimize bandwidth while preserving image integrity. With the integration of JPEG XS, stakeholders can confidently broadcast and stream high-definition content, ensuring a smooth, visually pristine experience. Its functionality is enhanced for environments where speed and quality are paramount, supporting a broad array of display and transmission scenarios.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
TicoXS is a cutting-edge FPGA/ASIC IP core designed for implementing the JPEG XS compression standard. This technology is acclaimed for delivering ultra-low latency and impeccable video quality while minimizing complexity and resource requirements. TicoXS cores are applicable for resolutions ranging from HD to 8K and beyond, supporting both progressive and interlaced frames with high frame rates. Its versatility and efficiency make it suitable for various applications, including broadcast, live production, and high-resolution video transmission in bandwidth-constrained environments.\n\nThe architecture of TicoXS offers remarkable benefits in terms of power consumption and silicon area, making it ideal for integration into compact and portable devices. It provides flexible color sampling and bit depth support, including 4:4:4, 4:2:2, and 4:2:0, catering to the diverse needs of different media formats and production environments. The cores are available for a range of FPGA devices from AMD, Intel, and other manufacturers, making it highly adaptable to different technological setups.\n\nOne of the standout features of TicoXS is its ability to maintain visually lossless quality while providing compression ratios from mathematically lossless to visually lossless settings, configurable up to 36:1. Its robust support for HDR and SDR video content allows for seamless handling of high dynamic range imagery, making it a superior choice for professional-grade visual applications. Whether for serial digital interface (SDI) mapping or integrated into IP-based video transport systems, TicoXS excels in delivering high-performance image compression.\n\nFurthermore, TicoXS's low latency is crucial for live broadcast and interactive applications, offering nearly instantaneous video transmission with remarkably low power usage. By incorporating TicoXS cores, developers and manufacturers can enhance their products' capabilities, ensuring compatibility with future standards and the increasing data volumes associated with high-resolution video. This technology represents a significant step forward in the efficient handling and distribution of video over varying network speeds and compute capabilities.
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The H.264 UHD Hi422 Intra Video Encoder offers robust encoding for high-definition video, perfecting the balance between quality and speed for critical industries such as broadcast and medical imaging. This encoder is designed to work in tandem with its counterpart decoder for seamless, low-latency video processing. Supporting 3840x2160p video at 30fps, the encoder maintains high video quality with precise color fidelity using 10-bit color and YUV 4:2:2 chroma formats. Implemented on the versatile Xilinx Zynq-7000 platform, it optimizes logic and RAM utilization, ensuring optimal performance while leaving room for additional system enhancements.
EdgeThought by Skymizer focuses on bringing high-efficiency AI inferencing capabilities directly to edge devices. This IP is centered around a compiler-driven, software-hardware co-design that ensures optimal resource efficiency in executing large language model (LLM) inferences. Engineered to minimize hardware demands, EdgeThought’s architecture is compact yet powerful, making it ideal for use in constrained memory environments. EdgeThought's dynamic decompression engine is a hallmark feature, facilitating on-the-fly model weight decompression which reduces both storage requirements and memory bandwidth consumption, all while maintaining high inference accuracy. This approach enables EdgeThought to enhance execution efficiency without the need for expensive, state-of-the-art hardware, making cutting-edge AI more accessible and cost-effective. Built on the robust LISA v2 and v3 architectures, EdgeThought integrates seamlessly with existing AI ecosystems, supporting popular LLM frameworks like HuggingFace and OpenAI APIs. This integration is complemented by a broad toolkit that includes tools for finetuning and retrieval-augmented generation, underscoring EdgeThought’s adaptability in various AI applications from IoT devices to high-performance edge servers.
The JPEG 2000 CODEC by intoPIX provides an advanced solution for image and video compression, known for its flexibility and robust performance across a wide range of applications. Used extensively in cinema, broadcast, and archiving, this codec is optimized to handle both compression efficiency and high image quality. It supports a variety of bit depths and color spaces, including RGB, YUV, and XYZ, with applications spreading from standard to ultra-high-definition content.\n\nThis codec is recognized for its mathematically lossless compression ability, making it suitable for applications where image integrity must remain flawless, such as medical imaging and digital cinema. JPEG 2000 can be configured for visually lossless to compressed formats, offering scalable quality options which can significantly reduce bandwidth and storage requirements without compromising output quality.\n\nIntegrated into FPGA or ASIC designs, the JPEG 2000 codec ensures ultra-low latency performance, crucial for real-time applications. Its scalability and compliance with international standards make it versatile for use across different media types, providing unmatched compression ratios and visual fidelity.\n\nIn a broadcast setting, JPEG 2000 is employed for its superior error resilience and the ability to transmit images over varying networks with robustness to data loss. It supports various compression profiles and wavelet transformations to adapt to different usage scenarios, providing a powerful solution for high-performance media workflows and next-generation digital media handling.
The AVB Milan IP core is designed for advanced network communication within FPGA systems, facilitating Audio Video Bridging (AVB) which ensures precise timing and robust data exchange. This IP core is pivotal in environments requiring high-quality audio and video transmission with low latency, such as live broadcasts and synchronized multi-device setups. Optimized for real-time applications, the AVB Milan IP core provides mechanisms that guarantee time-sensitive data is delivered accurately across networked devices. It supports various AVB standards and integrates seamlessly with existing Ethernet infrastructures, ensuring backward compatibility while extending functionality for modern applications. This approach allows for enhanced streaming experiences, prioritizing both audio and video data to maintain synchronization. Engineers and developers benefit from the AVB Milan IP by obtaining a ready-to-use framework that simplifies complex network setups, allowing for efficient resource utilization and system scalability. These features are particularly advantageous in professional audio-visual environments where reliability and timing precision are non-negotiable requirements.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The RT125 by Rafael Micro is a 28Gbps SR CDR/LA/TIA designed to address the high-speed demands of optical communication systems. This component integrates a Clock Data Recovery (CDR) module, Limiting Amplifier (LA), and Trans-Impedance Amplifier (TIA) in a coherent architecture aimed at providing robust signal integrity even in demanding data rates. Engineered for high-speed environments, the RT125 optimizes data recovery processes with its CDR component, ensuring accuracy in signal timing alignment and reducing jitter. The Limiting Amplifier provides optimal signal amplification, refining signal resolution without introducing significant noise. Complementing this is the Trans-Impedance Amplifier, which transforms optical signals into usable electronic formats with heightened sensitivity. This integrated solution is particularly advantageous in data center interconnects and high-speed telecommunication networks. Its ability to handle complex optical signals with precision and efficiency distinguishes it in the arena of short-reach communication systems, where rapid data processing and minimal error rates are critical. Rafael Micro's RT125 paves the way for advancements in quick and dependable high-speed data link developments.
The SMPTE 2110-22 RTP Subsystem IP Cores are specifically designed for the reliable transportation of high-quality JPEG XS compressed video over IP networks. These IP cores are crucial for applications in modern broadcast infrastructures and media production environments where precision and quality cannot be compromised. Supporting SMPTE 2110 standards, these cores ensure seamless interoperability and integration with existing systems.\n\nCapable of handling high frame rates and various resolutions, the SMPTE 2110-22 RTP Subsystem IP Cores offer a flexible and robust solution for organizations transitioning from legacy infrastructures to IP-based broadcast systems. By leveraging JPEG XS compression, these cores facilitate high-quality video streaming with reduced bandwidth requirements while maintaining a visually lossless quality. This not only enhances the efficiency but also reduces the operational costs of broadcasting channels and streaming services.\n\nAn integral feature of these IP cores is their ability to handle multiple video streams simultaneously, optimizing the use of available network bandwidth. With sophisticated packetization and depacketization processes, the cores support low-latency video transmission, crucial for live broadcasts and interactive applications. The inherent flexibility of these cores allows them to be configured to suit the specific needs of different broadcast environments, ensuring maximum performance and reliability.\n\nEngineered for use in high-demand environments, the SMPTE 2110-22 RTP Subsystem IP Cores are built to withstand rigorous operational conditions, providing broadcast professionals with the tools they need to maintain uninterrupted, premium-quality video feeds. These IP cores are an essential component in the ongoing evolution of broadcast technology, facilitating enhanced media workflows and pushing the boundaries of what is achievable in modern video transport solutions.
The AV1 Decoder from Allegro DVT stands as a forward-thinking solution in video processing technology. Engineered to decode the AV1 format, this component supports 12-bit pixel depth and full 4:4:4 chroma sub-sampling, which results in remarkable video fidelity and color accuracy. This decoder is indispensable in high-resolution video applications, including future-ready broadcasting and content streaming environments that prioritize next-level visual quality. It is adept at handling massive data streams efficiently, ensuring smooth playback without impacting system performance. Designed with scalability in mind, the AV1 Decoder fits seamlessly into diverse multimedia frameworks, offering robust decoding capabilities that align with the most demanding standards in contemporary video technology. Its inclusion in any video system ensures superior video playback experience with minimal latency and maximum quality.
HyperThought represents a leap forward in AI IP design by Skymizer, purpose-built for large language models (LLMs) to maximize performance and power efficiency at the edge. Its design features advanced compression technologies that significantly reduce language model size, resulting in lower parameter counts and diminished DRAM bandwidth needs. HyperThought operates efficiently with LPDDR4/5 memory, minimizing footprint without compromising on model integrity. The architecture of HyperThought is built for balanced performance, combining high throughput capabilities with optimal area usage to achieve unmatched compute efficiency. It delivers robust performance even on a 28nm process node, pushing the boundaries of what's feasible in compact AI solutions. Its scalable architecture supports multi-core configurations for heightened processing power, while also allowing multi-chip integration to handle large-scale model requirements effectively, reaching up to 1200 tokens per second for expansive models. Security is integral to HyperThought’s design, incorporating the Language Instruction Set Architecture (LISA v3) to safeguard all operations. This makes it a foundational component for next-gen AI innovations, ensuring both versatility and protection in diverse AI applications. HyperThought thus stands out as a comprehensive platform optimized for the future of AI processing.
The In-Memory Compute technology developed by DXCorr introduces a transformative approach to processing by performing computations directly within the memory array, minimizing latency and power consumption. This innovative technology addresses the inefficiencies encountered in traditional architectures where data must be moved back and forth between the processor and memory. By eliminating this bottleneck, In-Memory Compute enhances the speed and power efficiency of operations, a crucial factor in applications requiring intensive data processing, such as AI and deep learning architectures. In-Memory Compute is designed to complement existing memory technologies by adding a layer of computation capability, transforming how systems manage large datasets. This approach not only accelerates computing tasks but also reduces the overall energy footprint of memory operations. Ideal for edge computing and IoT applications, the technology ensures faster data analytics and decision-making, enabling devices to operate more autonomously. DXCorr's implementation of In-Memory Compute is geared towards scalable deployment, promising versatility across various technological landscapes. By merging memory and compute functions, this technology opens new pathways for system architects to explore innovative configurations that can adapt to complex computing demands, fostering advancements in various sectors, including automotive, healthcare, and consumer electronics.
The HDMI 2.0 IP core offers a full-featured solution for HDMI connectivity, suitable for diverse multimedia applications. This IP core is meticulously crafted to support both HDMI 1.4 and 2.0 standards, addressing varied compatibility requirements. Designed for precision, this IP facilitates seamless video processing with both RGB and YCbCr 4:4:4 formats, offering compatibility for 8-bit video systems. Engineered to enhance digital interface connections, this core enables dual and quad pixel clock configurations, ensuring efficient data throughput and quality rendering. Exclusive to the Lattice CertusPro-NX series, this IP integrates easily into existing systems, providing robust video transmission capabilities for high-performance exhibits and displays. Signifying Parretto’s commitment to quality and reliability, the HDMI 2.0 core is optimized for streamlined performance, reducing latency and accommodating high-definition outputs. Through this IP core, Parretto addresses the evolving demands of video technology, proving indispensable for video data processing in today's high-resolution domains. Its comprehensive support and flexibility make it a prime choice for developers focused on advanced video display solutions.
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