All IPs > Multimedia > AV1
AV1 semiconductor IPs have become a pivotal component in the realm of multimedia processing. As a next-generation video codec developed by the Alliance for Open Media (AOMedia), AV1 is designed to deliver high-quality video experiences at remarkably efficient bitrates. This makes it particularly appealing for applications that demand top-tier video quality without compromising on data transmission efficiency, such as streaming services, video conferencing platforms, and various forms of digital media broadcasting.
In the rapidly evolving tech landscape, the demand for efficient data processing and transmission is paramount. AV1 semiconductor IPs offer an innovative solution by significantly reducing the bandwidth requirements for video streaming. This enables smoother delivery of high-resolution content over constrained networks, making AV1 an attractive choice for content providers aiming to deliver superior user experiences. Additionally, the open-source nature of AV1 allows for widespread adoption and adaptation across various applications and platforms.
Products within this category typically include encoder and decoder IP cores optimized for AV1 video processing. These cores are engineered to handle complex encoding tasks that efficiently compress video data without sacrificing quality, playing a crucial role in enabling high-definition streaming even at lower bitrates. As digital media consumption continues to surge, AV1 semiconductor IPs are expected to play an integral role in supporting the technological backbone necessary for emerging multimedia applications, mobile devices, and smart TVs.
Moreover, as part of a broader ecosystem, AV1 complements existing multimedia systems by providing a scalable and cost-effective solution for next-level video coding. This IP's inclusion in multimedia product offerings bridges the gap between burgeoning consumer demands and the technological requirements of the digital age. Its implementation not only ensures compatibility with modern standards but also provides a future-proof option for developers and manufacturers investing in cutting-edge multimedia solutions.
The KL720 AI SoC is designed for optimal performance-to-power ratios, achieving 0.9 TOPS per watt. This makes it one of the most efficient chips available for edge AI applications. The SOC is crafted to meet high processing demands, suitable for high-end devices including smart TVs, AI glasses, and advanced cameras. With an ARM Cortex M4 CPU, it enables superior 4K imaging, full HD video processing, and advanced 3D sensing capabilities. The KL720 also supports natural language processing (NLP), making it ideal for emerging AI interfaces such as AI assistants and gaming gesture controls.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
ISPido is a comprehensive image signal processing (ISP) pipeline that is fully configurable via the AXI4-LITE protocol. It features a complete ISP pipeline incorporating modules for defective pixel correction, color filter array interpolation using the Malvar-Cutler algorithm, and a series of image enhancements. These include convolution filters, auto-white balance, color correction matrix, gamma correction, and color space conversion between RGB and YCbCr formats. ISPido supports resolutions up to 7680x7680, ensuring compatibility with ultra-high-definition applications, up to 8K resolution systems. It is engineered to comply with the AMBA AXI4 standards, offering versatility and easy integration into various systems, whether for FPGA, ASIC, or other hardware configurations.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The HDR Core is engineered to deliver enhanced dynamic range image processing by amalgamating multiple exposures to preserve image details in both bright and dim environments. It has the ability to support 120dB HDR through the integration of sensors like IMX585 and OV10640, among others. This core applies motion compensation alongside detection algorithms to mitigate ghosting effects in HDR imaging. It operates by effectively combining staggered based, dual conversion gain, and split pixel HDR sensor techniques to achieve realistic image outputs with preserved local contrast. The core adapts through frame-based HDR processing even when used with non-HDR sensors, demonstrating flexibility across various imaging conditions. Tone mapping is utilized within the HDR Core to adjust the high dynamic range image to fit the display capabilities of devices, ensuring color accuracy and local contrast are maintained without introducing noise, even in low light conditions. This makes the core highly valuable in applications where image quality and accuracy are paramount.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
MPEG-H Audio System enhances TV and virtual reality experiences by providing immersive and interactive audio. Capable of delivering high-quality sound, it supports personalized audio experiences where users can adjust audio elements such as dialogue and music levels. This adaptability revolutionizes how audiences interact with media, offering a customized experience that was previously unavailable. It's increasingly being adopted in broadcasting and virtual environments, ensuring compatibility with current and next-gen platforms.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is an advanced solution designed for high-speed data transmission applications. This core incorporates all necessary high-speed serial link blocks, such as high-speed drivers and PLL architectures, which enable precise clock recovery and signal synchronization.\n\nThe transceiver core is compliant with IEEE 802.3z for Gigabit Ethernet and is also compatible with Fibre Channel standards, ensuring robust performance across a variety of network settings. It features an inherently full-duplex operation, providing simultaneous bidirectional data paths through its 10-bit controller interface. This enhances communication efficiency and overall data throughput.\n\nParticularly suited for networks requiring low jitter and high-speed operation, this transceiver includes proprietary technology for superior jitter performance and noise immunity. Its implementation in low-cost, low-power CMOS further provides a cost-effective and energy-efficient solution for high-speed networking requirements.
VISENGI's H.264 Encoder is an advanced video compression solution renowned for its high-performance capabilities. Designed to accommodate modern high-resolution demands, this encoder allows UltraHD 4K 60 encoding on lower-end FPGAs like Spartan/Cyclone and extends to 8K 30fps on mid-range models such as Arria 10 and Zynq. Distinctive for its single-engine design, it provides the lowest latency and highest throughput in the industry, processing over 5.2 pixels per cycle. It supports various profiles such as the High 4:4:4 Predictive Profile, ensuring that full-color fidelity is maintained through options like 4:4:4, 4:2:2, and 4:2:0 inputs. The encoder is engineered to handle multiple inputs simultaneously, up to 32, enhancing its utility in complex systems with a single instance deployment. Its versatility in resolution scaling means it can manage any resolution from QVGA to 8K seamlessly. Real-time variable bit rate (VBR) and constant bit rate (CBR) control offer optimal management of H.264 parameters to meet specific video quality and file size requirements. Interface-wise, the encoder utilizes an AXI-Lite configuration and supports AXI3/4 for data I/O, making it broadly compatible and easy to deploy. Its robust architecture includes embedded DMA engines, optimized pixel input modes, and motion estimation options that contribute to its efficiency and performance. The output aligns with industry standards, encapsulating data in raw .264 byte streams and providing options for reconstructed video outputs.
The v-MP6000UDX Visual Processing Unit is a powerhouse of the Videantis portfolio, offering extensive capabilities for handling deep learning, computer vision, and video coding across a singular architecture. This unit brings prowess in processing tasks that require real-time performance and energy efficiency, making it pivotal for next-generation intelligent devices. Designed to support multiple computational requirements, the v-MP6000UDX processes deep learning models efficiently, acting as a unified platform that negates the need for disparate hardware accelerators. This processor's architecture is optimized for running complete neural networks swiftly and at low power, facilitating applications that demand rapid computing power with minimal energy constraints. Boasting a sophisticated memory hierarchy and high-bandwidth interfaces, the processor ensures efficient data handling and processing. Its enhanced memory architecture paired with a network-on-chip design fosters an environment where high-performance computations are achieved seamlessly. This makes the v-MP6000UDX suitable for deployment in complex systems such as autonomous vehicles, mobile technology, and industrial automation, where proficient data processing and precision are critical. Incorporating the latest design principles, the v-MP6000UDX unit integrates seamlessly into devices that require extensive video processing capabilities, benefiting from a vast library of codecs and support for emerging standards in video compression. This processing unit is indispensable for businesses aiming to enhance their product offerings with cutting-edge technology.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The Flat Panel Display Interface for Advanced Processes is a highly adaptable interface solution tailored for modern display technologies. It supports multiple data protocols, ensuring seamless communication between the main processor and display units. This interface product optimizes data handling capacities, making it ideal for applications requiring high-speed data exchange and complex display management. Designed for advanced processes, this display interface is highly efficient, reducing latency and improving overall performance. It supports various display formats, allowing for the integration of cutting-edge display technologies into high-functioning devices. Its comprehensive design is intended to boost the performance of advanced electronic display systems, making it a vital component in the development of high-resolution display products. The interface's adaptable configuration supports a range of operating environments and applications, facilitating efficient implementation across diverse platforms. Its robust construction ensures a long lifespan, contributing to the development of sustainable and reliable electronic solutions.
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
The TicoXS FPGA/ASIC IP Cores deliver a ground-breaking video compression standard known as JPEG XS. This technology is designed to handle visually lossless compression with little to no latency, perfectly suitable for real-time video transmission. TicoXS achieves unparalleled image quality and consistent performance due to its lightweight compression mechanisms, particularly beneficial for transmitting large volumes of video data efficiently. With its design suited for both FPGA and ASIC, TicoXS can operate robustly across various hardware platforms including Xilinx and Intel FPGAs. The IP cores support a wide spectrum of resolutions, from HD up to 10K, with flexibility in color space and bit depth which includes RGB, YUV, and more. This compatibility ensures that TicoXS cores can deliver real-time processing with remarkably low gate count and memory usage, tailored for high-speed content delivery systems. TicoXS is integral for applications that demand high-resolution outputs, such as broadcast, live production, and wireless video. The IP cores facilitate encoding and decoding of high-quality video streams, enabling seamless IP workflows. With added features such as adjustable compression rates and options for lossy and lossless modes, TicoXS provides ideal solutions for scenarios requiring streamlined data handling and pristine image quality in fast-paced media environments.
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Aimed at providing high-quality video encoding with minimal latency, the H.264 UHD Hi422 Intra Video Encoder surpasses industrial standards by supporting 4K video encoding suited for multiple high-demand applications. Its design excellence lies in handling 10-bit YUV 4:2:2 content seamlessly, ensuring sharp color contrasts and reducing gradient banding, making it ideal for medical, broadcast, and enterprise use. The encoder excels in maintaining low latency, meeting crucial performance needs in dynamic environments such as live news broadcasting and real-time video streaming. Utilizing the Xilinx Zynq-7000 architecture allows for reduced resource consumption while ensuring top-tier video quality and efficient IP streaming.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The AVB Milan IP is tailored for professional audio and video applications, adhering to the AVB standards for time-synchronized communication. It ensures deterministic data transfer, critical for audio networks and professional media systems. This IP guarantees low latency and precise timing, thus supporting complex audio and video systems' demands on synchronization and performance, differentiating it from conventional network protocols by offering real-time capabilities aligned with modern multimedia requirements.
The RT125 is a high-speed device capable of delivering 28Gbps, ideal for short-reach (SR) applications. It combines clock data recovery (CDR), limiting amplifier (LA), and trans-impedance amplifier (TIA) functionalities in a single compact package. Optimized for optical communication infrastructure, the RT125 is built to ensure minimal signal loss and maximum data integrity over short distances. This makes it suitable for modern data center applications where efficient, high-speed data interchange is critical.
The AV1 Decoder from Allegro DVT stands as a forward-thinking solution in video processing technology. Engineered to decode the AV1 format, this component supports 12-bit pixel depth and full 4:4:4 chroma sub-sampling, which results in remarkable video fidelity and color accuracy. This decoder is indispensable in high-resolution video applications, including future-ready broadcasting and content streaming environments that prioritize next-level visual quality. It is adept at handling massive data streams efficiently, ensuring smooth playback without impacting system performance. Designed with scalability in mind, the AV1 Decoder fits seamlessly into diverse multimedia frameworks, offering robust decoding capabilities that align with the most demanding standards in contemporary video technology. Its inclusion in any video system ensures superior video playback experience with minimal latency and maximum quality.
The In-Memory Compute technology developed by DXCorr introduces a transformative approach to processing by performing computations directly within the memory array, minimizing latency and power consumption. This innovative technology addresses the inefficiencies encountered in traditional architectures where data must be moved back and forth between the processor and memory. By eliminating this bottleneck, In-Memory Compute enhances the speed and power efficiency of operations, a crucial factor in applications requiring intensive data processing, such as AI and deep learning architectures. In-Memory Compute is designed to complement existing memory technologies by adding a layer of computation capability, transforming how systems manage large datasets. This approach not only accelerates computing tasks but also reduces the overall energy footprint of memory operations. Ideal for edge computing and IoT applications, the technology ensures faster data analytics and decision-making, enabling devices to operate more autonomously. DXCorr's implementation of In-Memory Compute is geared towards scalable deployment, promising versatility across various technological landscapes. By merging memory and compute functions, this technology opens new pathways for system architects to explore innovative configurations that can adapt to complex computing demands, fostering advancements in various sectors, including automotive, healthcare, and consumer electronics.
The H.264 Decoder from VISENGI is designed to work in harmony with their encoder, ensuring a seamless decode-encode cycle that maximizes efficiency and minimizes latency. It closely follows the profiles implemented by VISENGI's encoder, effectively handling the High 4:4:4 Predictive Profile and CAVLC 4:4:4 Intra Profile subsets. This tailored decoder guarantees synchronization with the encoder's high throughput while maintaining minimal latency throughout the process. A standout feature of the decoder is its capability to manage multiple streams in parallel, coupled with a scalable architecture that balances size, latency, and pixel throughput. This makes it exceptionally adaptable, be it for extensive data centers or compact hardware systems. Furthermore, it boasts a motion compensation module for enhanced video quality, particularly when paired with the encoder's motion estimation feature. The decoder supports a range of industry-standard interfaces, including AXI-Lite for configuration and AXI3/4 for input-output operations, which facilitate its integration into various hardware designs. Its robust structure is capable of dealing with extensive buffer requirements, offering up to 8 frame buffers per stream and maintaining color fidelity through 4:4:4 subsampling.
HMAC-SHA2-DPA-FIA by FortifyIQ provides an innovative solution for message authentication, with hardened protection against side-channel and fault injection attacks. Tailored to safeguard HMAC SHA2 operations, this IP remains an essential part of systems aiming to maintain high levels of security integrity. Designed to adapt to various computational environments, HMAC-SHA2-DPA-FIA guarantees that HMAC processing remains secure and efficient, regardless of external attempts to compromise system integrity. Its development is based on sophisticated algorithmic countermeasures that ensure operational resilience without impacting system performance. By aligning with stringent certification requirements, HMAC-SHA2-DPA-FIA is positioned as a reliable choice for industries needing assurances against data tampering and leakage during message authentication. This makes it particularly suitable for secure communications in sensitive fields like defense and finance.
Rambus's VESA Video Compression IP cores provide industry-leading visually lossless video compression for digital displays, supporting current and next-generation applications. These IP cores are crafted to harmonize high image quality with bandwidth efficiency, delivering impressive performance for mobile, AR/VR, and automotive displays. The solutions allow for the deployment of advanced display technologies in chip designs without trading off quality or system resources. Enabling ASIC and FPGA designs, these IPs are refined to offer maximum efficiency in managing video data streams. Through these innovations, Rambus addresses the skyrocketing demand for high-quality, high-speed video processing, ensuring compatibility with DisplayPort 1.4 and HDMI 2.1 applications.
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