All IPs > Interface Controller & PHY > I2C
The I2C Interface Controller & PHY category in our semiconductor IP catalog presents a crucial array of technologies tailored for seamless communication within embedded systems and a variety of electronic devices. The I2C, or Inter-Integrated Circuit, standard is a well-established protocol that facilitates serial communication, primarily in microcontrollers and other integrated circuits. Within this category, developers will find both controller IPs and Physical Layer (PHY) IPs designed to optimize the efficiency and functionality of I2C communications.
The products in this category include comprehensive controller IP cores that manage the I2C protocol, enabling devices to communicate over a shared bus efficiently. These controllers are essential components for systems requiring robust data exchange, such as sensor networks, home automation systems, and industrial control environments. Leveraging these IP cores can lead to significant reductions in design time, providing developers with a ready-to-use solution that adheres to standard I2C specifications while offering flexibility for customization.
PHY semiconductor IPs are crucial for ensuring the physical transmission of I2C data complies with electronic standards needed in various environments. They handle critical functions such as signal transmission, clock generation, and power management, thereby ensuring that data integrity is maintained across different system components and operating conditions. These IPs are particularly vital for applications that demand high reliability and performance in their I2C communications, such as automotive electronics, consumer devices, and medical equipment.
Integrating I2C Interface Controller & PHY semiconductor IPs can considerably enhance the performance of multi-device systems, offering scalable solutions that adapt to the increasing complexity of modern electronic configurations. By focusing on high efficiency and compatibility, these IPs support the development of innovative products that require reliable and efficient communication protocols, paving the way for advancements in technology and connectivity across industries.
The AHB-Lite APB4 Bridge is an adaptable soft interconnect bridge linking the AMBA 3 AHB-Lite protocol with the AMBA APB protocol. It facilitates seamless communication between these bus protocols, ensuring data transfers are conducted efficiently within an embedded system. This bridge supports parameterization, allowing engineers to configure it for their unique design needs, thereby improving system flexibility and performance in electronic projects.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
RegSpec is a cutting-edge tool that streamlines the generation of control and status register code, catering to the needs of IP designers by overcoming the limitations of traditional CSR generators. It supports complex synchronization and hardware interactions, allowing designers to automate intricate processes like pulse generation and serialization. Furthermore, it enhances verification by producing UVM-compatible code. This tool's flexibility shines as it can import and export in industry-standard formats such as SystemRDL and IP-XACT, interacting seamlessly with other CSR tools. RegSpec not only generates verilog RTL and SystemC header files but also provides comprehensive documentation across multiple formats including HTML, PDF, and Word. By transforming complex designs into streamlined processes, RegSpec plays a vital role in elevating design efficiency and precision. For system design, it creates standard C/C++ headers that facilitate firmware access, accompanied by SystemC models for advanced system modeling. Such comprehensive functionality ensures that RegSpec is invaluable for organizations seeking to optimize register specification, documentation, and CSR generation in a streamlined manner.
A trailblazer in high-speed rail connectivity, LightningBlu offers a groundbreaking, track-to-train multi-gigabit mmWave solution. This technology is renowned for its seamless integration with train networks, providing stable and fast connections crucial for high-speed transport. LightningBlu operates efficiently over a rail-friendly frequency range from 57-71 GHz and delivers an impressive data throughput of up to 3.5 Gbps. The system comprises both trackside and train-top nodes, each featuring innovative two-sector radios to ensure continuous, dynamic connection between the train and the trackside infrastructure. The design includes components qualified for rugged rail environments, promising extended service life and low maintenance needs. The solution significantly boosts operational efficiency for rail networks, being deployed in key infrastructures like South Western Railways and Caltrain in Silicon Valley. Versatile and resilient, LightningBlu adapts to varied complexities found in high-speed transport contexts. It communicates data faster than 5G while maintaining lower power consumption than traditional mobile networks, ensuring a superior commuter experience through its reliability and speed.
APB4 GPIO by Roa Logic is a comprehensive and adaptable core that introduces a user-defined number of general-purpose, bidirectional input and output channels to designs. It provides a flexible interface for developers who require customizable GPIO settings in their embedded systems, making it suitable for a wide range of applications in different industry verticals.
The Digital Blocks eSPI Master/Slave Controller IP is expertly tailored to conform with the Enhanced Serial Peripheral Interface (eSPI) Specification. It incorporates design flexibilities that allow it to function as either a master or a slave controller, enhancing its adaptability across various applications. Additionally, it is compliant with SPI specifications and supports AMBA interconnects such as AXI or AHB, further extending its interface and integration capabilities. This controller can handle the entire scope of eSPI operations, from the technical handling of the Bus Protocol to the intricacies of the Transaction and Link Layers. Given this robustness, the controller easily fits into high-demand environments where precise, reliable communication across SPI and eSPI networks is crucial. Developers can benefit from the design's extendable AMBA interfacing options, allowing it to interact with microprocessors via a spectrum of protocols. This ensures that the IP is suitable for environments where flexibility in interconnect compatibility maximizes the utility of embedded system designs, making it ideal for complex, multi-device platforms.
The 802.15.4 Transceiver Core is specifically crafted to support low-power, wireless personal area networks. As a standard for Zigbee, it aims at enabling robust and reliable communication between devices in applications such as home automation, smart metering, and industrial controls. This transceiver core is characterized by its excellent RF performance and energy efficiency, ensuring prolonged device operation with minimal power consumption. This IP core's architecture features advanced error correction and modulation schemes, bolstering performance even in environments with interference. It is engineered for ease of integration, ensuring that manufacturers can seamlessly incorporate it into their products, enabling rapid development cycles and time-to-market. Through its interoperability with other 802.15.4 devices, this transceiver facilitates the creation of extensive wireless network applications. Ideal for both consumer and industrial applications, it allows for flexible network configurations and robust data handling, making it a cornerstone for IoT development.
Secure Protocol Engines are high-performance IP blocks that focus on enhancing network and security processing capabilities in data centers. Designed to support secure communications, these engines provide fast SSL/TLS handshakes, MACsec and IPsec processing, ensuring secure data transmission across networks. They are particularly useful for offloading intensive tasks from central processing units, thereby improving overall system performance and efficiency. These engines cater to data centers and enterprises that demand high throughput and robust security measures.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
Designed to revolutionize AI-driven data centers, the Photowave Optical Communications Hardware capitalizes on the inherent advantages of photonics. With capabilities that support PCIe 5.0/6.0 and CXL 2.0/3.0, this hardware facilitates enhanced scalability of AI memory applications within data centers. The technology provides significant latency reduction and energy efficiency, allowing for more effective resource allocation across server racks, which is a crucial feature for modern data infrastructure. The Photowave hardware serves the evolving needs of data-driven applications, ensuring seamless integration and performance boosts in environments demanding high-speed data transfer and processing. By addressing the latency and power efficiency concerns prevalent in traditional electronics, it is integral in the transition towards faster, more sustainable data center operations. Incorporating these photonic advantages, Photowave stands as a testament to Lightelligence’s goal of transforming data operations and enhancing the utility of AI technologies. Its role in this ecosystem is vital, making it a cornerstone product for entities looking to modernize their computational frameworks.
The SPI Master/Slave Controller by Digital Blocks is a versatile Verilog IP core tailored for both master and slave Serial Peripheral Interface (SPI) bus communications. Designed to provide seamless integration, it supports various bus interfaces including AMBA AXI, AHB, and APB, connecting microprocessors to external devices through SPI master/slave interactions. Capable of handling Single, Dual, Quad, and Octal SPI Flash Memory devices, this controller offers enhanced functionality, including Execute-in-Place (XIP) operations for efficient use of flash memory within system designs. This makes it particularly advantageous for applications requiring in-situ code execution from the non-volatile memory, minimizing latency. Moreover, the SPI Master/Slave Controller is expandable to meet specific application requirements, maintaining compatibility with industry-standard specifications, and supporting a broad range of embedded system applications. Its adaptable design ensures users can configure this IP core to their specifications, optimizing performance and operational efficiency in multiple application domains.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 3.3V pads in the TSMC 3nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 3.3V interfaces. It features a small silicon footprint.
The UDP Offload Engine IP core from Atomic Rules is designed to boost application throughput across multiple 10/25/40/50/100/400 GbE Ethernet interfaces. It offloads UDP processing tasks from software to hardware, providing efficient data handling at remarkable speeds while ensuring compliance with the UDP/IPv4 standards. This engine implements checksum, segmentation, and reassembly functionalities in hardware, allowing developers to streamline operations without manually manipulating datagrams. It supports super-jumbo frames up to 16K bytes, enhancing data transfer rates significantly for demanding network applications. Designed to work seamlessly with the Internet Protocol suite, the UDP Offload Engine makes it possible to achieve exceptional data transfer rates and reduce the overhead associated with data handling in FPGA architectures. This optimization helps applications meet modern requirements for high-bandwidth communication without interrupting existing workflows.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 3.3V pads in the TSMC 7nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 3.3V interfaces. It features a small silicon footprint.
The I2C Master/Slave Controller IP Core crafted by Digital Blocks allows robust interfacing between microprocessors and the I2C bus. Designed for seamless integration into various systems, it supports a wide range of functions and data rates, including standard and higher-speed operations such as Fast-mode Plus and Hs-mode. This IP core offers complete compliance with the latest NXP I2C specifications, encompassing system-level features for advanced applications. Its architectural design simplifies the controller’s integration into SoC environments, supporting AMBA interconnects such as AXI, AHB, and APB, which enhances its adaptability and performance. Enhanced with features for improved system-level integration, it covers both master and slave operation modes, providing a comprehensive solution for device-to-device communication and data transactions in embedded systems. This adaptability makes it a valuable asset across various sectors needing reliable and efficient communication protocols.
LSI-TEC offers comprehensive certification technologies for MIFARE systems, a leading standard for contactless and contact smart card solutions. This technology provides an intricate framework for electronic transactions and data security, offering compatibility across various platforms and ensuring robust communication and authentication protocols. MIFARE technology is designed to enhance security and operational efficiency in numerous applications, including public transportation, access control, and identity verification systems. The solutions provided by LSI-TEC ensure that entities can seamlessly integrate MIFARE into their existing infrastructure, thus optimizing usability and reducing operational disruptions. Notably, LSI-TEC’s approach to MIFARE certification technology underscores its commitment to maintaining international standards of security and interoperability, thereby serving industries that require secure transaction and access solutions. Through technological enhancement and stringent testing, these certification technologies are tailored to support the high scalability needs of urban digital infrastructure developments.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 2.5V pads in the TSMC 5nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 2.5V interfaces. It features a small silicon footprint.
The BLE Wireless Sensor Network Library provides a framework for developing low-energy wireless sensor solutions, ideal for IoT applications. This library is designed to simplify the implementation of wireless sensor networks, ensuring energy efficiency and robust connectivity between devices. With support for a range of sensor types and configurations, this library facilitates the creation of bespoke sensor networks tailored to specific application needs. Its emphasis on low power consumption ensures prolonged operation of sensor devices, crucial for IoT deployments where battery life is a major consideration. Applications of the BLE library span diverse industries, from smart homes and healthcare to industrial automation and environmental monitoring. It provides developers with the resources needed to deploy efficient, scalable wireless networks capable of supporting various sensor-driven innovations.
The LineSpeed FLEX family consists of 100G PHY products that are engineered to support a wide spectrum of functions, including retiming, gearbox operations, multiplexing, and providing redundant links. This product line is crucial for applications found in line cards and modules, where diverse data rate support is essential for compatibility with industry standards like 10G, 25G, and 100G. With robust on-chip RS-FEC for both gearbox and retimer operations, the LineSpeed FLEX products are optimized for dense 10GbE aggregations and high-reliability environments. The versatile design of these products includes protocol-independent retimers, which allow for mixed port speeds and easy integration across various systems. Built with flexibility and scalability in mind, the LineSpeed FLEX family is adept at handling contemporary network challenges in high-performance contexts.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
EASii IC's CoaXPress IP stands out as a global leader in high-speed imaging data transmission used across professional and industrial imaging applications such as machine vision, medical imaging, and broadcasting. This IP leverages the simplicity of coaxial cabling combined with high-speed serial data transfer capabilities. CoaXPress provides a high-bandwidth, low-cost interface solution using coaxial cables for video acquisition peripherals. It supports high-speed data streams from multiple cameras with impressive GenICam compliance, endorsing a unified software interface for diverse camera types. EASii IC’s CoaXPress Device and Host IP cores are engineered to accommodate the latest standards, offering unparalleled integration for embedded systems. Designed with flexibility, CoaXPress IP includes dynamic device and link management, allowing it to seamlessly operate across multiple system configurations and supporting bidirectional, low-latency, high-precision communications. This versatility ensures its efficacy for large-scale, multistream video processing, capturing, and transmission requirements.
This networking solution from CetraC endows high-performance capabilities into FPGA and ASIC products, tailored for distributed architectural systems. It is crafted specifically for industries that demand high-speed data transmissions and excellent reliability across their networking infrastructures. The product supports numerous protocols such as TSN, CAN FD, and ARINC429, making it versatile for integration into various high-tech systems needing comprehensive data management and communication structures. The solution also features robust security measures including AES256 encryption to protect data integrity while facilitating seamless protocol conversions to enhance interoperability between various network segments.
The SPI Slave is a critical module designed for stable and efficient serial communication in systems that leverage the SPI protocol. Adhering to the Motorola reference standard, this slave device accommodates varying clock speeds and data bits, ensuring smooth and synchronized data exchanges. It's integral for electronic applications requiring consistent throughput and error management, often employed in consumer electronics and industrial equipment for its reliability and performance under diverse conditions.
The I2C Slave module complements the I2C Master by providing a robust interface for responding to master-driven commands using the I2C protocol. Fully aligned with I2C-bus specifications, this slave module handles data communication efficiently across different data modes—Standard, Fast, and Fast Plus. It facilitates seamless communication with minimal power consumption, making it a reliable choice for embedded systems, where multiple devices must communicate cohesively. Its adaptability contributes to efficient system integration across diverse electronic platforms.
The I2C Master core enables communication between integrated circuits using the I2C protocol. Compliant with the I2C-bus specification and user manual Rev. 5, it supports Standard-mode, Fast-mode, and Fast-mode Plus (Fm+) operations. This master module is capable of transmitting and receiving data efficiently, making it suitable for applications requiring control over multiple slave devices within electronic systems. It's widely used in consumer electronics and embedded systems where precise data coordination is crucial.
The LittleBee family of FPGAs is known for its flash-based non-volatile design, offering low power consumption and minimal package sizes, as small as 2.4x2.3mm. These FPGAs are particularly suited for I/O intensive applications, providing solutions for source synchronous interfacing and bridging in systems using protocols such as MIPI CSI-2, MIPI DSI, USB 2.0, Ethernet, and HDMI. These devices are tailored for hardware management applications due to their instant-on capability and built-in security functions. LittleBee FPGAs are further enhanced by features such as extended memory, hardened ARM Cortex-M processor cores, and Bluetooth Low Energy (LE), enriching their functionality and broadening their application scope compared to traditional FPGA offerings. Notably, the LittleBee series enhances its capabilities with an emphasis on quick boot sequences and robust security, making it suitable for applications spanning from consumer electronics to industrial applications requiring compact and efficient FPGA solutions.
The SPI Master core is designed to facilitate synchronous serial communication between various devices using the SPI protocol. It aligns with the SPI Standard and is fully compliant with Motorola's M68H11 Reference Manual. This core is ideal for controlling multiple slave devices, supporting bi-directional communication that is essential in high-speed data environments. It's a popular choice in embedded systems for applications that demand efficient, low-latency communication solutions.
This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
The Arora V series represents the second generation of the Arora FPGA family, boasting a rich array of internal resources. With a novel architecture and high-performance DSP blocks that support AI operations, these FPGAs also feature high-speed LVDS interfaces and ample BSRAM resources. Showcasing cutting-edge 22nm SRAM technology, these devices integrate high-speed SerDes interfaces ranging from 270 Mbps to 12.5 Gbps. Additionally, they include PCIe 2.1 hard cores supporting x1, x2, and x8 configurations, along with MIPI hard core modules reaching speeds of up to 2.5 Gbps. The FPGA is further equipped with DDR3 interfacing, capable of speeds up to 1333 Mbps. The initial offering, the GW5AT-138FC676, provides a robust configuration including 138K LUT logic resources, 6.4MB of block RAM, and 1.1MB of distributed SRAM, coupled with advanced DSP blocks and an integrated ADC. Future models will expand the range with devices offering 25K (non-Serdes) and 60K LUT options. Supported by GOWIN's EDA tool, these FPGAs create an efficient environment for FPGA hardware development, supporting multiple RTL programming languages, synthesis, placement and routing, bitstream generation and download, as well as power analysis and in-device logic analysis.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The 12~85MHz LVDS Rx from Leo LSI is designed to efficiently handle low voltage differential signaling across a broad frequency range. This receiver supports shift clock frequencies from 12 to 85MHz, making it versatile for various data communication needs while maintaining energy efficiency. It offers a common-mode range around +1.2V and a throughput capability of up to 2.38Gbps, paired with a bandwidth of 297.53Mbytes/sec. The design incorporates LVDS devices for low EMI environments and requires no external components, simplifying integration into existing systems. Optimized for high-speed data reception, this LVDS Rx is suitable for applications demanding robust signal integrity and minimal electromagnetic interference, such as in high-speed data transfer and multiplexing systems.
The I2S Controller is an essential component for audio data handling, offering seamless integration for digital audio processing applications. With its precision interface management, the controller is perfect for managing audio data streams in consumer electronics and professional audio equipment. Its versatility extends to a range of applications, ensuring high fidelity and low latency in audio processing tasks. This product supports various standards to ensure compatibility with a wide range of audio devices, making it indispensable for designers who seek robust audio handling capabilities. Its efficient interface allows for minimal design adjustments, enhancing product deployment speed for manufacturers and engineers alike. Designed to deliver optimal performance with minimal resource consumption, the I2S Controller is a testament to System Level Solutions' commitment to fostering innovation in audio technology. It balances the need for high-quality audio transmission with the practicality necessary for efficient implementation.
The Vulcan SoM is a flexible platform based on Versal Prime or AI Edge FPGA SoC modules, offering a blend of AI processing and advanced connectivity. It is designed for implementing complex algorithms across various embedded applications, promising enhanced performance with lower power usage. This module is optimized for sectors like bioscience instrumentation, radar systems, and quantum computing. The integrated heatsink and fan support makes it an ideal choice for high-demand environments.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
The Ares SoM utilizes the Agilex 7 SoC F-Series FPGA, combining high-performance and versatility. It is tailored for the rapid implementation of complex algorithms, ensuring optimal use in fields like electronic warfare and satellite communication. The system-on-module design enables it to be easily integrated into various systems, helping reduce development cycles and time-to-market for embedded solutions. The Ares SoM effectively supports applications that demand reliability and speed.
Based on the AMD Zynq Ultrascale+ MPSoC, the Zeus SoM merges ARM and FPGA capabilities to drive innovative designs across sectors such as radar and high-precision measurement systems. With multiprocessing capabilities, the Zeus SoM enables the concurrent execution of complex tasks, enhancing system efficiency. The board's compatibility with its carrier board allows for a streamlined development process, targeting markets demanding robust and scalable solutions.
The COMXpress SoM leverages Intel's Stratix 10 SoC technology to deliver high-performance computing in a compact form. Designed for applications that require intensive processing and high transceiver bandwidth, this module is ideal for markets such as HPC and video processing. Its architecture allows for customizable integration, supporting development in both industrial and embedded sectors.
Achilles SoM is developed with the Intel Arria 10 SoC, offering an efficient blend of CPU control and FPGA programming flexibility. It is crafted to support high-power applications, including automotive and military systems, where quick processing and adaptability are crucial. The Achilles SoM significantly reduces time-to-market by integrating essential components into a compact board design, making it ideal for diverse industrial uses.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology. The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter. The library also includes a 1.2V ODIO with two slew rate options as well as a 3.3V ODIO with a 5V tolerance. All I/Os have highly programmable POC options and active pull up/down. The library is compliant with ANSI/JEDEC/ESDA JS-001-2014 ESD standards.
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