All IPs > Interface Controller & PHY > I2C
The I2C Interface Controller & PHY category in our semiconductor IP catalog presents a crucial array of technologies tailored for seamless communication within embedded systems and a variety of electronic devices. The I2C, or Inter-Integrated Circuit, standard is a well-established protocol that facilitates serial communication, primarily in microcontrollers and other integrated circuits. Within this category, developers will find both controller IPs and Physical Layer (PHY) IPs designed to optimize the efficiency and functionality of I2C communications.
The products in this category include comprehensive controller IP cores that manage the I2C protocol, enabling devices to communicate over a shared bus efficiently. These controllers are essential components for systems requiring robust data exchange, such as sensor networks, home automation systems, and industrial control environments. Leveraging these IP cores can lead to significant reductions in design time, providing developers with a ready-to-use solution that adheres to standard I2C specifications while offering flexibility for customization.
PHY semiconductor IPs are crucial for ensuring the physical transmission of I2C data complies with electronic standards needed in various environments. They handle critical functions such as signal transmission, clock generation, and power management, thereby ensuring that data integrity is maintained across different system components and operating conditions. These IPs are particularly vital for applications that demand high reliability and performance in their I2C communications, such as automotive electronics, consumer devices, and medical equipment.
Integrating I2C Interface Controller & PHY semiconductor IPs can considerably enhance the performance of multi-device systems, offering scalable solutions that adapt to the increasing complexity of modern electronic configurations. By focusing on high efficiency and compatibility, these IPs support the development of innovative products that require reliable and efficient communication protocols, paving the way for advancements in technology and connectivity across industries.
The AHB-Lite APB4 Bridge serves as a crucial interconnect that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility and adaptability in managing system interconnections, bridging the gap between high-speed and low-speed peripherals with efficiency. The bridge's architecture is designed to maintain data integrity while transferring information across different protocol tiers. This bridge supports the implementation of a seamless transition for data exchanges, ensuring data packets are transmitted with minimal latency. It is ideal for systems that require stable connectivity across multiple peripheral interfaces, delivering a cohesive platform for system designers to enhance operational uniformity. By enabling efficient bus conversion, it supports broader system architectures, contributing to the overall efficiency of embedded designs. With its open-architecture design, the AHB-Lite APB4 Bridge caters to a wide range of applications, providing necessary adaptability to meet the unique demands of each project. Its robust design ensures that it can accommodate the complex architectures of modern embedded systems, enhancing both performance and reliability.
Great River Technology offers the ARINC 818 Product Suite, a comprehensive collection of tools and products designed to cover the full spectrum of ARINC 818 applications. This suite is pivotal for engineers and designers who are focused on the aviation sector, providing solutions necessary for the creation, testing, and deployment of high-speed digital interfaces in avionics. The suite supports design and implementation phases by offering robust support tools tailored for ARINC 818 development, including detailed implementers' guides and simulation resources. What's unique about this suite is its ability to facilitate process integrations for ARINC 818 standards across various platforms, making it adaptable for differing needs in aviation systems. The integration tools provided ensure that systems can efficiently manage data and video transmissions, providing clarity, speed, and reliability, all essential factors in mission-critical environments. Great River Technology’s ARINC 818 Product Suite is engineered to ensure seamless interoperability, offering support from initial project development through to practical operation, thus enabling avionic systems to function optimally in both standard and specialized conditions.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
The C100 IoT chip by Chipchain is engineered to meet the diverse needs of modern IoT applications. It integrates a powerful 32-bit RISC-V CPU capable of reaching speeds up to 1.5GHz, with built-in RAM and ROM to facilitate efficient data processing and computational capabilities. This sophisticated single-chip solution is known for its low power consumption, making it ideal for a variety of IoT devices. This chip supports seamless connectivity through embedded Wi-Fi and multiple transmission interfaces, allowing it to serve broad application areas with minimal configuration complexity. Additionally, it boasts integrated ADCs, LDOs, and temperature sensors, offering a comprehensive toolkit for developers looking to innovate across fields like security, healthcare, and smart home technology. Notably, the C100 simplifies the development process with its high level of integration and performance. It stands as a testament to Chipchain's commitment to providing reliable, high-performance solutions for the rapidly evolving IoT landscape. The chip's design focuses on ensuring stability and security, which are critical in IoT installations.
LightningBlu is a cutting-edge solution provided by Blu Wireless, designed specifically to serve the high-speed rail industry. This technology offers consistent, on-the-move multi-gigabit connectivity between trackside and train, which ensures a reliable provision of on-board services. These services include seamless internet access, enhanced entertainment options, and real-time information, creating a superior passenger experience while traveling. Utilizing mmWave technology, LightningBlu is capable of offering carrier-grade performance, supporting Mobility applications with remarkable consistency even at speeds exceeding 300 km/h. Such capabilities promise to revolutionize the connectivity standards within the high-speed rail networks. By integrating this advanced system, railway operators can ensure uninterrupted communication channels, thus optimizing their operations and boosting passenger satisfaction. The solution primarily operates within the mmWave spectrum of 57-71 GHz, making it a future-proof choice that aligns with the expanding global demand for high-quality, high-speed railway communications. With LightningBlu, Blu Wireless is spearheading the movement towards carbon-free, robust connectivity solutions, setting a new standard in the transportation sector.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The RISCV SoC - Quad Core Server Class is engineered for high-performance applications requiring robust processing capabilities. Designed around the RISC-V architecture, this SoC integrates four cores to offer substantial computing power. It's ideal for server-class operations, providing both performance efficiency and scalability. The RISCV architecture allows for open-source compatibility and flexible customization, making it an excellent choice for users who demand both power and adaptability. This SoC is engineered to handle demanding workloads efficiently, making it suitable for various server applications.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 3.3V pads in the TSMC 3nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 3.3V interfaces. It features a small silicon footprint.
The eSPI Master/Slave Controller by Digital Blocks is adept at handling multiple SPI and eSPI protocols. Compatible with existing AMBA interfaces such as AXI and AHB, this controller can switch roles between master and slave, catering to versatile communication requirements. It is structured to support efficient data exchange over the serial interface, with considerations for execution in place (XIP) functionalities extending its utility in flash memory interactions.
The APB4 GPIO core from Roa Logic is a fully parameterized solution designed to provide a customizable number of general-purpose, bidirectional I/O pins. This core enables developers to define the I/O behavior precisely, adapting to a plethora of configurations to meet specific project requirements. It is essential for applications that require extensive interfacing capabilities, ensuring streamlined connectivity across multiple components. The GPIO core supports a range of operational modes, providing the flexibility to handle complex I/O operations. With capabilities like programmable drive strength and individual pin configuration, it offers a high degree of customization that can be tailored to precise application needs. Roa Logic’s offering enhances design functionality and accelerates development timelines by facilitating easy integration and application-specific optimization. This component serves as a cornerstone for designs requiring robust peripheral interaction, catering to both industrial projects and educational purposes. Its adaptability and ease of integration ensure it's an invaluable component in modern electronics design, adhering to the high standards expected in today's interconnected environments.
The SPI Master/Slave Controller is engineered for efficient serial communication, offering integration with AMBA protocols for seamless connectivity to SPI-compatible devices. This controller is capable of both master and slave operations, ensuring flexible deployment across different systems. With the capability to execute transfers from microprocessor platforms to SPI devices, it offers a compact solution with significant off-loading capabilities for processor-based operations.
Designed for the burgeoning field of wireless connectivity, the 802.15.4 Transceiver Core from RF Integration is targeted towards low-rate wireless personal area networks (LR-WPANs). This core provides the backbone for connecting devices in home automation, industrial monitoring, and consumer electronics applications. Capable of supporting IEEE 802.15.4 standards, including Zigbee, the core facilitates low-power data communication, which is essential for devices where energy efficiency is paramount. The transceiver's design emphasizes reduced power consumption while maintaining robust wireless communication, making it an ideal choice for battery-powered devices. The flexibility of this core allows it to be integrated with various systems, enhancing the functionality of networked devices through secure and reliable connections. By leveraging RF Integration's expertise, this transceiver core not only meets the demand for energy-efficient solutions but also paves the way for future advancements in the Internet of Things (IoT).
The UDP Offload Engine is an advanced FPGA IP Core tailored for high-speed communication needs, supporting a wide spectrum of Ethernet speeds ranging from 10 GbE to 400 GbE. It efficiently manages the UDP protocol stack offloading UDP operations from software to hardware, which significantly enhances data throughput and minimizes processor utilization. This IP core adheres to established UDP/IPv4 standards, incorporating advanced features like checksum computation, segmentation, reassembly, and L4 UDP multicast pre-selection, making it exceptionally suitable for high-performance network environments where efficiency and reliability are paramount. Its compatibility with industry-standard Ethernet MACs facilitates seamless integration into existing network architectures. Designed to support Super-Jumbo Frames and featuring an arbitrary datagram PDU limit up to 64K Bytes, the UDP Offload Engine delivers a robust solution for network and communication applications, prominently reducing overhead and providing swift yet reliable data transfer capabilities beneficial for modern networking tasks.
The Secure Protocol Engines by Secure-IC are designed to offload and enhance network and security processing tasks within an SoC environment. These high-performance IP blocks ensure efficient management of cryptographic operations and facilitate secure data exchanges across networks. By integrating these engines, developers can achieve improved throughput and reduced latency in their security implementations, which is critical for maintaining the performance and safety of connected devices. These engines support standard protocols, ensuring compatibility with a wide range of applications.
Photowave optical communications hardware is engineered to support disaggregated AI memory applications that require seamless integration and scalability across PCI Express (PCIe) 5.0/6.0 and Compute Express Link (CXL) 2.0/3.0 standards. It optimizes both latency and energy efficiency, essential for modern data centers. The Photowave technology leverages the inherent advantages of photonics to allow for significantly lower latencies compared to traditional electronic counterparts, enabling faster data transmission and processing speeds. Photowave is particularly beneficial for data center management, allowing administrators to dynamically scale resources efficiently, whether it be within individual server racks or across multiple racks. This adaptability is crucial for environments that require high compute performance and low latency communication between various AI components. The technology's innovation lies in its ability to maintain performance while reducing energy consumption, offering a sustainable solution in line with the growing demand for energy-efficient technologies. This positions Photowave as a key player in enhancing the infrastructure of AI-driven applications.
This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
FireCore provides a robust solution integrating both PHY and Link layers, necessary for high-performance IEEE-1394 and AS5643 applications. Supporting transmission speeds up to S3200, it leverages precise timing controls and enhanced data encapsulation features. This IP core ensures compatibility with existing systems, enabling easy upgrades from older implementations. Its design allows for flexible configurations tailored to specific system needs, making it suitable for deployment in complex avionics environments.
The FireSpy Bus Analyzer line by DapTechnology offers a comprehensive range of tools designed for the analysis of IEEE-1394 and AS5643 protocols. They form the backbone of many aerospace and defense programs, ensuring accurate simulation and debugging with protocol decoding, timing analysis, and more. FireSpys are invaluable from early design studies and technology evaluations to system development and aircraft checkouts, handling up to nine-bus configurations for thorough monitoring and analysis across multiple application phases.
Serving as a counterpart to the INAP375T, the INAP375R receives high-speed data over a single cable with similar capabilities. This receiver can handle video and audio data without errors, owing to its implementation of the error-correction protocol AShell. It supports flexible connectivity options, adapting to different video interfaces and data configurations required in modern infotainment systems within cars. The robust design ensures compatibility with older APIX devices, thereby delivering seamless integration in automotive communication networks.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 3.3V pads in the TSMC 7nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 3.3V interfaces. It features a small silicon footprint.
Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The Analog I/O clamp described in this document can be used for 2.5V pads in the TSMC 5nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 2.5V interfaces. It features a small silicon footprint.
Designed for versatility in high-speed networking, the LineSpeed FLEX Family encompasses 100G PHY products adept at multiple roles including retiming, gearboxing, and multiplexing. Regarded for supporting modulation-independent functionality across line cards, these devices integrate easily with existing infrastructure to facilitate seamless telecom and data-center environments. By adopting common register and packaging structures, they simplify deployment while ensuring adherence to industry standards. These products enable high-performance routing and redundant link setups, meeting the demands of modern network requirements with RS-FEC supported Gearbox and Retimer options.
The RegSpec tool is a sophisticated register specification utility designed to streamline the specification and implementation of register architecture. Typically utilized in the automation of CSR (Control Status Register) generation, RegSpec enhances workflow efficiency by providing an intuitive interface for managing and generating register files. This tool aids engineers in defining precise and compliant registers, crucial for a variety of development projects. By facilitating accurate implementation of register definitions, RegSpec supports consistent architecture specifications, thereby reducing development time and errors.
The I2C Master/Slave Controller from Digital Blocks provides robust interfacing solutions via AMBA bus systems, managing complex communication between microprocessors and I2C bus components. It supports standard, fast-mode, and high-speed protocols, ensuring responsiveness to modern I2C connectivity requirements. This controller is integral to systems needing reliable communication in both high-speed and power-efficient environments.
MosChip delivers a comprehensive suite of Digital IP Solutions designed to enhance the electronic design automation processes for developers and manufacturers. This range of digital IPs is engineered to facilitate the rapid deployment of robust and efficient electronic systems, serving an array of industries, including telecommunications, consumer electronics, and automotive. Digital IP Solutions offered by MosChip encompass a broad spectrum of functionalities, including data processing, communication protocols, and system management features. Each digital module is crafted to optimize performance, power consumption, and integration within larger systems, ensuring that products can be brought to market with both speed and efficiency. These solutions are further supported by MosChip's extensive design and verification processes, which ensure that each IP core meets stringent quality and performance standards. This commitment provides confidence to manufacturers that their products will deliver reliable results and maintain compatibility across various environments and applications.
The MIPI Solutions developed by LTTS are crafted to optimize the collaborative functionality between mobile components, adhering to the stringent MIPI standards. These solutions are essential for the efficient integration of various mobile components, ensuring that devices operate at peak performance without compromising on quality or speed. The technology addresses compatibility and integration challenges, facilitating seamless communication within mobile architecture.\n\nBy leveraging MIPI solutions, mobile manufacturers can ensure their devices are capable of supporting a diverse range of applications, without overloading the system or impacting battery life negatively. These solutions are also designed to handle high data rates, ensuring fluidity in operation, which is crucial for advanced functions such as high-resolution video playback or real-time data processing.\n\nLTTS's commitment to compliance with MIPI standards assures users of a robust system-level optimization, which is critical as mobile technologies incorporate more capabilities. The solutions are designed to accommodate future enhancements, ensuring longevity and adaptability as new technologies emerge. This dedication to innovation and standard compliance makes LTTS's MIPI solutions a reliable choice for manufacturers aiming to advance their mobile technology platforms.
Developed to cater to modern mobile and IoT applications, Silvaco's I3C IP solutions bring together advanced controllers and targets compliant with the MIPI standard. Supporting both standard and basic configurations, these solutions enhance data communication and flexibility in complex systems.
The Bluetooth Low Energy (BLE) Wireless Sensor Network Library is a versatile suite enabling the rapid deployment and management of sensor networks across various applications. This library leverages BLE technology to maximize energy efficiency and extend the lifespan of sensor networks, making it ideal for IoT applications. The library offers robust connectivity and supports a wide range of devices, facilitating seamless integration into existing IoT ecosystems. It provides developers with the tools necessary to build custom applications, from smart homes to health monitoring systems, enhancing the versatility and functionality of BLE networks. In the age of connectivity, the BLE Wireless Sensor Network Library from EDI stands out due to its flexibility and user-friendliness. It enables innovators to prototype solutions swiftly while ensuring that network deployment scales to meet evolving demands. Its energy-conscious design is crucial for minimizing operational costs and environmental impact in consumer and industrial applications alike.
CetraC.io's High-Performance FPGA & ASIC Networking Product is designed to offer unparalleled performance in distributed network architectures. Built on the foundation of hardware acceleration, it simplifies network design by embedding complex networking functionalities directly into ASICs and FPGAs. These products are optimized for high-bandwidth operations and ensure consistent network reliability. Utilizing advanced finite state machine technology, CetraC.io provides a solution that dramatically enhances data throughput and minimizes latency in data transmissions. With an ability to handle multiple data streams concurrently, networks using these products can efficiently process and manage large volumes of data, crucial for real-time operations in sectors like aerospace and defense. This networking product supports a broad array of protocols, ensuring seamless integration within existing systems while maintaining security and data integrity. Designed with high efficiency in mind, it reduces the overhead typically associated with software-based networking solutions, leading to improvements in energy consumption and overall system performance. CetraC.io's networking product is ideal for applications requiring robust data processing, such as those found in mission-critical environments. Its inherent support for future-ready networking standards positions it well within industries demanding cutting-edge technology with scalable features for expanding network demands.
The SPI Slave IP Core complies with the SPI Standard as detailed in Motorola’s M68H11 Reference Manual, ensuring seamless slave-directed operations in Serial Peripheral Interface (SPI) communications. By excelling in handling serial data exchanges, it supports efficient communications in a broad range of applications. This core facilitates synchronization of data transfer between the master and multiple slave devices in SPI configurations, enhancing the interoperability and functionality of electronic systems. It is crafted to ensure that data transactions are handled with high precision, crucial for systems demanding accurate data exchange protocols. With an architecture designed for flexibility, the SPI Slave core is suitable for deployment in various industrial and consumer applications. It offers a reliable interface for devices requiring effective communication pathways, bolstering system capabilities and ensuring robust data handling processes.
The I2C Slave IP Core aligns with the I2C-bus specification and user manual Rev. 5, released on October 9, 2012. It is crafted to function as a slave device in inter-integrated circuit setups, ensuring compliance across multiple bus modes, including Standard-mode, Fast-mode, and Fast-mode Plus (Fm+). This core is crucial for simplifying the integration of slave devices within the I2C protocol, maintaining effective communication across system components. It supports efficient data transactions between microcontrollers and peripheral devices, acting as a conduit for reliable information flow. The I2C Slave core's design flexibility makes it suitable for a variety of applications where device-to-device communication is fundamental. It supports widespread industrial and consumer devices, ensuring integrative harmony within complex digital systems, and providing a proven solution for communication challenges in electronic applications.
EASii IC's CoaXPress IP stands out as a global leader in high-speed imaging data transmission used across professional and industrial imaging applications such as machine vision, medical imaging, and broadcasting. This IP leverages the simplicity of coaxial cabling combined with high-speed serial data transfer capabilities. CoaXPress provides a high-bandwidth, low-cost interface solution using coaxial cables for video acquisition peripherals. It supports high-speed data streams from multiple cameras with impressive GenICam compliance, endorsing a unified software interface for diverse camera types. EASii IC’s CoaXPress Device and Host IP cores are engineered to accommodate the latest standards, offering unparalleled integration for embedded systems. Designed with flexibility, CoaXPress IP includes dynamic device and link management, allowing it to seamlessly operate across multiple system configurations and supporting bidirectional, low-latency, high-precision communications. This versatility ensures its efficacy for large-scale, multistream video processing, capturing, and transmission requirements.
The INAP375T is a feature-rich transmitter designed for high-speed differential data transmission. It uses APIX2 technology, enabling efficient data transfer over a single twisted pair (STP) cable at speeds up to 3Gbps. This transmitter supports flexible frame configurations filled with video, audio, and data, adaptable to various automotive applications. The device incorporates advanced protocols such as AShell for safety-critical data transmission and offers backward compatibility with previous APIX versions, making it versatile for integrated into existing and new systems.
The I2C Master IP Core fully complies with the I2C-bus specification and user manual Rev. 5, dated October 9, 2012, supporting Standard-mode, Fast-mode, and Fast-mode Plus (Fm+). This core is integral for master-side control in inter-integrated circuit communications, providing a reliable protocol option for synchronous data transfer across microcontrollers and related components. Designed for flexibility and performance, the I2C Master enables efficient communication across multiple devices on the same bus, supporting various speed modes to accommodate different operational requirements. Its efficient design ensures seamless integration into existing systems, enhancing productivity and simplifying development. The adaptable nature of this IP allows for extensive customization, making it applicable across a wide spectrum of industrial and consumer electronics applications where reliable communication is essential. This core's robustness ensures dependable data exchanges, critical in environments with tightly coordinated communication needs.
The SPI Master IP Core adheres to the SPI Standard, as outlined in Motorola’s M68H11 Reference Manual. It functions to facilitate master-directed control in Serial Peripheral Interface (SPI) communications, essential for microcontroller interactions with peripheral devices. This core enables efficient serial data exchange by configuring electronic components for synchronous data transfer in a master-slave setup, making it indispensable in systems that require precise and rapid serial communication. Its robust architecture supports a wide variety of applications, enhancing system functionality and data integrity. Designed to operate seamlessly within various electronic environments, the SPI Master core provides the ability to execute high-speed data transactions, maintaining effective control over peripheral devices. Its customizable nature allows for tailored implementations to meet specific requirements of both industrial and consumer technology applications.
The I2C Master/Slave Controller Core simplifies data transfer over two-wire serial buses, supporting both master and slave operational modes. Designed for simplicity and efficiency, this controller provides flexible system integration via various bus interfaces and ensures robust communication through features like multi-master arbitration and clock synchronization. With its compatibility with standard I2C specifications, it adapts to a wide range of embedded systems, supporting data transfer speeds from 100 Kbps up to 400 Kbps. This IP core is ideally suited for consumer electronics and industrial automation systems.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
FireLink GPLink is engineered for integrating generalized protocol links into AS5643 and IEEE-1394 systems. It provides the adaptability necessary for varied communication architectures, ensuring robust support for diverse aviation interfaces. This capability allows for intricate data handling and enhanced synchronization, establishing itself as an essential tool for complex protocol management in aviation communication systems.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
FireCore GPLink adds generalized protocol link capabilities that extend the IEEE-1394 and AS5643 usage in diverse applications. Support for additional bus architectures allows FireCore GPLink to seamlessly integrate with complex communication systems, providing a versatile platform for vehicle management computers and other critical systems in aviation. With comprehensive data management, it enhances overall communication reliability and system effectiveness.
Enabling smooth inter-chip communication, the logiSPI controller bridge connects microcontrollers with AMD FPGAs and Zynq 7000 SoCs using the Serial Peripheral Interface (SPI) bus. It facilitates efficient data exchange at the board level, proving essential for designs that necessitate robust interfacing of multiple chip components.
Enhanced for flexibility and scalability, FireCore Extended builds on the core functionality to offer superior performance in demanding applications. It supports additional interfaces and control functions, optimizing resource management and increasing data throughput. It's engineered for applications that require intricate simulation and verification processes, thus making it indispensable in both development and operational environments within aerospace and defense sectors.
The FireGate solution by DapTechnology represents a leap forward in bus speed capabilities, targeting applications previously limited by off-the-shelf S800 speeds. Designed to meet the stringent demands of modern imaging and aerospace industries, it supports S1600 and S3200 transmission without compromising on data integrity or system performance. FireGate enables a new level of high-speed data processing and analysis, reaffirming DapTechnology's commitment to pioneering in high-performance systems and integrations.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
The I3C Host/Device Dual Role Controller IP by Arasan offers flexibility and efficiency in managing both master and slave configurations in device communication. Compliant with the latest I3C specifications, this IP facilitates data exchanges in smart devices with reduced complexity and power consumption. It is particularly effective in applications requiring systematic inter-device communication, such as IoT and mobile systems, where balanced performance and low power draw are priorities.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
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