All IPs > Graphic & Peripheral > Peripheral Controller
Peripheral Controller semiconductor IPs play a crucial role in the seamless integration of peripherals with core processing units, enhancing the functionality and connectivity of various electronic devices. These IPs are designed to manage the communication between the central processing unit (CPU) and external devices such as keyboards, mice, printers, and other peripherals. By enabling efficient data transfer and control signals between components, Peripheral Controller IPs ensure that systems operate smoothly and efficiently.
A key application of Peripheral Controller semiconductor IPs is in consumer electronics, where they facilitate the connection of tablets, smartphones, and laptops to a multitude of accessories and networks. For example, Universal Serial Bus (USB) controllers, memory card readers, and audio interfaces are just a few of the peripherals that these IPs manage. This allows end-users to transfer data quickly, connect various devices seamlessly, and enjoy a more versatile computing experience.
In industrial and automotive sectors, Peripheral Controller IPs are vital for maintaining robust and reliable communication within complex electronic systems. They are used to interface with sensors, actuators, and other control systems, ensuring that necessary data is transmitted accurately and in real-time. This is critical for applications that require precise timing and synchronization, such as automated manufacturing systems, smart grids, and advanced driver-assistance systems (ADAS).
Moreover, the evolution of Internet of Things (IoT) devices has further expanded the importance of Peripheral Controller IPs. As IoT ecosystems continue to grow, the need for efficient data management and connectivity solutions becomes more prominent. Peripheral Controller IPs offer the adaptability and scalability required to support a wide array of IoT applications, ensuring that devices can connect, communicate, and interact with each other effectively in both personal and industrial settings.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features: Supports UCIe 1.0 Specification Supports CXL 2.0 and CXL 3.0 Specifications Supports PCIe Gen6 Specification Supports PCIe Gen5 and older versions of PCIe specifications Supports single and two-stack modules Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers Supports CXL 3.0 256Byte flit mode Supports PCIe Gen6 flit mode Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules Supports sideband and Mainband signals Supports Lane repair handling Data to clock point training and eye width sweep support from transmitter and receiver ends UCIe controller can work as Downstream or Upstream Main Band Lane reversal supported Dynamic sense of normal and redundant clock and data lines activation UCIe enumeration through DVSEC Error logging and reporting supported Error injection supported through Register programming RDI/FDI PM entry, Exit, Abort flows supported Dynamic clock gang at adapter supported Configurable Options: Maximum link width (x1, x2, x4, x8, x16) MPS (128B to 4KB) MRRS (128B to 4KB) Transmit retry/Receive buffer size Number of Virtual Channels L1 PM substate support Optional Capability Features can be Configured Number of PF/VFDMA configurable Options AXI MAX payload size Variations Multiple CPI Interfaces (Configurable) Cache/memory configurable Type 0/1/2 device configurable
The LVDS IP from Sunplus is optimized for high-speed differential signaling, perfect for video, graphics, and other data-intensive applications. It offers robust performance with low electromagnetic interference, providing a reliable data communication channel. This IP is tailored for integration into systems that require efficient long-distance data transfer with minimal signal degradation.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features: Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0 Support for Single master and multiple slaves per interface port Single Data Rate (SDR) and Double Data Rate (DDR) support Source synchronous clocking Deep Power Down (DPD) enter and exit commands Eight IO ports in standard, expandable based on system requirements Optional Data Strobe (DS) for write masking bit wide SDR transfer support Profile 1.0 Commands for non-volatile memory device management Profile 2.0 Commands for read or write data for various slave devices Applications: Consumer Electronics Defense & Aerospace Virtual Reality Augmented Reality Medical Biometrics Automotive Devices Sensor Devices
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications: Supports PCIe Gen 6 and Pipe 5.X Specifications Core supports Flit and non-Flit Mode Lane Configurations: X16, X8, X4, X2, X1 AXI MM and Streaming supported Supports Gen1 to Gen6 modes Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s PAM support when operating at 64GT/s Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b Supports SerDes and non-SerDes architecture Optional DMA support as plugin module Support for alternate negotiation protocol Can operate as an endpoint or root complex Lane polarity control through register Lane de-skew supported Support for L1 states and L0P Support for SKP OS add/removal and SRIS mode No equalization support through configuration Deemphasis negotiation support at 5GT/s Supports EI inferences in all modes Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features: CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X PCIe Compatibility: Supports PCIe spec 6.0/5.0 CPI Interface: Support for CPI Interface AXI Interface: Configurable AXI master, AXI slave Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16 Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode Register Checks: Configuration and Memory Mapped registers Dual Mode: Supports Dual Mode operation Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers CXL Support: Can function as both CXL host and device Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized) Power Management: Supports Power Management features Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD Testing: Compliance Testing and Error Scenarios support
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
iWave Global delivers the Serial FPDP (sFPDP) solution, a high-bandwidth, low-latency serial communication protocol widely deployed in high-performance computing systems. This technology is optimized for applications that require rapid data transport, such as radar and high-definition video processing, making it a vital tool in industrial and defense sectors. By supporting high throughput rates, the Serial FPDP ensures timely and reliable data transmission, crucial for systems where time sensitivity and data integrity are paramount. The solution is particularly designed to address real-time data operations, ensuring that data handling meets rigorous industry standards. With its robust design, the Serial FPDP accommodates various network topologies, allowing for the flexible deployment of communication systems. This flexibility and performance make it highly applicable in environments where system designers demand unobstructed high-speed data transfer capabilities.
The KL530 represents a significant advancement in AI chip technology with a new NPU architecture optimized for both INT4 precision and transformer networks. This SOC is engineered to provide high processing efficiency and low power consumption, making it suitable for AIoT applications and other innovative scenarios. It features an ARM Cortex M4 CPU designed for low-power operation and offers a robust computational power of up to 1 TOPS. The chip's ISP enhances image quality, while its codec ensures efficient multimedia compression. Notably, the chip's cold start time is under 500 ms with an average power draw of less than 500 mW, establishing it as a leader in energy efficiency.
The ARINC 818-3 IP Core from iWave Global represents an advancement in avionics video interface technology, designed for high-speed and high-fidelity video data transmission. This IP core addresses the needs of modern aerospace systems that require robust video communication links both for military and commercial use. It supports a wide array of enhancements over previous generations, including increased bandwidth and improved signal integrity. This ensures that the ARINC 818-3 IP Core can handle the demands of next-generation avionic systems seamlessly, supporting advanced video processing and display systems. The core's design prioritizes modularity and scalability, allowing for easy integration and expansion to meet evolving system requirements. It is positioned as an essential tool for aviation applications demanding high reliability and accuracy in video data handling and display solutions, making it indispensable for new and retrofitted aerospace projects.
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The pPLL03F-GF22FDX is a sophisticated all-digital fractional-N PLL optimized for performance computing applications using GlobalFoundries 22FDX technology. This PLL is engineered for environments with rigorous timing requirements, offering low jitter performance of less than 10 picoseconds RMS at operational frequencies as high as 4GHz. Compact and power-efficient, it typically occupies less than 0.01 square millimeters and consumes under 5 milliwatts of power. The architecture of the pPLL03F-GF22FDX is built on Perceptia's advanced second-generation digital PLL technology, which provides consistent performance across various processes, regardless of PVT conditions. This design is particularly well-suited to applications where multiple clock domains are present, each controlled by its dedicated PLL, thanks to integrated power supply regulation that simplifies system design and power sharing. Integration into complex SoC designs is seamless, supported by comprehensive deliverables that include models and views necessary for modern backend design flows. The adaptable nature of this PLL allows it to be configured as either an integer-N or fractional-N PLL, offering flexibility in aligning system-level input and output clock frequencies. Clients are also offered extensive customization and integration support, ensuring optimal fit and functionality in diverse applications.
The Mixed-Signal CODEC offered by Archband Labs integrates advanced analog and digital audio processing to deliver superior sound quality. Designed for a variety of applications such as portable audio devices, automotive systems, and entertainment systems, this CODEC provides efficiency and high performance. With cutting-edge technologies, it handles complex signal conversions with minimal power consumption. This CODEC supports numerous interface standards, making it a versatile component in numerous audio architectures. It's engineered to offer precise sound reproduction and maintains audio fidelity across all use cases. The integrated components within the CODEC streamline design processes and reduce the complexity of audio system implementations. Furthermore, the Mixed-Signal CODEC incorporates features that support high-resolution audio, ensuring compatibility with high-definition sound systems. It's an ideal choice for engineers looking for a reliable and comprehensive audio processing solution.
Bluespec's Portable RISC-V Cores are designed to bring flexibility and extended functionality to FPGA platforms such as Achronix, Xilinx, Lattice, and Microsemi. They offer support for operating systems like Linux and FreeRTOS, making them versatile for various applications. These cores are accompanied by standard open-source development tools, which facilitate seamless integration and development processes. By utilizing these tools, developers can modify and enhance the cores to suit their specific needs, ensuring a custom fit for their projects. The portable cores are an excellent choice for developers looking to deploy RISC-V architecture across different FPGA platforms without being tied down to proprietary solutions. With Bluespec's focus on open-source, users can experience freedom in innovation and development without sacrificing performance or compatibility.
aiSim 5 represents a pivotal advancement in the simulation of automated driving systems, facilitating realistic and efficient validation of ADAS and autonomous driving components. Designed to exceed conventional expectations, aiSim 5 combines high-fidelity sensor and environment simulation with an AI-based digital twin concept to deliver unparalleled simulation accuracy and realism. It is the first simulator to be certified at ISO 26262 ASIL-D level, offering users the utmost industry trust.\n\nThe simulated environments are rooted in physics-based sensor data and cover a wide spectrum of operational design domains, including urban areas and highways. This ensures the simulation tests AD systems under diverse and challenging conditions, such as adverse weather events. aiSim 5's modular architecture supports easy integration with existing systems, leveraging open APIs to ensure seamless incorporation into various testing and continuous integration pipelines.\n\nNotably, aiSim 5 incorporates aiFab's domain randomization to create extensive synthetic data, mirroring real-world variances. This feature assists in identifying edge cases, allowing developers to test system responsiveness in rare but critical scenarios. By turning the spotlight on multi-sensor simulation and synthetic data generation, aiSim 5 acts as a powerful tool to accelerate the development lifecycle of ADAS and AD technologies, fostering innovation and development efficiency.\n\nThrough its intuitive graphical interface, aiSim 5 democratizes access to high-performance simulations, supporting operating systems like Microsoft Windows and Linux Ubuntu. This flexibility, coupled with the tool’s compatibility with numerous standards such as OpenSCENARIO and FMI, makes aiSim an essential component for automotive simulation projects striving for precision and agility.
The DisplayPort/eDP by Silicon Library is designed to provide high-performance interfaces capable of delivering exceptional video clarity and fidelity. Supporting DisplayPort 1.4 standards, this module is ideal for high-resolution displays, ensuring sharp and fluid visual output. This IP ensures seamless data transfer for video signals with high bandwidth efficiency, making it extremely suitable for advanced multimedia applications. It supports a range of resolutions, including Ultra HD, and facilitates excellent color depth and dynamic range in visual displays. Silicon Library's DisplayPort/eDP module offers exceptional flexibility in integration across a plethora of consumer electronic devices, enhancing their visual performance. With features optimized for energy efficiency and reduced latency, this product is perfect for modern applications that demand the pinnacle of video output technology.
MajEQ Pro is an advanced equalizer tailored for professional audio applications, allowing both static and dynamic EQ adjustments to match specific frequency response targets. It handles tasks such as venue correction or adapting to atmospheric changes at live events. This tool encompasses features including high and low-pass filters with variable slopes, tone controls, and unique filter designs such as Bell or Presence filters with customizable gain, frequency, and Q.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
The DB9000AXI Display Controller by Digital Blocks is engineered to meet the needs of systems using TFT LCD and OLED display panels, providing dynamic resolution support from 320x240 to 1920x1080 at Full HD. It integrates seamlessly into systems with AMBA AXI4 interfacing, providing reliable connectivity between frame buffer memory and the display. This controller is versatile, supporting resolutions for advanced displays including 4K and 8K, making it suitable for a myriad of demanding visual applications. Its architecture provides a 32/64/128/256/512-bit AXI4 interface to the memory controller and can drive 1/2/4/8 port display panel interfaces, accommodating diverse system layouts. Optional features include LVDS link layer interfaces and connections to MIPI DSI/DisplayPort/DVI/HDMI, enhancing its capability to support complex video requirements in high-resolution displays. For system developers, the DB9000AXI is accompanied by a comprehensive toolkit including a simulation test suite, Linux drivers, and Syntheses Design Constraints, ensuring that it fits into varied development environments efficiently. It is an optimal choice for high-performance processors such as ARM and is compatible with RISC-V or MIPS frameworks, boasting quality of service, superior burst length capability, and an extensive user manual to facilitate integration and development processes.
The RISC-V Hardware-Assisted Verification by Bluespec is a high-performance platform designed for swift and precise verification of RISC-V cores. It supports testing at both the core level (ISA) and system level, accommodating RTOS and Linux-based environments. This solution can verify standard ISA extensions, custom ISA extensions, and integrated accelerators, making it a versatile tool for various verification needs. One of the standout features of this platform is its scalability and accessibility via the AWS cloud, which ensures that resources can be tapped into as needed, enabling efficient verification anytime, anywhere. Such scalability is crucial for teams that require the flexibility to test various designs without being confined to local server limitations. With an emphasis on broad compatibility, the RISC-V Hardware-Assisted Verification platform is ideal for those involved in developing RISC-V based systems. It assists developers in ensuring their designs are accurate and reliable before deployment, reducing errors and speeding up time-to-market.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
The AON1100 offers a sophisticated AI solution for voice and sensor applications, marked by a remarkable power usage of less than 260μW during processing yet maintaining high levels of accuracy in environments with sub-0dB SNR. It is a leading option for always-on devices, providing effective solutions for contexts requiring constant machine listening ability.\n\nThis AI chip excels in processing real-world acoustic and sensor data efficiently, delivering up to 90% accuracy by employing advanced signal processing techniques. The AON1100's low power requirements make it an excellent choice for battery-operated devices, ensuring sustainable functionality through efficient power consumption over extended operational periods.\n\nThe scalability of the AON1100 allows it to be adapted for various applications, including smart homes and automotive settings. Its integration within broader AI platform strategies enhances intelligent data collection and contextual understanding capabilities, delivering transformative impacts on device interactivity and user experience.
APB4 GPIO by Roa Logic is a comprehensive and adaptable core that introduces a user-defined number of general-purpose, bidirectional input and output channels to designs. It provides a flexible interface for developers who require customizable GPIO settings in their embedded systems, making it suitable for a wide range of applications in different industry verticals.
The Universal Drive Controller is an advanced solution tailored for motion control applications across a range of motor types, including DC, BLDC, and stepper motors. It offers a comprehensive set of features that allows for independent position and velocity control of multiple motors directly from FPGA platforms. This flexibility makes it ideal for various industrial and commercial applications where precise motor control is paramount. With a focus on enhancing efficiency and performance, this controller simplifies the integration of motor control systems by providing a unified framework. It streamlines the management of complex control loops and ensures that each motor operates under optimal conditions. This results in improved operational stability and precision in movement, which is crucial for applications requiring high levels of accuracy. The design of the Universal Drive Controller is optimized for easy integration and configuration, supporting seamless implementation within existing setups. It promises to cut down development times and reduce complexities associated with traditional motor controller solutions. By utilizing FPGA technology, it offers a scalable and future-proof solution that can accommodate emerging requirements in motor control engineering.
Polybus Systems' InfiniBand Transport Layer Core is a pivotal component for data acquisition, high-performance computing, and networking setups. It supports user communication and remote direct memory access (RDMA) operations, enhancing the flexibility and efficiency of data management. With support for multiple virtual lanes and numerous queue pairs, this core is ideal for high-load network environments requiring responsive data pathways and reliable data delivery.
The Camera PHY Interface tailored for advanced semiconductor processes is integral for optimizing high-speed data transmission between image sensors and processors. Specialized to accommodate the latest advancements in process technology, this interface IP ensures superior performance while maintaining minimal power consumption and enhanced data integrity. By leveraging cutting-edge technology, it is engineered to handle multiple data lanes simultaneously, providing flexibility and adaptability across various applications in the visual data industry. This interface finds its utility in high-definition imaging solutions, contributing significantly to industries such as automotive, consumer electronics, medical imaging, and surveillance systems. Its design is aimed at simplifying integration in complex systems while providing robust data throughput and decreasing electromagnetic interference to ensure unmitigated signal clarity. With compatibility extending to the sub-LVDS, MIPI D-PHY, and HiSPi standards, this Camera PHY Interface IP is adaptable for evolving interface technologies, ensuring that devices can benefit from advanced connectivity protocols without compromising on performance metrics. The adoption of this IP supports industry trends towards miniaturization and reduced device footprints, thus making it indispensable for modern imaging solutions.
The IP Camera Front End from Bitec is tailored for optimizing CMOS sensor outputs, providing high-performance IP core solutions designed for digital video stream processing. Fully parameterized, this core supports a wide range of sensor types and configurations, making it adaptable to numerous application needs including surveillance, broadcasting, and consumer electronics. By integrating with Altera devices, the core offers streamlined processing, aligning with standard industry practices for image capture and processing. It ensures minimal latency and high efficiency in operating image pipelines, which is crucial for applications requiring real-time video analysis and transmission. This IP core's flexibility allows for significant customization, ensuring that it can be fine-tuned to meet the demands of diverse imaging tasks. By leveraging its parameterization capabilities, developers can optimize power consumption and data throughput, enhancing both the performance and efficiency of camera systems designed for various sectors.
Certus Semiconductor's Analog I/O offerings bring ultra-low capacitance and robust ESD protection to the forefront. These solutions are crafted to handle extreme voltage conditions while securing signal integrity by minimizing impedance mismatches. Key features include integrated ESD and power clamps, support for broad RF frequencies, and the ability to handle signal swings below ground. Ideal for high-speed RF applications, these Analog I/Os provide superior protection and performance, aligning with the most demanding circuit requirements.
The I/O semiconductor solutions from Analog Bits are designed to interface with multiple systems, ensuring seamless signal transmission across a variety of applications. These solutions offer a comprehensive range of features, including differential signaling and CMOS compatibility, enabling optimal communication within integrated circuits. By providing robust I/O management, these solutions help maintain signal integrity and efficiency. Analog Bits' I/O IP is distinguished by its adaptability to various process nodes, making it highly versatile in applications ranging from consumer electronics to industrial automation systems. The technology supports robust data transfer and is tailored to meet the demands of modern high-performance computing environments where quick, reliable communication interfaces are crucial. The solutions align with the complex requirements of contemporary digital systems, facilitating superior performance and power management. With features designed to minimize electromagnetic interference and ensure high fidelity in signal transmission, the I/O IP from Analog Bits is a pivotal component in the deployment of advanced semiconductor technologies.
Polybus Systems' InfiniBand Double Data Rate (DDR) Link Layer Core advances network infrastructure capabilities by supporting bidirectional speeds of 20 Gbits/second at an operational frequency of 250 MHz. Utilizing a 5 GHz SerDes, it integrates seamlessly with both FPGA designs, such as Xilinx Virtex and Altera Stratix series, and ASIC applications. This core is engineered for enhanced data throughput, enabling efficient data transmission across sophisticated electronic systems.
The logiCVC-ML is an advanced display controller that supports resolutions up to 2048x2048, tailored for TFT LCD displays. Optimized for AMD's Zynq 7000 AP SoC and FPGAs, this IP core is equipped with software drivers compatible with Linux, Android, and Windows Embedded Compact 7. This versatility ensures the logiCVC-ML can be implemented across a wide array of applications demanding high-resolution display capabilities. With a strong focus on integrating with existing systems, the logiCVC-ML offers multilayer video capabilities, making it ideal for complex display needs in various industries. Its support extends beyond simple display output, accommodating sophisticated graphics operations that enhance user experiences across diverse platforms. The IP core's efficient use of resources ensures minimal impact on overall system performance, allowing developers to allocate resources to other critical functions. The logiCVC-ML thus represents a blend of high performance and resource efficiency, making it a valuable component in any high-resolution display application.
Himax provides a comprehensive portfolio of display drivers designed for large-sized panels. These ICs are essential in applications such as LCD TVs, monitors, and notebooks, where they serve functions like timing control, source driving, and programming gamma/Vcom. Himax's display drivers are engineered to deliver excellent image quality, reliability, and compatibility with major panel makers situated in Korea, Taiwan, China, and Japan. By incorporating advanced technologies, these drivers support various resolution standards while maintaining efficient power consumption, which is crucial for large display panels. As a market leader, Himax continues to innovate in handling large formats, ensuring optimal performance and seamless integration in consumer electronics products. These drivers are tailored to deliver strong visual performance across a wealth of devices. Whether for automotive, consumer electronics, or TVs, Himax ensures that each display driver withstands the rigorous demands of high-definition content delivery. Their dedication to providing robust solutions is evidenced by their collaborations with leading display manufacturers globally, ensuring their products align with the evolving needs of end-users in different markets. Through a meticulous focus on innovation and quality control, Himax’s display drivers cater to critical industry standards while fostering outstanding performance enhancements. Their strategic approach ensures they remain at the forefront of the display technology domain, offering pioneering solutions that align with modern viewing preferences.
Specializing in advanced communication technologies, this module is tailored for WiFi6, LTE, and 5G networks. It is engineered to optimize RF front-end performance for next-generation wireless communication standards. This module ensures reliable and fast data transfer rates, crucial for applications ranging from mobile networks to IoT (Internet of Things) infrastructure, enabling high-speed connectivity and reduced latency.
Dedicated to enhancing camera interfacing, YouMIPI solutions include CSI and DSI interface technologies tailored to boost signal integrity and system integration. These solutions are designed to accommodate high-throughput requirements, fundamental for advanced multimedia communications.
The AON1020™ is engineered for superior voice and audio recognition alongside sensor-supported applications, forming an integral component of the AONSens™ Neural Network cores. It includes an AI processing engine supplied in Verilog RTL, viable for synthesis in ASIC products and FPGAs, plus dedicated software.\n\nDesigned for purposes such as voice control, context detection, and sensor applications, it supports always-on multi-wake-word detection and accurate voice command recognition. With features to differentiate and accurately detect context via various sensors, this processing engine ensures reliability in changing auditory environments.\n\nAON1020 demonstrates resilience against background noise and variability, delivering speaker-independent functionality. Optimized for detecting both single and multiple commands simultaneously, it addresses diverse needs efficiently, including human activity detecting tasks, leveraging high-accuracy algorithms in dynamic scenarios.
The D/AVE 2D core is tailored for delivering optimized 2D graphics performance across a broad range of devices. It supports essential 2D operations such as line drawing, shape filling, and image blitting, making it ideal for applications requiring crisp, clear visuals. This core is highly optimized for low power consumption, making it suitable for battery-operated devices. Moreover, its design ensures scalability, allowing for performance enhancement through additional features or integration with existing systems. The D/AVE 2D core is particularly beneficial for devices such as handhelds, tablets, and industrial equipment requiring robust graphical output with efficient resource use. Built for flexibility, it can integrate seamlessly with different hardware platforms, supporting various interfaces and display types.
The ARINC 664 P7 IP Core by iWave Global is at the forefront of aviation network solutions, offering an advanced platform for Ethernet-based communication in aerospace systems. Known for adhering to stringent industry standards, this IP core provides reliable and efficient communication protocols essential for avionics Ethernet networks. It effectively manages high-speed data across network infrastructures, paving the way for streamlined operations within aircraft systems. The core supports features essential for critical networked systems, such as bandwidth allocation, prioritization of data flows, and quality of service mechanisms. Ideal for enhanced networking capabilities in aircraft, the ARINC 664 P7 IP Core ensures data communication integrity, which is essential for the safety-critical operations found in modern aviation environments. This core is crucial for developers aiming to create sophisticated onboard systems that require precise and dependable data exchange mechanisms.
Genesis stands out as a comprehensive suite tailored for package and PCB design, addressing the intricacies involved in modern electronic design processes. Embodying a variety of functionalities, Genesis supports the full design cycle—from conceptualization to verification—ensuring that complex electronic systems are optimized for performance and manufacturability. Its robust platform includes design, analysis, and integration capabilities that cater to the diverse needs of the electronics industry. A key aspect of Genesis is its ability to streamline the integration of components in multilayer PCBs and advanced semiconductor packages. This reduces design cycles and enhances the reliability of final products, crucial in high-stakes fields like telecommunications and computing. The suite's powerful analysis tools provide engineers with insights into electromagnetic compatibility, signal integrity, and thermal performance, facilitating early-stage problem detection and correction. The Genesis suite collaborates effectively with other Xpeedic tools, creating a cohesive ecosystem for electronic designers. Its advanced simulation capabilities ensure that products are ready for today's demanding markets, emphasizing electrical performance and compliance with stringent industry standards. Genesis exemplifies Xpeedic's commitment to delivering superior design solutions that meet the rapidly evolving needs of technology innovators.
Domain-Specific RISC-V Cores from Bluespec provide targeted acceleration for specific application areas by packaging accelerators as software threads. This approach enables developers to achieve systematic hardware acceleration, improving the performance of applications that demand high computational power. These cores are designed to support scalable concurrency, which means they can efficiently handle multiple operations simultaneously, making them ideal for complex scenarios that require high throughput and low latency. The ease of scalability ensures that developers can rapidly adapt their designs to meet evolving demands without extensive redesign. Bluespec’s domain-specific cores are well-suited for specialized markets where performance and efficiency can make a significant impact. By providing a robust platform for acceleration, Bluespec empowers developers to create competitive and rapidly deployable solutions.
The ARINC 818-2 IP Core by iWave Global is engineered to support the high-speed video interface standard used in aerospace applications. This IP core signifies a leap in the integration of advanced video transmission protocols with existing avionics architectures. It is tailored for applications that demand highly reliable and efficient video data communications. Focusing on seamless compatibility, the ARINC 818-2 IP Core integrates easily into various platforms, ensuring minimal modifications and reduced time-to-market for development. This core supports high-speed data transfer rates, providing robust solutions for real-time video streaming and data transfer. Ideal for systems requiring precise video data handling, the ARINC 818-2 IP Core guarantees data integrity and synchronization across all transmission stages. Its versatile design allows for broad implementation across military and commercial aviation sectors, where data reliability and transfer efficiency are paramount.
The Capacitive Proximity Switch from Microdul is an energy-efficient solution for detecting touch and proximity in electronic devices. This switch is characterized by its low power requirements, aiding in the extension of battery life for handheld and portable gadgets. Its adaptability allows it to be used for single keys, keypads, sliders, or proximity switches. The device can efficiently distinguish between different types of touch events, helping select features or wake up devices without unnecessary energy consumption.
The InfiniBand Quad Data Rate (QDR) Link Layer Core from Polybus Systems is designed to provide top-tier performance for high-speed network applications. This core operates at 500 MHz in ASIC formats and 250 MHz in FPGA implementations, supporting data rates of up to 80 Gbits/second in ASICs and versatile operation modes in FPGAs. The core's peripheral component interconnect and sequencing (PCS) layer compatibility allows it to work efficiently with leading FPGA series, including Xilinx Kintex7 and Virtex7, as well as Altera Stratix devices.
ViaExpert is an essential tool for engineers dealing with via modeling tasks in PCB design and semiconductor applications. This tool is tailored to model vias—conductive pathways through the board substrates—ensuring they meet critical signal integrity and performance standards. Accurate via modeling is paramount in the design of high-frequency PCBs and multilayer boards where parasitic inductance and capacitance can significantly impact functionality. With ViaExpert, users benefit from an enhanced simulation environment that delivers precise characterizations of via structures under various operating conditions. This capability is particularly beneficial in anticipating and mitigating potential issues such as signal distortion and cross-talk between layers. By simulating real-world conditions, engineers can optimize the via design to meet stringent design specifications and reliability standards. This tool's integration capacity with other simulation platforms allows for a holistic approach to electronic design, where via performance is evaluated alongside other components in a system. This ensures that all aspects of electrical performance are considered, thus contributing to the quicker development of robust and efficient electronic designs.
The Guiliani GUI Framework is a comprehensive solution for developing sophisticated graphical user interfaces tailored for embedded systems. Featuring an intuitive design environment, it allows for the creation of innovative and responsive GUIs across various hardware platforms. The framework supports a wide range of widgets and controls, offering developers the flexibility to craft tailored user interfaces that enhance the user experience. The Guiliani software is engineered to optimize performance while maintaining low-resource utilization, ensuring smooth and efficient operation on devices with constrained computing power. With its wide compatibility and extensive functionality, the framework is perfect for industrial, consumer, and automotive applications where an engaging and functional user interface is essential.
The IMG DXS GPU is designed to meet the safety and performance demands of automotive applications with a focus on advanced driver assistance systems (ADAS). Featuring a multi-core architecture with built-in functional safety mechanisms, it allows for efficient handling of mixed-criticality workloads. Its distributed safety mechanisms enable significant reductions in silicon area and power consumption, making it ideal for safety-critical environments. This GPU excels in providing high-performance visuals for in-car systems like digital instrument clusters and heads-up displays. With ISO 26262 functional safety certification, it meets stringent automotive industry standards, ensuring reliability even in fault scenarios. The IMG DXS GPU supports a wide range of graphical applications, from infotainment to vital safety systems, with hardware-accelerated graphics rendering capabilities. It is engineered for seamless integration into automotive systems, offering robust performance while maintaining energy efficiency.
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