TT-Ascalon™ is a versatile RISC-V CPU core developed by Tenstorrent, emphasizing the utility of open standards to meet a diverse array of computing needs. Built to be highly configurable, TT-Ascalon™ allows for the inclusion of 2 to 8 cores per cluster complemented by a customizable L2 cache. This architecture caters to clients seeking a tailored processing solution without the limitations tied to proprietary systems.
With support for CHI.E and AXI5-LITE interfaces, TT-Ascalon™ ensures robust connectivity while maintaining system integrity and performance density. Its security capabilities are premised on equivalent RISC-V primitives, ensuring a reliable and trusted environment for operations involving sensitive data.
Tenstorrent’s engineering prowess, evident in TT-Ascalon™, has been shaped by experienced personnel from renowned tech giants. This IP is meant to align with various performance targets, suited for complex computational tasks that demand flexibility and efficiency in design.
