Sofics has verified its ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces.
The Analog I/O clamp described in this document can be used for 3.3V pads in the TSMC 7nm FinFET technology. The ESD clamp is designed to provide 2kV HBM protection for 3.3V interfaces. It features a small silicon footprint.
