TimeServo serves as a precise FPGA system timer or clock that supports line-rate independent packet timestamping while addressing high-resolution, modest accuracy timekeeping needs. Engineered with a PI-DPLL, it synchronizes local TCXO with an external 1 PPS signal, enabling high syntonicity and facilitating accurate timestamping with MAC-integrated environments. The component can be extended to TimeServoPTP for a fully compliant IEEE-1588v2/PTP configuration, creating a standalone slave device without the need for host intervention.
Providing up to 32 runtime-tunable outputs, TimeServo operates independently across diverse clock domains and supports various output formats including binary, IEEE ordinary, and transparent. Management and observability through an AXI control plane enable dynamic time adjustments and phase-frequency monitoring, ensuring operational adaptability. The attribute of using a standard AXI4-Lite interface strengthens integration prospects with existing FPGA setups.
TimeServo's robust phase lock capabilities are backed by a 120-bit resolution phase accumulator and phase-locked loop (PLL) systems capable of maintaining jitter accuracy and flexibility. The design advances are supplemented with application examples and software tools to ease setup and implementation, supporting a wide range of time-sensitive industrial applications.
