The Synthesizable Programmable Core (SPC) offered by ADICSYS is a sophisticated soft FPGA IP aimed at enhancing flexibility and extending the lifecycle of ASICs. This core diminishes the risk of errors, adapts rapidly to evolving specifications, and accelerates the time to market. It supports RTL-level decision-making, allowing modifications even in later development phases, thereby reducing delays and costs associated with design changes.
SPC's advantage is underscored by its complete compatibility with standard ASIC CAD tools, providing a seamless integration into the existing ASIC workflow without constraints on the design process. Its reliance on standard cells for eFPGA construction also reduces the gap between standard and custom cell designs, making high-risk and high-cost full-custom designs a thing of the past.
Built to support the challenges of modern technology nodes, SPC allows for enhanced backend access, simulation, synthesis, and testing. It offers immediate flexibility for late-stage semiconductor design decisions and can be tailored to fit varying scales and amounts of SPCs within a given project, thus promoting effective and efficient integration in a variety of silicon environments.
