All IPs > Memory & Logic Library > Standard cell > Standard Cell Library
The Standard Cell Library (STD-Cell Library) from the offering includes a range of design tools aimed at optimizing performance, power, and area parameters in chip design. It features a broad array of standard cells and supports customization for more complex application needs. This library forms the core of foundational IP, providing essential building blocks to enhance the chip design framework and integrate efficiently within various process nodes.
| Foundry | Process Nodes |
|---|---|
| TSMC |
28nm 40nm 55nm 180nm |
| Class | Value |
|---|---|
| Categories |
Memory & Logic Library > Standard cell |
| Optimization Kits | Power Manage Kit, Low Power Optimization Kit, High Performance Kit |
| Availability | All Countries & Regions |
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