The RV32IC_P5 processor core is tailored for medium-scale embedded applications that require enhanced performance. Featuring a 5-stage pipeline, this RISC-V processor supports a wider range of applications due to its ability to handle both trusted firmware and user-level applications. Enhanced with machine-mode and user-mode privileged architecture, it is compliant with RISC-V Privileged Architecture Version 1.10. The core offers optional support for branch prediction and data cache memories, delivering high-speed processing capabilities. With its sophisticated design, it is suitable for ASIC and FPGA-based implementations, supporting various execution contexts through an array of configurable options such as interrupt management and memory protection.
