The RV32IC_P5 Processor Core is a high-performance, 5-stage pipeline RISC-V processor designed to support medium-scale embedded systems that demand elevated performance levels. It features capabilities like caching and support for both trusted firmware and general user applications. Using the RISC-V RV32I base instruction set, this core complies with the RISC-V User-Level ISA V 2.2 and introduces several optional standard extensions.
The processor includes "A" standard extensions, which aid in critical section handling in uniprocessor systems, and support for RVC standard compressed instructions to optimize code size. Developed with both machine-mode and user-mode privileged architectures, it ensures direct physical memory access while supporting potential application-specific DSP operations through customizable instruction set extensions.
It is equipped with a robust interrupt handling mechanism, including vectoring of interrupts and exceptions delegated to user mode, allowing for expedited response times. Its power efficiency is maintained by a wait-for-interrupt instruction that enables clock gating during low-power idle states, and it interfaces through AHB-Lite paths for extended memory and memory-mapped I/O access.
