The RV32EC_P2 core is a streamlined 2-stage pipeline RISC-V processor core aimed at small, low-power embedded applications. This processor core is designed to run only trusted firmware and can be implemented in both ASIC and FPGA-based design flows. It is compliant with RISC-V User-Level ISA V2.2, incorporating standard compressed instructions to minimize code size and optional integer multiplication and division instructions for flexibility. With a simple machine-mode privileged architecture, it supports direct physical memory addressing, along with an external interrupt controller for expanded interrupt handling. The core also integrates tightly-coupled memory interfaces and a low-power idle state option, making it highly adaptable for various low-energy applications.
