Riviera-PRO is designed to address the rigorous verification requirements of engineers working on advanced FPGA and System-on-Chip (SoC) designs. It enhances testbench productivity, usability, and automation by combining a high-performance simulation engine with robust debugging capabilities. Engineers benefit from Riviera-PRO's support for advanced verification methodologies, such as Universal Verification Methodology (UVM), allowing for efficient testbench reusability and comprehensive debugging across different abstraction levels.
