IQonIC Works’ RISC-V Platform-Level Interrupt Controller (PLIC) IP is designed in adherence to the RISC-V PLIC specification for managing numerous interrupt sources in systems featuring multiple processor targets. This controller is highly configurable, allowing adjustments to match the specifics of an application's interrupt source and target requirements.
The PLIC supports a configurable number of interrupt sources, ranging from 31 to as many as 1023, catering to a wide array of potential system demands. Its capability extends to supporting numerous target hart contexts and multiple priority levels, making it an adaptable solution for differing project complexities. Each interrupt source can be tailored for synchronous or asynchronous signals, and sensitivity choices include level and edge (rising/falling) detection.
The interrupt controller is equipped with an AHB-Lite interface to facilitate register access for setting and managing priorities, enabling or disabling interrupts, and co-ordinating the handling of claims and completions of interrupts. This makes the PLIC vital for applications where robust, secure, and efficient management of interrupts is critical, aiding in the seamless operation of complex embedded systems.
