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All IPs > Analog & Mixed Signal > Clock Synthesizer > pPLL05 Family

pPLL05 Family

From Perceptia Devies Australia

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Description

Designed for low power applications, the pPLL05 family boasts an all-digital Fractional-N PLL architecture that operates efficiently at frequencies up to 1GHz. Offering minimal power consumption at less than 1mW, it is well-suited for IoT and embedded systems where energy efficiency is critical. The bright spot of this family is its compact design, occupying less than 0.01 square millimeters, while maintaining low jitter levels.

Implemented across multiple foundry process nodes, the pPLL05's technology is flexible and adaptable to various manufacturing environments. Its small size and power efficiency enable broader application, providing significant advantages in systems where battery life and thermal management are paramount.

The pPLL05 supports both integer-N and fractional-N operations, delivering a high degree of flexibility in clocking configurations. The PLL complements systems that require precise cyclic operations while ensuring reliability and integration ease. As with all Perceptia PLLs, it integrates seamlessly within larger SoCs, featuring industry-standard test and verification setups.

Features
  • Low Power
  • Small size
Foundries & Process Nodes
Foundry Process Nodes
Samsung 40nm
TSMC 28nm
Tech Specs
Class Value
Categories Analog & Mixed Signal > Clock Synthesizer
Analog & Mixed Signal > PLL
Interface Controller & PHY > AMBA AHB / APB/ AXI
Graphic & Peripheral > Clock Generator
Jitter Low
Die Area < 0.01 sq mm
Power < 1.0mW
Power (W) <1W
Availability All Countries & Regions
Applications
  • IoT
  • Embedded
  • Moderate speed digital systems
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