The pPLL02F family from Perceptia is engineered to serve as general-purpose all-digital Fractional-N PLLs suitable for moderate-speed digital systems and logic clocking. Designed with versatility in mind, this PLL range is ideal for clocking microprocessor blocks and mixed-domain systems. It boasts a compact footprint, occupying less than 0.01 square millimeters, while maintaining low power consumption, typically under 3.5 milliwatts. These PLLs integrate seamlessly into system-on-a-chip (SoC) designs, accommodating multiple domains by allowing instances of the PLL to share power supplies or integrate with existing power architecture.
The family is founded on Perceptia's second-generation all-digital PLL technology, which ensures consistent performance across various manufacturing processes, unaffected by variations in process, voltage, or temperature. The integration of these PLLs is straightforward, aided by comprehensive design support including all necessary models and verification reports for backend procedures. In fractional-N mode, the pPLL02F family offers flexibility in clock frequency modulation, ensuring precise fit for demanding timing scenarios.
Available across several foundry processes, from 5nm to 40nm, the pPLL02F family provides support for multiple designs and platforms, with proven silicon across major industry players. It's a robust solution for systems requiring multiple PLL operations, offering features like low jitter and high integration capabilities. These characteristics make the pPLL02F family a practical choice for designers seeking a balance between area efficiency, power conservation, and performance in their clocking solutions.
