PowerMiser represents a leading-edge Low Power SRAM IP designed for advanced devices that require extended battery life with minimal operational and standby power usage. PowerMiser is effectively utilised across several manufacturing processes including 28nm FDSOI, 28nm HDC+, and 22nm ULL BULK CMOS. It offers remarkable dynamic power savings of over 50% compared to its commercial counterparts and achieves substantial leakage power reductions depending on the operating environment. Even with its significant power-saving capabilities, PowerMiser incurs only a slight area penalty, catering to the dense requirements of modern systems.
The PowerMiser compilers are highly versatile, supporting large capacities and offering various trade-offs between word numbers, lengths, and multiplexing factors. This flexibility is crucial in managing the intricate needs of contemporary SoCs, ensuring power efficiency without performance compromise. Moreover, PowerMiser's architecture eliminates the need for power-intensive level shifters, further optimising power consumption for applications demanding rigorous efficiency such as edge-AI deployments.
Standing out with a retentive sleep mode feature, PowerMiser ensures rapid wake-up times and maximal leakage current savings. Its innovative design techniques paired with SureCore’s extensive expertise in power management lead to a unique product that significantly reduces the energy footprint of embedded systems, allowing manufacturers to meet the ever-tightening energy standards of today's market.
