PowerMiser is sureCore's flagship low-power SRAM product designed to meet the demands of devices requiring extended battery life and minimal power draw both in operation and standby. Leveraging processes such as 28nm FDSOI, 28nm HDC+, and 22nm ULL BULK CMOS, this SRAM achieves substantial power savings of over 50% in dynamic power, due in part to its wide operating voltage range from 0.7V to 1.2V. PowerMiser also manages significant reductions in leakage power, ranging from 38% to 21%, depending on operating conditions, incurring a marginal area increase of 5-10%. Supporting capacities up to 576Kbit and offering flexibility with three multiplexing factors, the PowerMiser compiler optimizes trade-offs in SRAM design and facilitates standard EDA tool flows.
With a patented "Bit Line Voltage Control" technique, PowerMiser ensures no performance is sacrificed at lower voltages. It also features versatile retentive sleep modes, including light and deep sleep, helping conserve power while maintaining swift wake-up times. These attributes make PowerMiser an attractive solution for constructs with substantial SRAM usage, particularly in AI edge devices where power efficiency is paramount.
The architecture of PowerMiser, coupled with a minimal differential between core array and peripheral supplies, allows synchronous operation without power-hungry level shifters. Developers are afforded the capability to adjust both logic and memory voltages in tandem, aligning performance and power consumption adjustments with application requirements. As the drive for longer battery operation continues, PowerMiser presents as a crucial component in reducing the traditionally high power drain of embedded SRAM, especially pertinent for the applications that form the rapidly evolving technological landscape.
