All IPs > Interface Controller & PHY > PCI > PCIe Gen1/2 PHY
Complying with the PCI-SIG's PCIe v2.0 specifications, this PCIe PHY core features a configurable PIPE interface and supports a broad range of computing applications. Its architecture minimizes gate count while maximizing efficiency, with synchronized state machine transitions and an 8b/10b encoder/decoder included. The design is built to meet the demands of PCIe infrastructures, providing robust connectivity and high data transfer rates in a compact form factor.
| Class | Value |
|---|---|
| Categories |
Interface Controller & PHY > PCI Interface Controller & PHY > D2D |
| Availability | All Countries & Regions |
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