All IPs > Interface Controller & PHY > PCI > PCIe Gen1/2 PHY
The PCIe Gen1/2 PHY IP core is compliant with the PCIe v2.0 specifications, featuring PIPE interface flexibility and minimal gate count architecture. It is capable of generating a comprehensive set of Ordered Sets required for PCIe standards and includes an IBM-compatible 8b/10b Encoder and Decoder. This core ensures high interoperability and performance for next-generation PCIe devices, serving as a critical component in high-speed data and networking interfaces.
| Class | Value |
|---|---|
| Categories |
Interface Controller & PHY > PCI Interface Controller & PHY > D2D |
| Availability | All Countries & Regions |
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