The PCIe Gen 6 Verification IP from Truechip offers support for high data rates of 64.0 GT/s per lane and is designed to be backward compatible. This IP integrates new PAM4 signaling, enhancing data transmission integrity, along with Gray coding for improved error correction. It accommodates both Flit mode and Non-Flit mode operations, facilitating diverse applications and systems requirements. A notable feature of this IP is its support for TS0 ordered set, enabling enhanced equalization at 64bit, which is crucial for maintaining high-performance levels in complex systems. Truechip’s verification IPs are built with comprehensive protocol checkers, making use of SystemVerilog and UVM, thus ensuring easy integration into existing verification flows. By offering full debug capabilities and functional coverage, the PCIe Gen 6 Verification IP is ideal for designers looking to innovate while minimizing the risk of errors in high-speed serial protocol implementation.
