Truechip's PCIe Gen 6 Verification IP is crafted to rigorously test and verify devices adhering to the PCI Express (PCIe) Gen 6 standard. It supports verification processes targeted at high-speed data transactions, handling a data rate of 64.0 gigatransfers per second per lane. This IP is backward compatible with previous PCIe generations, ensuring smooth transitions and flexible integration into existing systems.
One of the standout features of this Verification IP is its capacity to support new PCIe 6.0 specifications, such as PAM4 signaling and Gray coding, both of which are crucial for improved data integrity and speed. The IP also facilitates verification in Flit Mode and Non-Flit Mode, allowing comprehensive coverage for various operational scenarios. The inclusion of advanced features like the TS0 ordered set ensures efficient communication across the PCIe link, emphasizing equalization at 64-bit intervals.
This Verification IP benefits from Truechip's hallmark attributes like full protocol checkers, extensive functional coverage, and a user-friendly interface. These features help design engineers ensure their designs meet PCIe standards efficiently. Moreover, the IP integrates with standard SystemVerilog/UVM flows, providing seamless incorporation into existing verification environments. Its robustness and versatility make it a valuable tool in any verification suite supporting PCIe technology.
