Truechip’s NoC Verification IP provides a powerful solution for the verification of Network-on-Chip designs, supporting multi-protocol NoC ports. Each interface is capable of managing different protocols, which allows for the verification of segmented slave memories. The NoC Verification IP includes a comprehensive suite of test scenarios and coverage models, enabling users to tailor sequences to their specific environments.
This sophisticated IP is optimized for integration in both standalone NoC blocks and complex SoC designs, compliant with latest ARM bus protocols like AHB, AXI, and SiFive TileLink among others. Key features include customizable slave port addresses, priority settings, and QoS support throughout the NoC. Its detailed protocol monitoring ensures data integrity and extends support for both logical and physical address conversions, making it indispensable for modern high-performance networks.
